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From: "Mylène Josserand" <mylene.josserand@bootlin.com>
To: linux@armlinux.org.uk, maxime.ripard@bootlin.com, wens@csie.org,
	marc.zyngier@arm.com, mark.rutland@arm.com, robh+dt@kernel.org,
	horms@verge.net.au, geert@linux-m68k.org, magnus.damm@gmail.com
Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
	clabbe.montjoie@gmail.com, quentin.schulz@bootlin.com,
	thomas.petazzoni@bootlin.com,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, mylene.josserand@bootlin.com
Subject: [PATCH v8 05/12] ARM: dts: sun8i: a83t: Add CCI-400 node
Date: Tue,  1 May 2018 14:31:24 +0200	[thread overview]
Message-ID: <20180501123131.7738-6-mylene.josserand@bootlin.com> (raw)
In-Reply-To: <20180501123131.7738-1-mylene.josserand@bootlin.com>

Add CCI-400 node and control-port on CPUs needed by SMP bringup.

Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 41 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 53ace066b7dc..0669b8dc499d 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -66,6 +66,7 @@
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
 			operating-points-v2 = <&cpu0_opp_table>;
+			cci-control-port = <&cci_control0>;
 			reg = <0>;
 		};
 
@@ -73,6 +74,7 @@
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
 			operating-points-v2 = <&cpu0_opp_table>;
+			cci-control-port = <&cci_control0>;
 			reg = <1>;
 		};
 
@@ -80,6 +82,7 @@
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
 			operating-points-v2 = <&cpu0_opp_table>;
+			cci-control-port = <&cci_control0>;
 			reg = <2>;
 		};
 
@@ -87,6 +90,7 @@
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
 			operating-points-v2 = <&cpu0_opp_table>;
+			cci-control-port = <&cci_control0>;
 			reg = <3>;
 		};
 
@@ -96,6 +100,7 @@
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
 			operating-points-v2 = <&cpu1_opp_table>;
+			cci-control-port = <&cci_control1>;
 			reg = <0x100>;
 		};
 
@@ -103,6 +108,7 @@
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
 			operating-points-v2 = <&cpu1_opp_table>;
+			cci-control-port = <&cci_control1>;
 			reg = <0x101>;
 		};
 
@@ -110,6 +116,7 @@
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
 			operating-points-v2 = <&cpu1_opp_table>;
+			cci-control-port = <&cci_control1>;
 			reg = <0x102>;
 		};
 
@@ -117,6 +124,7 @@
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
 			operating-points-v2 = <&cpu1_opp_table>;
+			cci-control-port = <&cci_control1>;
 			reg = <0x103>;
 		};
 	};
@@ -354,6 +362,39 @@
 			reg = <0x01700000 0x400>;
 		};
 
+		cci@1790000 {
+			compatible = "arm,cci-400";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x01790000 0x10000>;
+			ranges = <0x0 0x01790000 0x10000>;
+
+			cci_control0: slave-if@4000 {
+				compatible = "arm,cci-400-ctrl-if";
+				interface-type = "ace";
+				reg = <0x4000 0x1000>;
+			};
+
+			cci_control1: slave-if@5000 {
+				compatible = "arm,cci-400-ctrl-if";
+				interface-type = "ace";
+				reg = <0x5000 0x1000>;
+			};
+
+			pmu@9000 {
+				compatible = "arm,cci-400-pmu,r1";
+				reg = <0x9000 0x5000>;
+				interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
 		syscon: syscon@1c00000 {
 			compatible = "allwinner,sun8i-a83t-system-controller",
 				"syscon";
-- 
2.11.0

WARNING: multiple messages have this Message-ID
From: mylene.josserand@bootlin.com (Mylène Josserand)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v8 05/12] ARM: dts: sun8i: a83t: Add CCI-400 node
Date: Tue,  1 May 2018 14:31:24 +0200	[thread overview]
Message-ID: <20180501123131.7738-6-mylene.josserand@bootlin.com> (raw)
In-Reply-To: <20180501123131.7738-1-mylene.josserand@bootlin.com>

Add CCI-400 node and control-port on CPUs needed by SMP bringup.

Signed-off-by: Myl?ne Josserand <mylene.josserand@bootlin.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 41 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 53ace066b7dc..0669b8dc499d 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -66,6 +66,7 @@
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
 			operating-points-v2 = <&cpu0_opp_table>;
+			cci-control-port = <&cci_control0>;
 			reg = <0>;
 		};
 
@@ -73,6 +74,7 @@
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
 			operating-points-v2 = <&cpu0_opp_table>;
+			cci-control-port = <&cci_control0>;
 			reg = <1>;
 		};
 
@@ -80,6 +82,7 @@
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
 			operating-points-v2 = <&cpu0_opp_table>;
+			cci-control-port = <&cci_control0>;
 			reg = <2>;
 		};
 
@@ -87,6 +90,7 @@
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
 			operating-points-v2 = <&cpu0_opp_table>;
+			cci-control-port = <&cci_control0>;
 			reg = <3>;
 		};
 
@@ -96,6 +100,7 @@
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
 			operating-points-v2 = <&cpu1_opp_table>;
+			cci-control-port = <&cci_control1>;
 			reg = <0x100>;
 		};
 
@@ -103,6 +108,7 @@
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
 			operating-points-v2 = <&cpu1_opp_table>;
+			cci-control-port = <&cci_control1>;
 			reg = <0x101>;
 		};
 
@@ -110,6 +116,7 @@
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
 			operating-points-v2 = <&cpu1_opp_table>;
+			cci-control-port = <&cci_control1>;
 			reg = <0x102>;
 		};
 
@@ -117,6 +124,7 @@
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
 			operating-points-v2 = <&cpu1_opp_table>;
+			cci-control-port = <&cci_control1>;
 			reg = <0x103>;
 		};
 	};
@@ -354,6 +362,39 @@
 			reg = <0x01700000 0x400>;
 		};
 
+		cci at 1790000 {
+			compatible = "arm,cci-400";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x01790000 0x10000>;
+			ranges = <0x0 0x01790000 0x10000>;
+
+			cci_control0: slave-if at 4000 {
+				compatible = "arm,cci-400-ctrl-if";
+				interface-type = "ace";
+				reg = <0x4000 0x1000>;
+			};
+
+			cci_control1: slave-if at 5000 {
+				compatible = "arm,cci-400-ctrl-if";
+				interface-type = "ace";
+				reg = <0x5000 0x1000>;
+			};
+
+			pmu at 9000 {
+				compatible = "arm,cci-400-pmu,r1";
+				reg = <0x9000 0x5000>;
+				interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
 		syscon: syscon at 1c00000 {
 			compatible = "allwinner,sun8i-a83t-system-controller",
 				"syscon";
-- 
2.11.0

  parent reply	other threads:[~2018-05-01 12:34 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-05-01 12:31 [PATCH v8 00/12] Sunxi: Add SMP support on A83T Mylène Josserand
2018-05-01 12:31 ` Mylène Josserand
2018-05-01 12:31 ` [PATCH v8 01/12] ARM: Allow this header to be included by assembly files Mylène Josserand
2018-05-01 12:31   ` Mylène Josserand
2018-05-01 12:31 ` [PATCH v8 02/12] ARM: sunxi: smp: Move assembly code into a file Mylène Josserand
2018-05-01 12:31   ` Mylène Josserand
2018-05-02 13:18   ` Maxime Ripard
2018-05-02 13:18     ` Maxime Ripard
2018-05-01 12:31 ` [PATCH v8 03/12] ARM: dts: sun8i: Add CPUCFG device node for A83T dtsi Mylène Josserand
2018-05-01 12:31   ` Mylène Josserand
2018-05-01 12:31 ` [PATCH v8 04/12] ARM: dts: sun8i: Add R_CPUCFG device node for the " Mylène Josserand
2018-05-01 12:31   ` Mylène Josserand
2018-05-01 12:31 ` Mylène Josserand [this message]
2018-05-01 12:31   ` [PATCH v8 05/12] ARM: dts: sun8i: a83t: Add CCI-400 node Mylène Josserand
2018-05-01 12:31 ` [PATCH v8 06/12] ARM: smp: Add initialization of CNTVOFF Mylène Josserand
2018-05-01 12:31   ` Mylène Josserand
2018-05-01 12:31 ` [PATCH v8 07/12] ARM: sunxi: " Mylène Josserand
2018-05-01 12:31   ` Mylène Josserand
2018-05-02 13:08   ` Maxime Ripard
2018-05-02 13:08     ` Maxime Ripard
2018-05-02 13:28     ` Mylène Josserand
2018-05-02 13:28       ` Mylène Josserand
2018-05-01 12:31 ` [PATCH v8 08/12] ARM: sun9i: smp: Rename clusters's power-off Mylène Josserand
2018-05-01 12:31   ` Mylène Josserand
2018-05-01 12:31 ` [PATCH v8 09/12] ARM: sun9i: smp: Add is_a83t field Mylène Josserand
2018-05-01 12:31   ` Mylène Josserand
2018-05-02 13:09   ` Maxime Ripard
2018-05-02 13:09     ` Maxime Ripard
2018-05-01 12:31 ` [PATCH v8 10/12] ARM: sun8i: smp: Add support for A83T Mylène Josserand
2018-05-01 12:31   ` Mylène Josserand
2018-05-02 13:14   ` Maxime Ripard
2018-05-02 13:14     ` Maxime Ripard
2018-05-01 12:31 ` [PATCH v8 11/12] ARM: dts: sun8i: Add enable-method for SMP support for the A83T SoC Mylène Josserand
2018-05-01 12:31   ` Mylène Josserand
2018-05-01 12:31 ` [PATCH v8 12/12] ARM: shmobile: Convert file to use cntvoff Mylène Josserand
2018-05-01 12:31   ` Mylène Josserand
2018-05-02  6:36   ` Simon Horman
2018-05-02  6:36     ` Simon Horman
2018-05-02 13:18     ` Maxime Ripard
2018-05-02 13:18       ` Maxime Ripard

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