[PATCH v7 0/5] mtd: Add a SPI NAND driver

[PATCH v7 0/5] mtd: Add a SPI NAND driver

[Boris Brezillon]

Hello,

This is a brand new version of the SPI NAND framework initially
proposed by Peter. Note that this version has little in common with the
previous one, mainly because it's been reworked to use the SPI mem
interface (which allowed us to get rid of the complex NAND
initialization/registration logic).

Also, this version now natively supports on-die ECC and multi-die chips
(which was required to expose the 256MB of the W25M02GV chip). I know I
initially asked Peter to not support on-die ECC in the first version
of the framework so that we can work on a proper abstraction for ECC
controllers, but I ended up implementing it, since all the chips seem
to have on-die ECC and the implementation was not that complicated.

I'm not giving up on the "ECC controller abstraction" stuff, but with
this initial implementation we at least have usable SPI NAND support,
which should give us some time for complex setups with external ECC
controllers.

Just a few details about the patches in this series:

Patch 1 is just extending the nand_page_io_req structure to pass
information about the access mode (ECC enabled/disabled) so that we
can use that in the SPI NAND framework to decide whether on-die ECC
should be enabled or not.

Patch 2 is adding the core infrastructure to handle SPI NANDs, and
patch 3 is decribing the SPI NAND bindings.

Patch 4 and 5 add support for 2 different chips, one from Micron and
one from Winbond.

Comments/reviews are welcome.

Thanks,

Boris

v7 changes:
- Use the spi-mem interface
- Add support for on-die ECC
- Add support for Winbond W25M02GV chip

v6 changes:
- includes generic NAND framework patches in series
- rebase on nand/next (commit 6076fd1e9d879521f7082a5e22185b71e480b777)
- remove on-die ECC support
- remove devm_free() since everything allocated by devm_kmalloc() will be
  automatically freed when device is released
- add comment header for structs in spinand.h
- remove spinand_register()/unregister(), call spinand_detect() in
  spinand_init() and only expose spinand_init()/cleanup()
- add nand_release_bbt() in bbt.c and use it in nand_cleanup() and
  spinand_cleanup()
- use BIT(n) instead (1 << n) in macro of spinand.h
- rename spinand_alloc() to devm_spinand_alloc()
- name lables in better way
- fix some typos
- add empty lines between code blocks

v5 changes:
- rebase patch on nand/next with Boris's generic NAND framework patches[3]
- replace pr_xxx() with dev_xxx()
- replace kzalloc()i/kfree() with devm_kzalloc()/devm_kfree()
- rename spinand_op_init() to spinand_init_op() for consistency
- remove command opcode in function comments
- use BIT(n) instead (1 << n) in macro
- remove manufactures.c and put spinand_manufacturers table in core.c
- change spinand_write_reg() u8 *buf argument to u8 value,
  since the length is always 1
- remove spinand_manufacture->detect() check, since it is always != NULL
- alloc spinand_ecc_engine struct in vendor.c when using on-die ECC
  (for hardware ECC, it should be in controllers/*.c)
- add comment header for struct spinand_op
- fix timeout bug in spinand_wait(), thanks for Arnaud's debug
- make spinand_manufacturers const
- add ecc_engine_ops pointer in struct micron_spinand_info
- make controller->cap assignment right with SPI_TX/RX_QUAD/DUAL flag

v4 changes:
- initialize struct mtd_oob_ops to 0 in bbt.c
- rename new added helper in nand.h to nand_check_xxxx()
- add struct mtd_oob_ops consistency check in nand_check_oob_ops()
- add dataleft in struct nand_page_iter instead of offs
- remove spinand_manufacturers->ops->detect() check since it is mandatory
- remove spinand_set_manufacturer_ops() and do the job in
  spinand_manufacturer_detect()
- move .priv out of struct spinand_controller
- add spinand_alloc/free/register/unregister() and make
  spinand_detect/init() static
- make BBT be configured by device tree
- chip->id.data stores raw ID directly
- refine device info print message after detect success
- add struct mtd_layout_ops pointer in struct micron_spinand_info
- remove micron_spinand_init() and do its job in micron_spinand_detect()
- fix BBT block cannot be erased bug

v3 changes:
- rebase patch on 4.11-rc1[2]
- change read ID method. read 4 bytes ID out then let ->detect() of each
  manufacutre driver to decode ID and detect the device.
- make SPI NAND id table private to each manufacutre driver
- fix coding style to make checkpatch.pl happy
- update the MAINTAINERS file for spi nand code
- add nand_size() helper in nand.h
- use nand_for_each_page() helper in spinand_do_read/write_ops()
- create helper to check boundaries in generic NAND code and use it
  in SPI NAND core
- rename spinand_base.c to core.c
- manufactures' drivers expose spinand_manufacturer struct instead of
  spinand_manufacturer_ops struct to keep Manufacture ID macro in
  manufactures' drivers and rename spinand_ids.c to manufacture.c
- rename spinand_micron.c to micron.c
- rename chips/ directory to controllers/
- rename generic_spi.c to generic-spi.c
- replace ->build_column_addr() and ->get_dummy() hooks with ->prepare_op() in
  spinand_manufacturer_ops struct
- rename __spinand_erase() to spinand_erase()
- rename spinand_erase() to spinand_erase_skip_bbt()
- rename spinand_scan_ident() to spinand_detect()
- rename spinand_scan_tail() to spinand_init()
- move non detect related code from spinand_detect() to spinand_init()
- remove spinand_fill_nandd, assign nand->ops in spinand_detect()
- merge v2 patch 3(bad block support) and patch 4(BBT support)
- drop getchip parameter, remove spinand_get/remove_device(), take the lock
  by caller directly
- fix function comment headers
- use nand_bbt_is_initialized() helper
- replace spinand_ecc_engine and spinand_controller object in spinand_device
  struct with pointer
- replace struct spinand_manufacturer_ops pointer in spinand_device struct
  with spinand_manufacturer struct

v2 changes:
- replace "spi_nand" with "spinand".
- rename spi nand related structs for better understanding.
- introduce spi nand controller, manufacturer and ecc_engine struct.
- add spi nand manufacturer initialization function refer to Boris's
  manuf-init branch.
- remove NAND_SKIP_BBTSCAN from series. Add it later when enabling HW ECC.
- reorganize series according to Boris's suggestion.

Boris Brezillon (2):
  mtd: nand: Pass mode information to nand_page_io_req
  dt-bindings: Add bindings for SPI NAND devices

Frieder Schrempf (1):
  mtd: nand: spi: Add initial support for Winbond W25M02GV

Peter Pan (2):
  mtd: nand: Add core infrastructure to support SPI NANDs
  mtd: nand: spi: Add initial support for Micron MT29F2G01ABAGD

 Documentation/devicetree/bindings/mtd/spi-nand.txt |   27 +
 drivers/mtd/nand/Kconfig                           |    1 +
 drivers/mtd/nand/Makefile                          |    1 +
 drivers/mtd/nand/spi/Kconfig                       |    7 +
 drivers/mtd/nand/spi/Makefile                      |    2 +
 drivers/mtd/nand/spi/core.c                        | 1140 ++++++++++++++++++++
 drivers/mtd/nand/spi/micron.c                      |  133 +++
 drivers/mtd/nand/spi/winbond.c                     |  141 +++
 include/linux/mtd/nand.h                           |    3 +
 include/linux/mtd/spinand.h                        |  419 +++++++
 include/linux/spi/spi-mem.h                        |    4 +-
 11 files changed, 1877 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/mtd/spi-nand.txt
 create mode 100644 drivers/mtd/nand/spi/Kconfig
 create mode 100644 drivers/mtd/nand/spi/Makefile
 create mode 100644 drivers/mtd/nand/spi/core.c
 create mode 100644 drivers/mtd/nand/spi/micron.c
 create mode 100644 drivers/mtd/nand/spi/winbond.c
 create mode 100644 include/linux/mtd/spinand.h

-- 
2.14.1

[PATCH v7 1/5] mtd: nand: Pass mode information to nand_page_io_req

[Boris Brezillon]

The NAND sub-layers are likely to need the MTD_OPS_XXX mode information
in order to decide if they should enable/disable ECC or how they should
place the OOB bytes in the provided OOB buffer.

Add a field to nand_page_io_req to pass this information.

Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
---
 include/linux/mtd/nand.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 792ea5c26329..abe975c87b90 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -86,6 +86,7 @@ struct nand_pos {
  * @ooboffs: the OOB offset within the page
  * @ooblen: the number of OOB bytes to read from/write to this page
  * @oobbuf: buffer to store OOB data in or get OOB data from
+ * @mode: one of the %MTD_OPS_XXX mode
  *
  * This object is used to pass per-page I/O requests to NAND sub-layers. This
  * way all useful information are already formatted in a useful way and
@@ -106,6 +107,7 @@ struct nand_page_io_req {
 		const void *out;
 		void *in;
 	} oobbuf;
+	int mode;
 };
 
 /**
@@ -599,6 +601,7 @@ static inline void nanddev_io_iter_init(struct nand_device *nand,
 {
 	struct mtd_info *mtd = nanddev_to_mtd(nand);
 
+	iter->req.mode = req->mode;
 	iter->req.dataoffs = nanddev_offs_to_pos(nand, offs, &iter->req.pos);
 	iter->req.ooboffs = req->ooboffs;
 	iter->oobbytes_per_page = mtd_oobavail(mtd, req);
-- 
2.14.1

[PATCH v7 2/5] mtd: nand: Add core infrastructure to support SPI NANDs

[Boris Brezillon]

From: Peter Pan <peterpandong@micron.com>

Add a SPI NAND framework based on the generic NAND framework and the
spi-mem infrastructure.

In its current state, this framework supports the following features:

- single/dual/quad IO modes
- on-die ECC

Signed-off-by: Peter Pan <peterpandong@micron.com>
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
---
 drivers/mtd/nand/Kconfig      |    1 +
 drivers/mtd/nand/Makefile     |    1 +
 drivers/mtd/nand/spi/Kconfig  |    7 +
 drivers/mtd/nand/spi/Makefile |    2 +
 drivers/mtd/nand/spi/core.c   | 1122 +++++++++++++++++++++++++++++++++++++++++
 include/linux/mtd/spinand.h   |  415 +++++++++++++++
 include/linux/spi/spi-mem.h   |    4 +-
 7 files changed, 1551 insertions(+), 1 deletion(-)
 create mode 100644 drivers/mtd/nand/spi/Kconfig
 create mode 100644 drivers/mtd/nand/spi/Makefile
 create mode 100644 drivers/mtd/nand/spi/core.c
 create mode 100644 include/linux/mtd/spinand.h

diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 88c7d3b4ff8b..9033215e62ea 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -4,3 +4,4 @@ config MTD_NAND_CORE
 source "drivers/mtd/nand/onenand/Kconfig"
 
 source "drivers/mtd/nand/raw/Kconfig"
+source "drivers/mtd/nand/spi/Kconfig"
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 3f0cb87f1a57..7ecd80c0a66e 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -5,3 +5,4 @@ obj-$(CONFIG_MTD_NAND_CORE) += nandcore.o
 
 obj-y	+= onenand/
 obj-y	+= raw/
+obj-y	+= spi/
diff --git a/drivers/mtd/nand/spi/Kconfig b/drivers/mtd/nand/spi/Kconfig
new file mode 100644
index 000000000000..7c37d2929b68
--- /dev/null
+++ b/drivers/mtd/nand/spi/Kconfig
@@ -0,0 +1,7 @@
+menuconfig MTD_SPI_NAND
+	tristate "SPI NAND device Support"
+	select MTD_NAND_CORE
+	depends on SPI_MASTER
+	select SPI_MEM
+	help
+	  This is the framework for the SPI NAND device drivers.
diff --git a/drivers/mtd/nand/spi/Makefile b/drivers/mtd/nand/spi/Makefile
new file mode 100644
index 000000000000..feb79a1d1b46
--- /dev/null
+++ b/drivers/mtd/nand/spi/Makefile
@@ -0,0 +1,2 @@
+spinand-objs := core.o
+obj-$(CONFIG_MTD_SPI_NAND) += spinand.o
diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c
new file mode 100644
index 000000000000..faad9bc93775
--- /dev/null
+++ b/drivers/mtd/nand/spi/core.c
@@ -0,0 +1,1122 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016-2017 Micron Technology, Inc.
+ *
+ * Authors:
+ *	Peter Pan <peterpandong@micron.com>
+ *	Boris Brezillon <boris.brezillon@bootlin.com>
+ */
+
+#define pr_fmt(fmt)	"spi-nand: " fmt
+
+#include <linux/device.h>
+#include <linux/jiffies.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/mtd/spinand.h>
+#include <linux/of.h>
+#include <linux/slab.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/spi-mem.h>
+
+static void spinand_cache_op_adjust_colum(struct spinand_device *spinand,
+					  const struct nand_page_io_req *req,
+					  u16 *column)
+{
+	struct nand_device *nand = spinand_to_nand(spinand);
+	unsigned int shift;
+
+	if (nand->memorg.planes_per_lun < 2)
+		return;
+
+	/* The plane number is passed in MSB just above the column address */
+	shift = fls(nand->memorg.pagesize);
+	*column |= req->pos.plane << shift;
+}
+
+static int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, u8 *val)
+{
+	struct spi_mem_op op = SPINAND_GET_FEATURE_OP(reg,
+						      spinand->scratchbuf);
+	int ret;
+
+	ret = spi_mem_exec_op(spinand->spimem, &op);
+	if (ret)
+		return ret;
+
+	*val = *spinand->scratchbuf;
+	return 0;
+}
+
+static int spinand_write_reg_op(struct spinand_device *spinand, u8 reg, u8 val)
+{
+	struct spi_mem_op op = SPINAND_SET_FEATURE_OP(reg,
+						      spinand->scratchbuf);
+
+	*spinand->scratchbuf = val;
+	return spi_mem_exec_op(spinand->spimem, &op);
+}
+
+static int spinand_read_status(struct spinand_device *spinand, u8 *status)
+{
+	return spinand_read_reg_op(spinand, REG_STATUS, status);
+}
+
+static int spinand_get_cfg(struct spinand_device *spinand, u8 *cfg)
+{
+	struct nand_device *nand = spinand_to_nand(spinand);
+
+	if (WARN_ON(spinand->cur_target < 0 ||
+		    spinand->cur_target >= nand->memorg.ntargets))
+		return -EINVAL;
+
+	*cfg = spinand->cfg_cache[spinand->cur_target];
+	return 0;
+}
+
+static int spinand_set_cfg(struct spinand_device *spinand, u8 cfg)
+{
+	struct nand_device *nand = spinand_to_nand(spinand);
+	int ret;
+
+	if (WARN_ON(spinand->cur_target < 0 ||
+		    spinand->cur_target >= nand->memorg.ntargets))
+		return -EINVAL;
+
+	if (spinand->cfg_cache[spinand->cur_target] == cfg)
+		return 0;
+
+	ret = spinand_write_reg_op(spinand, REG_CFG, cfg);
+	if (ret)
+		return ret;
+
+	spinand->cfg_cache[spinand->cur_target] = cfg;
+	return 0;
+}
+
+/**
+ * spinand_upd_cfg() - Update the configuration register
+ * @spinand: the spinand device
+ * @mask: the mask encoding the bits to update in the config reg
+ * @val: the new value to apply
+ *
+ * Update the configuration register.
+ *
+ * Return: 0 on success, a negative error code otherwise.
+ */
+int spinand_upd_cfg(struct spinand_device *spinand, u8 mask, u8 val)
+{
+	int ret;
+	u8 cfg;
+
+	ret = spinand_get_cfg(spinand, &cfg);
+	if (ret)
+		return ret;
+
+	cfg &= ~mask;
+	cfg |= val;
+
+	return spinand_set_cfg(spinand, cfg);
+}
+
+/**
+ * spinand_select_target() - Select a specific NAND target/die
+ * @spinand: the spinand device
+ * @target: the target/die to select
+ *
+ * Select a new target/die. If chip only has one die, this function is a NOOP.
+ *
+ * Return: 0 on success, a negative error code otherwise.
+ */
+int spinand_select_target(struct spinand_device *spinand, unsigned int target)
+{
+	struct nand_device *nand = spinand_to_nand(spinand);
+	int ret;
+
+	if (WARN_ON(target >= nand->memorg.ntargets))
+		return -EINVAL;
+
+	if (spinand->cur_target == target)
+		return 0;
+
+	if (nand->memorg.ntargets == 1) {
+		spinand->cur_target = target;
+		return 0;
+	}
+
+	ret = spinand->select_target(spinand, target);
+	if (ret)
+		return ret;
+
+	spinand->cur_target = target;
+	return 0;
+}
+
+static int spinand_init_cfg_cache(struct spinand_device *spinand)
+{
+	struct nand_device *nand = spinand_to_nand(spinand);
+	struct device *dev = &spinand->spimem->spi->dev;
+	unsigned int target;
+	int ret;
+
+	spinand->cfg_cache = devm_kzalloc(dev,
+					  sizeof(*spinand->cfg_cache) *
+					  nand->memorg.ntargets,
+					  GFP_KERNEL);
+	if (!spinand->cfg_cache)
+		return -ENOMEM;
+
+	for (target = 0; target < nand->memorg.ntargets; target++) {
+		ret = spinand_select_target(spinand, target);
+		if (ret)
+			return ret;
+
+		/*
+		 * We use spinand_read_reg_op() instead of spinand_get_cfg()
+		 * here to bypass the config cache.
+		 */
+		ret = spinand_read_reg_op(spinand, REG_CFG,
+					  &spinand->cfg_cache[target]);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static void spinand_init_quad_enable(struct spinand_device *spinand)
+{
+	bool enable = false;
+	u8 cfg = 0;
+
+	if (!(spinand->flags & SPINAND_HAS_QE_BIT))
+		return;
+
+	if (spinand->op_templates.read_cache->data.buswidth == 4 ||
+	    spinand->op_templates.write_cache->data.buswidth == 4 ||
+	    spinand->op_templates.update_cache->data.buswidth == 4)
+		enable = true;
+
+	WARN_ON(spinand_get_cfg(spinand, &cfg));
+
+	if (enable)
+		cfg |= CFG_QUAD_ENABLE;
+	else
+		cfg &= ~CFG_QUAD_ENABLE;
+
+	WARN_ON(spinand_set_cfg(spinand, cfg));
+}
+
+static void spinand_ecc_enable(struct spinand_device *spinand,
+			       bool enable)
+{
+	u8 cfg = 0;
+
+	WARN_ON(spinand_get_cfg(spinand, &cfg));
+
+	if (enable)
+		cfg |= CFG_ECC_ENABLE;
+	else
+		cfg &= ~CFG_ECC_ENABLE;
+
+	WARN_ON(spinand_set_cfg(spinand, cfg));
+}
+
+static int spinand_write_enable_op(struct spinand_device *spinand)
+{
+	struct spi_mem_op op = SPINAND_WR_EN_DIS_OP(true);
+
+	return spi_mem_exec_op(spinand->spimem, &op);
+}
+
+static int spinand_load_page_op(struct spinand_device *spinand,
+				const struct nand_page_io_req *req)
+{
+	struct nand_device *nand = spinand_to_nand(spinand);
+	unsigned int row = nanddev_pos_to_row(nand, &req->pos);
+	struct spi_mem_op op = SPINAND_PAGE_READ_OP(row);
+
+	return spi_mem_exec_op(spinand->spimem, &op);
+}
+
+static int spinand_read_from_cache_op(struct spinand_device *spinand,
+				      const struct nand_page_io_req *req)
+{
+	struct spi_mem_op op = *spinand->op_templates.read_cache;
+	struct nand_device *nand = spinand_to_nand(spinand);
+	struct mtd_info *mtd = nanddev_to_mtd(nand);
+	struct nand_page_io_req adjreq = *req;
+	unsigned int nbytes = 0;
+	void *buf = NULL;
+	u16 column = 0;
+	int ret;
+
+	if (req->datalen) {
+		adjreq.datalen = nanddev_page_size(nand);
+		adjreq.dataoffs = 0;
+		adjreq.databuf.in = spinand->databuf;
+		buf = spinand->databuf;
+		nbytes = adjreq.datalen;
+	}
+
+	if (req->ooblen) {
+		adjreq.ooblen = nanddev_per_page_oobsize(nand);
+		adjreq.ooboffs = 0;
+		adjreq.oobbuf.in = spinand->oobbuf;
+		nbytes += nanddev_per_page_oobsize(nand);
+		if (!buf) {
+			buf = spinand->oobbuf;
+			column = nanddev_page_size(nand);
+		}
+	}
+
+	spinand_cache_op_adjust_colum(spinand, &adjreq, &column);
+	op.addr.val = column;
+
+	/*
+	 * Some controllers are limited in term of max RX data size. In this
+	 * case, just repeat the READ_CACHE operation after updating the
+	 * column.
+	 */
+	while (nbytes) {
+		op.data.buf.in = buf;
+		op.data.nbytes = nbytes;
+		ret = spi_mem_adjust_op_size(spinand->spimem, &op);
+		if (ret)
+			return ret;
+
+		ret = spi_mem_exec_op(spinand->spimem, &op);
+		if (ret)
+			return ret;
+
+		buf += op.data.nbytes;
+		nbytes -= op.data.nbytes;
+		op.addr.val += op.data.nbytes;
+	}
+
+	if (req->datalen)
+		memcpy(req->databuf.in, spinand->databuf + req->dataoffs,
+		       req->datalen);
+
+	if (req->ooblen) {
+		if (req->mode == MTD_OPS_AUTO_OOB)
+			mtd_ooblayout_get_databytes(mtd, req->oobbuf.in,
+						    spinand->oobbuf,
+						    req->ooboffs,
+						    req->ooblen);
+		else
+			memcpy(req->oobbuf.in, spinand->oobbuf + req->ooboffs,
+			       req->ooblen);
+	}
+
+	return 0;
+}
+
+static int spinand_write_to_cache_op(struct spinand_device *spinand,
+				     const struct nand_page_io_req *req)
+{
+	struct spi_mem_op op = *spinand->op_templates.write_cache;
+	struct nand_device *nand = spinand_to_nand(spinand);
+	struct mtd_info *mtd = nanddev_to_mtd(nand);
+	struct nand_page_io_req adjreq = *req;
+	unsigned int nbytes = 0;
+	void *buf = NULL;
+	u16 column = 0;
+	int ret;
+
+	memset(spinand->databuf, 0xff,
+	       nanddev_page_size(nand) +
+	       nanddev_per_page_oobsize(nand));
+
+	if (req->datalen) {
+		memcpy(spinand->databuf + req->dataoffs, req->databuf.out,
+		       req->datalen);
+		adjreq.dataoffs = 0;
+		adjreq.datalen = nanddev_page_size(nand);
+		adjreq.databuf.out = spinand->databuf;
+		nbytes = adjreq.datalen;
+		buf = spinand->databuf;
+	}
+
+	if (req->ooblen) {
+		if (req->mode == MTD_OPS_AUTO_OOB)
+			mtd_ooblayout_set_databytes(mtd, req->oobbuf.out,
+						    spinand->oobbuf,
+						    req->ooboffs,
+						    req->ooblen);
+		else
+			memcpy(spinand->oobbuf + req->ooboffs, req->oobbuf.out,
+			       req->ooblen);
+
+		adjreq.ooblen = nanddev_per_page_oobsize(nand);
+		adjreq.ooboffs = 0;
+		nbytes += nanddev_per_page_oobsize(nand);
+		if (!buf) {
+			buf = spinand->oobbuf;
+			column = nanddev_page_size(nand);
+		}
+	}
+
+	spinand_cache_op_adjust_colum(spinand, &adjreq, &column);
+
+	op = *spinand->op_templates.write_cache;
+	op.addr.val = column;
+
+	/*
+	 * Some controllers are limited in term of max TX data size. In this
+	 * case, split the operation into one LOAD CACHE and one or more
+	 * LOAD RANDOM CACHE.
+	 */
+	while (nbytes) {
+		op.data.buf.out = buf;
+		op.data.nbytes = nbytes;
+
+		ret = spi_mem_adjust_op_size(spinand->spimem, &op);
+		if (ret)
+			return ret;
+
+		ret = spi_mem_exec_op(spinand->spimem, &op);
+		if (ret)
+			return ret;
+
+		buf += op.data.nbytes;
+		nbytes -= op.data.nbytes;
+		op.addr.val += op.data.nbytes;
+
+		/*
+		 * We need to use the RANDOM LOAD CACHE operation if there's
+		 * more than one iteration, because the LOAD operation resets
+		 * the cache to 0xff.
+		 */
+		if (nbytes) {
+			column = op.addr.val;
+			op = *spinand->op_templates.update_cache;
+			op.addr.val = column;
+		}
+	}
+
+	return 0;
+}
+
+static int spinand_program_op(struct spinand_device *spinand,
+			      const struct nand_page_io_req *req)
+{
+	struct nand_device *nand = spinand_to_nand(spinand);
+	unsigned int row = nanddev_pos_to_row(nand, &req->pos);
+	struct spi_mem_op op = SPINAND_PROG_EXEC_OP(row);
+
+	return spi_mem_exec_op(spinand->spimem, &op);
+}
+
+static int spinand_erase_op(struct spinand_device *spinand,
+			    const struct nand_pos *pos)
+{
+	struct nand_device *nand = &spinand->base;
+	unsigned int row = nanddev_pos_to_row(nand, pos);
+	struct spi_mem_op op = SPINAND_BLK_ERASE_OP(row);
+
+	return spi_mem_exec_op(spinand->spimem, &op);
+}
+
+static int spinand_wait(struct spinand_device *spinand, u8 *s)
+{
+	unsigned long timeo =  jiffies + msecs_to_jiffies(400);
+	u8 status;
+
+	do {
+		spinand_read_status(spinand, &status);
+		if (!(status & STATUS_BUSY))
+			goto out;
+	} while (time_before(jiffies, timeo));
+
+	/*
+	 * Extra read, just in case the STATUS_READY bit has changed
+	 * since our last check
+	 */
+	spinand_read_status(spinand, &status);
+
+out:
+	if (s)
+		*s = status;
+
+	return status & STATUS_BUSY ? -ETIMEDOUT : 0;
+}
+
+static int spinand_read_id_op(struct spinand_device *spinand, u8 *buf)
+{
+	struct spi_mem_op op = SPINAND_READID_OP(0, spinand->scratchbuf,
+						 SPINAND_MAX_ID_LEN);
+	int ret;
+
+	ret = spi_mem_exec_op(spinand->spimem, &op);
+	if (!ret)
+		memcpy(buf, spinand->scratchbuf, SPINAND_MAX_ID_LEN);
+
+	return 0;
+}
+
+static int spinand_reset_op(struct spinand_device *spinand)
+{
+	struct spi_mem_op op = SPINAND_RESET_OP;
+	int ret;
+
+	ret = spi_mem_exec_op(spinand->spimem, &op);
+	if (ret)
+		return ret;
+
+	return spinand_wait(spinand, NULL);
+}
+
+static int spinand_lock_block(struct spinand_device *spinand, u8 lock)
+{
+	return spinand_write_reg_op(spinand, REG_BLOCK_LOCK, lock);
+}
+
+static int spinand_check_ecc_status(struct spinand_device *spinand, u8 status)
+{
+	struct nand_device *nand = spinand_to_nand(spinand);
+
+	if (spinand->eccinfo.get_status)
+		return spinand->eccinfo.get_status(spinand, status);
+
+	switch (status & STATUS_ECC_MASK) {
+	case STATUS_ECC_NO_BITFLIPS:
+		return 0;
+
+	case STATUS_ECC_HAS_BITFLIPS:
+		/*
+		 * We have no way to know exactly how many bitflips have been
+		 * fixed, so let's return the maximum possible value so that
+		 * wear-leveling layers move the data immediately.
+		 */
+		return nand->eccreq.strength;
+
+	case STATUS_ECC_UNCOR_ERROR:
+		return -EBADMSG;
+
+	default:
+		break;
+	}
+
+	return -EINVAL;
+}
+
+static int spinand_read_page(struct spinand_device *spinand,
+			     const struct nand_page_io_req *req,
+			     bool ecc_enabled)
+{
+	struct nand_device *nand = spinand_to_nand(spinand);
+	struct device *dev = &spinand->spimem->spi->dev;
+	u8 status;
+	int ret;
+
+	spinand_load_page_op(spinand, req);
+
+	ret = spinand_wait(spinand, &status);
+	if (ret < 0) {
+		dev_err(dev, "failed to load page @%llx (err = %d)\n",
+			nanddev_pos_to_offs(nand, &req->pos), ret);
+		return ret;
+	}
+
+	spinand_read_from_cache_op(spinand, req);
+
+	if (!ecc_enabled)
+		return 0;
+
+	return spinand_check_ecc_status(spinand, status);
+}
+
+static int spinand_write_page(struct spinand_device *spinand,
+			      const struct nand_page_io_req *req)
+{
+	struct nand_device *nand = spinand_to_nand(spinand);
+	struct device *dev = &spinand->spimem->spi->dev;
+	u8 status;
+	int ret = 0;
+
+	spinand_write_enable_op(spinand);
+	spinand_write_to_cache_op(spinand, req);
+	spinand_program_op(spinand, req);
+
+	ret = spinand_wait(spinand, &status);
+	if (!ret && (status & STATUS_PROG_FAILED))
+		ret = -EIO;
+
+	if (ret < 0)
+		dev_err(dev, "failed to program page @%llx (err = %d)\n",
+			nanddev_pos_to_offs(nand, &req->pos), ret);
+
+	return ret;
+}
+
+static int spinand_mtd_read(struct mtd_info *mtd, loff_t from,
+			    struct mtd_oob_ops *ops)
+{
+	struct spinand_device *spinand = mtd_to_spinand(mtd);
+	struct nand_device *nand = mtd_to_nanddev(mtd);
+	unsigned int max_bitflips = 0;
+	struct nand_io_iter iter;
+	bool enable_ecc = false;
+	bool ecc_failed = false;
+	int ret = 0;
+
+	if (ops->mode != MTD_OPS_RAW && spinand->eccinfo.ooblayout)
+		enable_ecc = true;
+
+	mutex_lock(&spinand->lock);
+
+	nanddev_io_for_each_page(nand, from, ops, &iter) {
+		spinand_select_target(spinand, iter.req.pos.target);
+		spinand_ecc_enable(spinand, enable_ecc);
+		ret = spinand_read_page(spinand, &iter.req, enable_ecc);
+		if (ret < 0 && ret != -EBADMSG)
+			break;
+
+		if (ret == -EBADMSG) {
+			ecc_failed = true;
+			mtd->ecc_stats.failed++;
+			ret = 0;
+		} else {
+			mtd->ecc_stats.corrected += ret;
+			max_bitflips = max_t(unsigned int, max_bitflips, ret);
+		}
+
+		ops->retlen += iter.req.datalen;
+		ops->oobretlen += iter.req.ooblen;
+	}
+
+	mutex_unlock(&spinand->lock);
+
+	if (ecc_failed && !ret)
+		ret = -EBADMSG;
+
+	return ret ? ret : max_bitflips;
+}
+
+static int spinand_mtd_write(struct mtd_info *mtd, loff_t to,
+			     struct mtd_oob_ops *ops)
+{
+	struct spinand_device *spinand = mtd_to_spinand(mtd);
+	struct nand_device *nand = mtd_to_nanddev(mtd);
+	struct nand_io_iter iter;
+	bool enable_ecc = false;
+	int ret = 0;
+
+	if (ops->mode != MTD_OPS_RAW && mtd->ooblayout)
+		enable_ecc = true;
+
+	mutex_lock(&spinand->lock);
+
+	nanddev_io_for_each_page(nand, to, ops, &iter) {
+		spinand_select_target(spinand, iter.req.pos.target);
+		spinand_ecc_enable(spinand, enable_ecc);
+
+		ret = spinand_write_page(spinand, &iter.req);
+		if (ret)
+			break;
+
+		ops->retlen += iter.req.datalen;
+		ops->oobretlen += iter.req.ooblen;
+	}
+
+	mutex_unlock(&spinand->lock);
+
+	return ret;
+}
+
+static bool spinand_isbad(struct nand_device *nand, const struct nand_pos *pos)
+{
+	struct spinand_device *spinand = nand_to_spinand(nand);
+	struct nand_page_io_req req = {
+		.pos = *pos,
+		.ooblen = 2,
+		.ooboffs = 0,
+		.oobbuf.in = spinand->oobbuf,
+		.mode = MTD_OPS_RAW,
+	};
+	int ret;
+
+	memset(spinand->oobbuf, 0, 2);
+	spinand_select_target(spinand, pos->target);
+	ret = spinand_read_page(spinand, &req, false);
+	if (spinand->oobbuf[0] != 0xff || spinand->oobbuf[1] != 0xff)
+		return true;
+
+	return false;
+}
+
+static int spinand_mtd_block_isbad(struct mtd_info *mtd, loff_t offs)
+{
+	struct nand_device *nand = mtd_to_nanddev(mtd);
+	struct spinand_device *spinand = nand_to_spinand(nand);
+	struct nand_pos pos;
+	int ret;
+
+	nanddev_offs_to_pos(nand, offs, &pos);
+	mutex_lock(&spinand->lock);
+	ret = nanddev_isbad(nand, &pos);
+	mutex_unlock(&spinand->lock);
+
+	return ret;
+}
+
+static int spinand_markbad(struct nand_device *nand, const struct nand_pos *pos)
+{
+	struct spinand_device *spinand = nand_to_spinand(nand);
+	struct nand_page_io_req req = {
+		.pos = *pos,
+		.ooboffs = 0,
+		.ooblen = 2,
+		.oobbuf.out = spinand->oobbuf,
+	};
+
+	/* Erase block before marking it bad. */
+	spinand_select_target(spinand, pos->target);
+	spinand_write_enable_op(spinand);
+	spinand_erase_op(spinand, pos);
+
+	memset(spinand->oobbuf, 0, 2);
+	return spinand_write_page(spinand, &req);
+}
+
+static int spinand_mtd_block_markbad(struct mtd_info *mtd, loff_t offs)
+{
+	struct nand_device *nand = mtd_to_nanddev(mtd);
+	struct spinand_device *spinand = nand_to_spinand(nand);
+	struct nand_pos pos;
+	int ret;
+
+	nanddev_offs_to_pos(nand, offs, &pos);
+	mutex_lock(&spinand->lock);
+	ret = nanddev_markbad(nand, &pos);
+	mutex_unlock(&spinand->lock);
+
+	return ret;
+}
+
+static int spinand_erase(struct nand_device *nand, const struct nand_pos *pos)
+{
+	struct spinand_device *spinand = nand_to_spinand(nand);
+	struct device *dev = &spinand->spimem->spi->dev;
+	u8 status;
+	int ret;
+
+	spinand_select_target(spinand, pos->target);
+	spinand_write_enable_op(spinand);
+	spinand_erase_op(spinand, pos);
+
+	ret = spinand_wait(spinand, &status);
+
+	if (!ret && (status & STATUS_ERASE_FAILED))
+		ret = -EIO;
+
+	if (ret)
+		dev_err(dev, "failed to erase block %d (err = %d)\n",
+			pos->eraseblock, ret);
+
+	return ret;
+}
+
+static int spinand_mtd_erase(struct mtd_info *mtd,
+			     struct erase_info *einfo)
+{
+	struct spinand_device *spinand = mtd_to_spinand(mtd);
+	int ret;
+
+	mutex_lock(&spinand->lock);
+	ret = nanddev_mtd_erase(mtd, einfo);
+	mutex_unlock(&spinand->lock);
+
+	return ret;
+}
+
+static int spinand_mtd_block_isreserved(struct mtd_info *mtd, loff_t offs)
+{
+	struct spinand_device *spinand = mtd_to_spinand(mtd);
+	struct nand_device *nand = mtd_to_nanddev(mtd);
+	struct nand_pos pos;
+	int ret;
+
+	nanddev_offs_to_pos(nand, offs, &pos);
+	mutex_lock(&spinand->lock);
+	ret = nanddev_isreserved(nand, &pos);
+	mutex_unlock(&spinand->lock);
+
+	return ret;
+}
+
+const struct spi_mem_op *
+spinand_find_supported_op(struct spinand_device *spinand,
+			  const struct spi_mem_op *ops,
+			  unsigned int nops)
+{
+	unsigned int i;
+
+	for (i = 0; i < nops; i++) {
+		if (spi_mem_supports_op(spinand->spimem, &ops[i]))
+			return &ops[i];
+	}
+
+	return NULL;
+}
+
+static const struct nand_ops spinand_ops = {
+	.erase = spinand_erase,
+	.markbad = spinand_markbad,
+	.isbad = spinand_isbad,
+};
+
+static int spinand_manufacturer_detect(struct spinand_device *spinand)
+{
+	return -ENOTSUPP;
+}
+
+static int spinand_manufacturer_init(struct spinand_device *spinand)
+{
+	if (spinand->manufacturer->ops->init)
+		return spinand->manufacturer->ops->init(spinand);
+
+	return 0;
+}
+
+static void spinand_manufacturer_cleanup(struct spinand_device *spinand)
+{
+	/* Release manufacturer private data */
+	if (spinand->manufacturer->ops->cleanup)
+		return spinand->manufacturer->ops->cleanup(spinand);
+}
+
+static const struct spi_mem_op *
+spinand_select_op_variant(struct spinand_device *spinand,
+			  const struct spinand_op_variants *variants)
+{
+	struct nand_device *nand = spinand_to_nand(spinand);
+	unsigned int i;
+
+	for (i = 0; i < variants->nops; i++) {
+		struct spi_mem_op op = variants->ops[i];
+		unsigned int nbytes;
+		int ret;
+
+		nbytes = nanddev_per_page_oobsize(nand) +
+			 nanddev_page_size(nand);
+
+		while (nbytes) {
+			op.data.nbytes = nbytes;
+			ret = spi_mem_adjust_op_size(spinand->spimem, &op);
+			if (ret)
+				break;
+
+			if (!spi_mem_supports_op(spinand->spimem, &op))
+				break;
+
+			nbytes -= op.data.nbytes;
+		}
+
+		if (!nbytes)
+			return &variants->ops[i];
+	}
+
+	return NULL;
+}
+
+/**
+ * spinand_match_and_init() - Try to find a match between a device ID and an
+ *			      entry in a spinand_info table
+ * @spinand: SPI NAND object
+ * @table: SPI NAND device description table
+ * @table_size: size of the device description table
+ *
+ * Should be used by SPI NAND manufacturer drivers when they want to find a
+ * match between a device ID retrieved through the READ_ID command and an
+ * entry in the SPI NAND description table. If a match is found, the spinand
+ * object will be initialized with information provided by the matching
+ * spinand_info entry.
+ *
+ * Return: 0 on success, a negative error code otherwise.
+ */
+int spinand_match_and_init(struct spinand_device *spinand,
+			   const struct spinand_info *table,
+			   unsigned int table_size, u8 devid)
+{
+	struct nand_device *nand = spinand_to_nand(spinand);
+	unsigned int i;
+
+	for (i = 0; i < table_size; i++) {
+		const struct spinand_info *info = &table[i];
+		const struct spi_mem_op *op;
+
+		if (devid != info->devid)
+			continue;
+
+		nand->memorg = table[i].memorg;
+		nand->eccreq = table[i].eccreq;
+		spinand->eccinfo = table[i].eccinfo;
+		spinand->flags = table[i].flags;
+		spinand->select_target = table[i].select_target;
+
+		op = spinand_select_op_variant(spinand,
+					       info->op_variants.read_cache);
+		if (!op)
+			return -ENOTSUPP;
+
+		spinand->op_templates.read_cache = op;
+
+		op = spinand_select_op_variant(spinand,
+					       info->op_variants.write_cache);
+		if (!op)
+			return -ENOTSUPP;
+
+		spinand->op_templates.write_cache = op;
+
+		op = spinand_select_op_variant(spinand,
+					       info->op_variants.update_cache);
+		spinand->op_templates.update_cache = op;
+
+		spinand_init_quad_enable(spinand);
+
+		return 0;
+	}
+
+	return -ENOTSUPP;
+}
+
+static int spinand_detect(struct spinand_device *spinand)
+{
+	struct device *dev = &spinand->spimem->spi->dev;
+	struct nand_device *nand = &spinand->base;
+	int ret;
+
+	ret = spinand_reset_op(spinand);
+	if (ret)
+		return ret;
+
+	ret = spinand_read_id_op(spinand, spinand->id.data);
+	if (ret)
+		return ret;
+
+	spinand->id.len = SPINAND_MAX_ID_LEN;
+
+	ret = spinand_manufacturer_detect(spinand);
+	if (ret) {
+		dev_err(dev, "unknown raw ID %*phN\n", SPINAND_MAX_ID_LEN,
+			spinand->id.data);
+		return ret;
+	}
+
+	if (nand->memorg.ntargets > 1 && !spinand->select_target) {
+		dev_err(dev,
+			"SPI NANDs with more than one die must implement ->select_target()\n");
+		return -EINVAL;
+	}
+
+	dev_info(&spinand->spimem->spi->dev,
+		 "%s SPI NAND was found.\n", spinand->manufacturer->name);
+	dev_info(&spinand->spimem->spi->dev,
+		 "%llu MiB, block size: %zu KiB, page size: %zu, OOB size: %u\n",
+		 nanddev_size(nand) >> 20, nanddev_eraseblock_size(nand) >> 10,
+		 nanddev_page_size(nand), nanddev_per_page_oobsize(nand));
+
+	return 0;
+}
+
+static int spinand_noecc_ooblayout_ecc(struct mtd_info *mtd, int section,
+				       struct mtd_oob_region *region)
+{
+	return -ERANGE;
+}
+
+static int spinand_noecc_ooblayout_free(struct mtd_info *mtd, int section,
+					struct mtd_oob_region *region)
+{
+	if (section)
+		return -ERANGE;
+
+	/* Reserve 2 bytes for the BBM. */
+	region->offset = 2;
+	region->length = 62;
+
+	return 0;
+}
+
+static const struct mtd_ooblayout_ops spinand_noecc_ooblayout = {
+	.ecc = spinand_noecc_ooblayout_ecc,
+	.free = spinand_noecc_ooblayout_free,
+};
+
+static int spinand_init(struct spinand_device *spinand)
+{
+	struct device *dev = &spinand->spimem->spi->dev;
+	struct mtd_info *mtd = spinand_to_mtd(spinand);
+	struct nand_device *nand = mtd_to_nanddev(mtd);
+	int ret, i;
+
+	/*
+	 * We need a scratch buffer because the spi_mem interface requires that
+	 * buf passed in spi_mem_op->data.buf be DMA-able.
+	 */
+	spinand->scratchbuf = kzalloc(SPINAND_MAX_ID_LEN, GFP_KERNEL);
+	if (!spinand->scratchbuf)
+		return -ENOMEM;
+
+	ret = spinand_detect(spinand);
+	if (ret)
+		goto err_free_bufs;
+
+	/*
+	 * Use kzalloc() instead of devm_kzalloc() here, because some drivers
+	 * may use this buffer for DMA access.
+	 * Memory allocated by devm_ does not guarantee DMA-safe alignment.
+	 */
+	spinand->databuf = kzalloc(nanddev_page_size(nand) +
+			       nanddev_per_page_oobsize(nand),
+			       GFP_KERNEL);
+	if (!spinand->databuf)
+		goto err_free_bufs;
+
+	spinand->oobbuf = spinand->databuf + nanddev_page_size(nand);
+
+	ret = spinand_init_cfg_cache(spinand);
+	if (ret)
+		goto err_free_bufs;
+
+	ret = spinand_manufacturer_init(spinand);
+	if (ret) {
+		dev_err(dev,
+			"Failed to initialize the SPI NAND chip (err = %d)\n",
+			ret);
+		goto err_free_bufs;
+	}
+
+	/* After power up, all blocks are locked, so unlock it here. */
+	for (i = 0; i < nand->memorg.ntargets; i++) {
+		spinand_select_target(spinand, i);
+		spinand_lock_block(spinand, BL_ALL_UNLOCKED);
+	}
+
+	ret = nanddev_init(nand, &spinand_ops, THIS_MODULE);
+	if (ret)
+		goto err_free_bufs;
+
+	/*
+	 * Right now, we don't support ECC, so let the whole oob
+	 * area is available for user.
+	 */
+	mtd->_read_oob = spinand_mtd_read;
+	mtd->_write_oob = spinand_mtd_write;
+	mtd->_block_isbad = spinand_mtd_block_isbad;
+	mtd->_block_markbad = spinand_mtd_block_markbad;
+	mtd->_block_isreserved = spinand_mtd_block_isreserved;
+	mtd->_erase = spinand_mtd_erase;
+
+	if (spinand->eccinfo.ooblayout)
+		mtd_set_ooblayout(mtd, spinand->eccinfo.ooblayout);
+	else
+		mtd_set_ooblayout(mtd, &spinand_noecc_ooblayout);
+
+	ret = mtd_ooblayout_count_freebytes(mtd);
+	if (ret < 0)
+		goto err_cleanup_nanddev;
+
+	return 0;
+
+err_cleanup_nanddev:
+	nanddev_cleanup(nand);
+
+err_free_bufs:
+	kfree(spinand->databuf);
+	kfree(spinand->scratchbuf);
+	return ret;
+}
+
+static void spinand_cleanup(struct spinand_device *spinand)
+{
+	struct nand_device *nand = &spinand->base;
+
+	spinand_manufacturer_cleanup(spinand);
+	nanddev_cleanup(nand);
+	kfree(spinand->databuf);
+	kfree(spinand->scratchbuf);
+}
+
+static int spinand_probe(struct spi_mem *mem)
+{
+	struct spinand_device *spinand;
+	struct mtd_info *mtd;
+	int ret;
+
+	spinand = devm_kzalloc(&mem->spi->dev, sizeof(*spinand),
+			       GFP_KERNEL);
+	if (!spinand)
+		return -ENOMEM;
+
+	spinand->spimem = mem;
+	spi_mem_set_drvdata(mem, spinand);
+	spinand_set_of_node(spinand, mem->spi->dev.of_node);
+	mutex_init(&spinand->lock);
+	mtd = spinand_to_mtd(spinand);
+	mtd->dev.parent = &mem->spi->dev;
+
+	ret = spinand_init(spinand);
+	if (ret)
+		return ret;
+
+	ret = mtd_device_register(mtd, NULL, 0);
+	if (ret)
+		goto err_spinand_cleanup;
+
+	return 0;
+
+err_spinand_cleanup:
+	spinand_cleanup(spinand);
+
+	return ret;
+}
+
+static int spinand_remove(struct spi_mem *mem)
+{
+	struct spinand_device *spinand;
+	struct mtd_info *mtd;
+	int ret;
+
+	spinand = spi_mem_get_drvdata(mem);
+	mtd = spinand_to_mtd(spinand);
+
+	ret = mtd_device_unregister(mtd);
+	if (ret)
+		return ret;
+
+	spinand_cleanup(spinand);
+
+	return 0;
+}
+
+static const struct spi_device_id spinand_ids[] = {
+	{ .name = "spi-nand" },
+	{ /* sentinel */ },
+};
+
+#ifdef CONFIG_OF
+static const struct of_device_id spinand_of_ids[] = {
+	{ .compatible = "spi-nand" },
+	{ /* sentinel */ },
+};
+#endif
+
+static struct spi_mem_driver spinand_drv = {
+	.spidrv = {
+		.id_table = spinand_ids,
+		.driver = {
+			.name = "spi-nand",
+			.of_match_table = of_match_ptr(spinand_of_ids),
+		},
+	},
+	.probe = spinand_probe,
+	.remove = spinand_remove,
+};
+module_spi_mem_driver(spinand_drv);
+
+MODULE_DESCRIPTION("SPI NAND framework");
+MODULE_AUTHOR("Peter Pan<peterpandong@micron.com>");
+MODULE_LICENSE("GPL v2");
diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h
new file mode 100644
index 000000000000..17a4584c0017
--- /dev/null
+++ b/include/linux/mtd/spinand.h
@@ -0,0 +1,415 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2016-2017 Micron Technology, Inc.
+ *
+ *  Authors:
+ *	Peter Pan <peterpandong@micron.com>
+ */
+#ifndef __LINUX_MTD_SPINAND_H
+#define __LINUX_MTD_SPINAND_H
+
+#include <linux/mutex.h>
+#include <linux/bitops.h>
+#include <linux/device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/spi-mem.h>
+
+/**
+ * Standard SPI NAND flash operations
+ */
+
+#define SPINAND_RESET_OP						\
+	SPI_MEM_OP(SPI_MEM_OP_CMD(0xff, 1),				\
+		   SPI_MEM_OP_NO_ADDR,					\
+		   SPI_MEM_OP_NO_DUMMY,					\
+		   SPI_MEM_OP_NO_DATA)
+
+#define SPINAND_WR_EN_DIS_OP(enable)					\
+	SPI_MEM_OP(SPI_MEM_OP_CMD((enable) ? 0x06 : 0x04, 1),		\
+		   SPI_MEM_OP_NO_ADDR,					\
+		   SPI_MEM_OP_NO_DUMMY,					\
+		   SPI_MEM_OP_NO_DATA)
+
+#define SPINAND_READID_OP(ndummy, buf, len)				\
+	SPI_MEM_OP(SPI_MEM_OP_CMD(0x9f, 1),				\
+		   SPI_MEM_OP_NO_ADDR,					\
+		   SPI_MEM_OP_DUMMY(ndummy, 1),				\
+		   SPI_MEM_OP_DATA_IN(len, buf, 1))
+
+#define SPINAND_SET_FEATURE_OP(reg, valptr)				\
+	SPI_MEM_OP(SPI_MEM_OP_CMD(0x1f, 1),				\
+		   SPI_MEM_OP_ADDR(1, reg, 1),				\
+		   SPI_MEM_OP_NO_DUMMY,					\
+		   SPI_MEM_OP_DATA_OUT(1, valptr, 1))
+
+#define SPINAND_GET_FEATURE_OP(reg, valptr)				\
+	SPI_MEM_OP(SPI_MEM_OP_CMD(0x0f, 1),				\
+		   SPI_MEM_OP_ADDR(1, reg, 1),				\
+		   SPI_MEM_OP_NO_DUMMY,					\
+		   SPI_MEM_OP_DATA_IN(1, valptr, 1))
+
+#define SPINAND_BLK_ERASE_OP(addr)					\
+	SPI_MEM_OP(SPI_MEM_OP_CMD(0xd8, 1),				\
+		   SPI_MEM_OP_ADDR(3, addr, 1),				\
+		   SPI_MEM_OP_NO_DUMMY,					\
+		   SPI_MEM_OP_NO_DATA)
+
+#define SPINAND_PAGE_READ_OP(addr)					\
+	SPI_MEM_OP(SPI_MEM_OP_CMD(0x13, 1),				\
+		   SPI_MEM_OP_ADDR(3, addr, 1),				\
+		   SPI_MEM_OP_NO_DUMMY,					\
+		   SPI_MEM_OP_NO_DATA)
+
+#define SPINAND_PAGE_READ_FROM_CACHE_OP(fast, addr, ndummy, buf, len)	\
+	SPI_MEM_OP(SPI_MEM_OP_CMD(fast ? 0x0b : 0x03, 1),		\
+		   SPI_MEM_OP_ADDR(2, addr, 1),				\
+		   SPI_MEM_OP_DUMMY(ndummy, 1),				\
+		   SPI_MEM_OP_DATA_IN(len, buf, 1))
+
+#define SPINAND_PAGE_READ_FROM_CACHE_X2_OP(addr, ndummy, buf, len)	\
+	SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1),				\
+		   SPI_MEM_OP_ADDR(2, addr, 1),				\
+		   SPI_MEM_OP_DUMMY(ndummy, 1),				\
+		   SPI_MEM_OP_DATA_IN(len, buf, 2))
+
+#define SPINAND_PAGE_READ_FROM_CACHE_X4_OP(addr, ndummy, buf, len)	\
+	SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1),				\
+		   SPI_MEM_OP_ADDR(2, addr, 1),				\
+		   SPI_MEM_OP_DUMMY(ndummy, 1),				\
+		   SPI_MEM_OP_DATA_IN(len, buf, 4))
+
+#define SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(addr, ndummy, buf, len)	\
+	SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1),				\
+		   SPI_MEM_OP_ADDR(2, addr, 2),				\
+		   SPI_MEM_OP_DUMMY(ndummy, 2),				\
+		   SPI_MEM_OP_DATA_IN(len, buf, 2))
+
+#define SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(addr, ndummy, buf, len)	\
+	SPI_MEM_OP(SPI_MEM_OP_CMD(0xeb, 1),				\
+		   SPI_MEM_OP_ADDR(2, addr, 4),				\
+		   SPI_MEM_OP_DUMMY(ndummy, 4),				\
+		   SPI_MEM_OP_DATA_IN(len, buf, 4))
+
+#define SPINAND_PROG_EXEC_OP(addr)					\
+	SPI_MEM_OP(SPI_MEM_OP_CMD(0x10, 1),				\
+		   SPI_MEM_OP_ADDR(3, addr, 1),				\
+		   SPI_MEM_OP_NO_DUMMY,					\
+		   SPI_MEM_OP_NO_DATA)
+
+#define SPINAND_PROG_LOAD(reset, addr, buf, len)			\
+	SPI_MEM_OP(SPI_MEM_OP_CMD(reset ? 0x02 : 0x84, 1),		\
+		   SPI_MEM_OP_ADDR(2, addr, 1),				\
+		   SPI_MEM_OP_NO_DUMMY,					\
+		   SPI_MEM_OP_DATA_OUT(len, buf, 1))
+
+#define SPINAND_PROG_LOAD_X4(reset, addr, buf, len)			\
+	SPI_MEM_OP(SPI_MEM_OP_CMD(reset ? 0x32 : 0x34, 1),		\
+		   SPI_MEM_OP_ADDR(2, addr, 1),				\
+		   SPI_MEM_OP_NO_DUMMY,					\
+		   SPI_MEM_OP_DATA_OUT(len, buf, 4))
+
+/**
+ * Standard SPI NAND flash commands
+ */
+#define SPINAND_CMD_PROG_LOAD_X4		0x32
+#define SPINAND_CMD_PROG_LOAD_RDM_DATA_X4	0x34
+
+/* feature register */
+#define REG_BLOCK_LOCK		0xa0
+#define BL_ALL_UNLOCKED		0x00
+
+/* configuration register */
+#define REG_CFG			0xb0
+#define CFG_ECC_ENABLE		BIT(4)
+#define CFG_QUAD_ENABLE		BIT(0)
+
+/* status register */
+#define REG_STATUS		0xc0
+#define STATUS_BUSY		BIT(0)
+#define STATUS_ERASE_FAILED	BIT(2)
+#define STATUS_PROG_FAILED	BIT(3)
+#define STATUS_ECC_MASK		GENMASK(5, 4)
+#define STATUS_ECC_NO_BITFLIPS	(0 << 4)
+#define STATUS_ECC_HAS_BITFLIPS	(1 << 4)
+#define STATUS_ECC_UNCOR_ERROR	(2 << 4)
+
+struct spinand_op;
+struct spinand_device;
+
+#define SPINAND_MAX_ID_LEN	4
+
+/**
+ * struct spinand_id - SPI NAND id structure
+ * @data: buffer containing the id bytes. Currently 4 bytes large, but can
+ *	  be extended if required
+ * @len: ID length
+ *
+ * struct_spinand_id->data contains all bytes returned after a READ_ID command,
+ * including dummy bytes if the chip does not emit ID bytes right after the
+ * READ_ID command. The responsibility to extract real ID bytes is left to
+ * struct_manufacurer_ops->detect().
+ */
+struct spinand_id {
+	u8 data[SPINAND_MAX_ID_LEN];
+	int len;
+};
+
+/**
+ * struct manufacurer_ops - SPI NAND manufacturer specific operations
+ * @detect: detect a SPI NAND device. Every time a SPI NAND device is probed
+ *	    the core calls the struct_manufacurer_ops->detect() hook of each
+ *	    registered manufacturer until one of them return 1. Note that
+ *	    the first thing to check in this hook is that the manufacturer ID
+ *	    in struct_spinand_device->id matches the manufacturer whose
+ *	    ->detect() hook has been called. Should return 1 if there's a
+ *	    match, 0 if the manufacturer ID does not match and a negative
+ *	    error code otherwise. When true is returned, the core assumes
+ *	    that properties of the NAND chip (spinand->base.memorg and
+ *	    spinand->base.eccreq) have been filled
+ * @init: initialize a SPI NAND device
+ * @cleanup: cleanup a SPI NAND device
+ *
+ * Each SPI NAND manufacturer driver should implement this interface so that
+ * NAND chips coming from this vendor can be detected and initialized properly.
+ */
+struct spinand_manufacturer_ops {
+	int (*detect)(struct spinand_device *spinand);
+	int (*init)(struct spinand_device *spinand);
+	void (*cleanup)(struct spinand_device *spinand);
+};
+
+/**
+ * struct spinand_manufacturer - SPI NAND manufacturer instance
+ * @id: manufacturer ID
+ * @name: manufacturer name
+ * @ops: manufacturer operations
+ */
+struct spinand_manufacturer {
+	u8 id;
+	char *name;
+	const struct spinand_manufacturer_ops *ops;
+};
+
+/**
+ * struct spinand_op_variants - SPI NAND operation variants
+ * @ops: the list of variants for a given operation
+ * @nops: the number of variants
+ *
+ * Some operations like read-from-cache/write-to-cache have several variants
+ * depending on the number of IO lines you use to transfer data or address
+ * cycles. This structure is a way to describe the different variants supported
+ * by a chip and let the core pick the best one based on the SPI mem controller
+ * capabilities.
+ */
+struct spinand_op_variants {
+	const struct spi_mem_op *ops;
+	unsigned int nops;
+};
+
+#define SPINAND_OP_VARIANTS(name, ...)					\
+	const struct spinand_op_variants name = {			\
+		.ops = (struct spi_mem_op[]) { __VA_ARGS__ },		\
+		.nops = sizeof((struct spi_mem_op[]){ __VA_ARGS__ }) /	\
+			sizeof(struct spi_mem_op),			\
+	}
+
+/**
+ * spinand_ecc_info - description of the on-die ECC implemented by a SPI NAND
+ *		      chip
+ * @get_status: get the ECC status. Should return a positive number encoding
+ *		the number of corrected bitflips if correction was possible or
+ *		-EBADMSG if there are uncorrectable errors. I can also return
+ *		other negative error codes if the error is not caused by
+ *		uncorrectable bitflips
+ * @ooblayout: the OOB layout used by the on-die ECC implementation
+ */
+struct spinand_ecc_info {
+	int (*get_status)(struct spinand_device *spinand, u8 status);
+	const struct mtd_ooblayout_ops *ooblayout;
+};
+
+#define SPINAND_HAS_QE_BIT		BIT(0)
+
+/**
+ * struct spinand_info - Structure used to describe SPI NAND chips
+ * @model: model name
+ * @devid: device ID
+ * @flags: OR-ing of the SPINAND_XXX flags
+ * @memorg: memory organization
+ * @eccreq: ECC requirements
+ * @eccinfo: on-die ECC info
+ * @op_variants: operations variants
+ * @op_variants.read_cache: variants of the read-cache operation
+ * @op_variants.write_cache: variants of the write-cache operation
+ * @op_variants.update_cache: variants of the update-cache operation
+ * @select_target: function used to select a target/die. Required only for
+ *		   multi-die chips
+ *
+ * Each SPI NAND manufacturer driver should have a spinand_info table
+ * describing all the chips supported by the driver.
+ */
+struct spinand_info {
+	const char *model;
+	u8 devid;
+	u32 flags;
+	struct nand_memory_organization memorg;
+	struct nand_ecc_req eccreq;
+	struct spinand_ecc_info eccinfo;
+	struct {
+		const struct spinand_op_variants *read_cache;
+		const struct spinand_op_variants *write_cache;
+		const struct spinand_op_variants *update_cache;
+	} op_variants;
+	int (*select_target)(struct spinand_device *spinand,
+			     unsigned int target);
+};
+
+#define SPINAND_INFO_OP_VARIANTS(__read, __write, __update)		\
+	{								\
+		.read_cache = __read,					\
+		.write_cache = __write,					\
+		.update_cache = __update,				\
+	}
+
+#define SPINAND_ECCINFO(__ooblayout, __get_status)			\
+	.eccinfo = {							\
+		.ooblayout = __ooblayout,				\
+		.get_status = __get_status,				\
+	}
+
+#define SPINAND_SELECT_TARGET(__func)					\
+	.select_target = __func,
+
+#define SPINAND_INFO(__model, __id, __memorg, __eccreq, __op_variants,	\
+		     __flags, ...)					\
+	{								\
+		.model = __model,					\
+		.devid = __id,						\
+		.memorg = __memorg,					\
+		.eccreq = __eccreq,					\
+		.op_variants = __op_variants,				\
+		.flags = __flags,					\
+		__VA_ARGS__						\
+	}
+
+/**
+ * struct spinand_device - SPI NAND device instance
+ * @base: NAND device instance
+ * @spimem: pointer to the SPI mem object
+ * @lock: lock used to serialize accesses to the NAND
+ * @id: NAND ID as returned by READ_ID
+ * @flags: NAND flags
+ * @op_templates: various SPI mem op templates
+ * @op_templates.read_cache: read cache op template
+ * @op_templates.write_cache: write cache op template
+ * @op_templates.update_cache: update cache op template
+ * @select_target: select a specific target/die. Usually called before sending
+ *		   a command addressing a page or an eraseblock embedded in
+ *		   this die. Only required if your chip exposes several dies
+ * @cur_target: currently selected target/die
+ * @eccinfo: on-die ECC information
+ * @cfg_cache: config register cache. One entry per die
+ * @databuf: bounce buffer for data
+ * @oobbuf: bounce buffer for OOB data
+ * @scratchbuf: buffer used for everything but page accesses. This is needed
+ *		because the spi-mem interface explicitly requests that buffers
+ *		passed in spi_mem_op be DMA-able, so we can't based the bufs on
+ *		the stack
+ * @manufacturer: SPI NAND manufacturer information
+ * @priv: manufacturer private data
+ */
+struct spinand_device {
+	struct nand_device base;
+	struct spi_mem *spimem;
+	struct mutex lock;
+	struct spinand_id id;
+	u32 flags;
+
+	struct {
+		const struct spi_mem_op *read_cache;
+		const struct spi_mem_op *write_cache;
+		const struct spi_mem_op *update_cache;
+	} op_templates;
+
+	int (*select_target)(struct spinand_device *spinand,
+			     unsigned int target);
+	unsigned int cur_target;
+
+	struct spinand_ecc_info eccinfo;
+
+	u8 *cfg_cache;
+	u8 *databuf;
+	u8 *oobbuf;
+	u8 *scratchbuf;
+	const struct spinand_manufacturer *manufacturer;
+	void *priv;
+};
+
+/**
+ * mtd_to_spinand() - Get the SPI NAND device attached to an MTD instance
+ * @mtd: MTD instance
+ *
+ * Return: the SPI NAND device attached to @mtd.
+ */
+static inline struct spinand_device *mtd_to_spinand(struct mtd_info *mtd)
+{
+	return container_of(mtd_to_nanddev(mtd), struct spinand_device, base);
+}
+
+/**
+ * spinand_to_mtd() - Get the MTD device embedded in a SPI NAND device
+ * @spinand: SPI NAND device
+ *
+ * Return: the MTD device embedded in @spinand.
+ */
+static inline struct mtd_info *spinand_to_mtd(struct spinand_device *spinand)
+{
+	return nanddev_to_mtd(&spinand->base);
+}
+
+/**
+ * nand_to_spinand() - Get the SPI NAND device embedding an NAND object
+ * @nand: NAND object
+ *
+ * Return: the SPI NAND device embedding @nand.
+ */
+static inline struct spinand_device *nand_to_spinand(struct nand_device *nand)
+{
+	return container_of(nand, struct spinand_device, base);
+}
+
+/**
+ * spinand_to_nand() - Get the NAND device embedded in a SPI NAND object
+ * @spinand: SPI NAND device
+ *
+ * Return: the NAND device embedded in @spinand.
+ */
+static inline struct nand_device *
+spinand_to_nand(struct spinand_device *spinand)
+{
+	return &spinand->base;
+}
+
+/**
+ * spinand_set_of_node - Attach a DT node to a SPI NAND device
+ * @spinand: SPI NAND device
+ * @np: DT node
+ *
+ * Attach a DT node to a SPI NAND device.
+ */
+static inline void spinand_set_of_node(struct spinand_device *spinand,
+				       struct device_node *np)
+{
+	nanddev_set_of_node(&spinand->base, np);
+}
+
+int spinand_match_and_init(struct spinand_device *dev,
+			   const struct spinand_info *table,
+			   unsigned int table_size, u8 devid);
+
+int spinand_upd_cfg(struct spinand_device *spinand, u8 mask, u8 val);
+int spinand_select_target(struct spinand_device *spinand, unsigned int target);
+
+#endif /* __LINUX_MTD_SPINAND_H */
diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h
index bb4bd15ae1f6..4fa34a227a0f 100644
--- a/include/linux/spi/spi-mem.h
+++ b/include/linux/spi/spi-mem.h
@@ -3,7 +3,9 @@
  * Copyright (C) 2018 Exceet Electronics GmbH
  * Copyright (C) 2018 Bootlin
  *
- * Author: Boris Brezillon <boris.brezillon@bootlin.com>
+ * Author:
+ *	Peter Pan <peterpandong@micron.com>
+ *	Boris Brezillon <boris.brezillon@bootlin.com>
  */
 
 #ifndef __LINUX_SPI_MEM_H
-- 
2.14.1

[PATCH v7 3/5] dt-bindings: Add bindings for SPI NAND devices

[Boris Brezillon]

Add bindigns for SPI NAND chips.

Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
---
 Documentation/devicetree/bindings/mtd/spi-nand.txt | 27 ++++++++++++++++++++++
 1 file changed, 27 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mtd/spi-nand.txt

diff --git a/Documentation/devicetree/bindings/mtd/spi-nand.txt b/Documentation/devicetree/bindings/mtd/spi-nand.txt
new file mode 100644
index 000000000000..d55f80196c63
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/spi-nand.txt
@@ -0,0 +1,27 @@
+SPI NAND flash
+
+Required properties:
+- compatible: should be "spi-nand"
+- reg: should encode the chip-select line used to access the NAND chip
+
+Optional properties
+- spi-max-frequency: maximum frequency of the SPI bus the chip can operate at.
+		     This should encode board limitations (i.e. max freq can't
+		     be achieved due to crosstalk on IO lines).
+		     When unspecified, the driver assumes the chip can run at
+		     the max frequency defined in the spec (information
+		     extracted chip detection time).
+- spi-tx-bus-width: The bus width (number of data wires) that is used for MOSI.
+		    Only encodes the board constraints (i.e. when not all IO
+		    signals are routed on the board). Device constraints are
+		    extracted when detecting the chip, and controller
+		    constraints are exposed by the SPI mem controller. If this
+		    property is missing that means no constraint at the board
+		    level.
+- spi-rx-bus-width: The bus width (number of data wires) that is used for MISO.
+		    Only encodes the board constraints (i.e. when not all IO
+		    signals are routed on the board). Device constraints are
+		    extracted when detecting the chip, and controller
+		    constraints are exposed by the SPI mem controller. If this
+		    property is missing that means no constraint at the board
+		    level.
-- 
2.14.1

[PATCH v7 4/5] mtd: nand: spi: Add initial support for Micron MT29F2G01ABAGD

[Boris Brezillon]

From: Peter Pan <peterpandong@micron.com>

Add a basic driver for Micron SPI NANDs. Only one device is supported
right now, but the driver will be extended to support more devices
afterwards.

Signed-off-by: Peter Pan <peterpandong@micron.com>
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
---
 drivers/mtd/nand/spi/Makefile |   2 +-
 drivers/mtd/nand/spi/core.c   |  17 ++++++
 drivers/mtd/nand/spi/micron.c | 133 ++++++++++++++++++++++++++++++++++++++++++
 include/linux/mtd/spinand.h   |   3 +
 4 files changed, 154 insertions(+), 1 deletion(-)
 create mode 100644 drivers/mtd/nand/spi/micron.c

diff --git a/drivers/mtd/nand/spi/Makefile b/drivers/mtd/nand/spi/Makefile
index feb79a1d1b46..79a1f1e79221 100644
--- a/drivers/mtd/nand/spi/Makefile
+++ b/drivers/mtd/nand/spi/Makefile
@@ -1,2 +1,2 @@
-spinand-objs := core.o
+spinand-objs := core.o micron.o
 obj-$(CONFIG_MTD_SPI_NAND) += spinand.o
diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c
index faad9bc93775..a4b8906d7084 100644
--- a/drivers/mtd/nand/spi/core.c
+++ b/drivers/mtd/nand/spi/core.c
@@ -767,8 +767,25 @@ static const struct nand_ops spinand_ops = {
 	.isbad = spinand_isbad,
 };
 
+static const struct spinand_manufacturer *spinand_manufacturers[] = {
+	&micron_spinand_manufacturer,
+};
+
 static int spinand_manufacturer_detect(struct spinand_device *spinand)
 {
+	unsigned int i;
+	int ret;
+
+	for (i = 0; i < ARRAY_SIZE(spinand_manufacturers); i++) {
+		ret = spinand_manufacturers[i]->ops->detect(spinand);
+		if (ret > 0) {
+			spinand->manufacturer = spinand_manufacturers[i];
+			return 0;
+		} else if (ret < 0) {
+			return ret;
+		}
+	}
+
 	return -ENOTSUPP;
 }
 
diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c
new file mode 100644
index 000000000000..9c4381d6847b
--- /dev/null
+++ b/drivers/mtd/nand/spi/micron.c
@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2016-2017 Micron Technology, Inc.
+ *
+ * Authors:
+ *	Peter Pan <peterpandong@micron.com>
+ */
+
+#include <linux/device.h>
+#include <linux/kernel.h>
+#include <linux/mtd/spinand.h>
+
+#define SPINAND_MFR_MICRON		0x2c
+
+#define MICRON_STATUS_ECC_MASK		GENMASK(7, 4)
+#define MICRON_STATUS_ECC_NO_BITFLIPS	(0 << 4)
+#define MICRON_STATUS_ECC_1TO3_BITFLIPS	(1 << 4)
+#define MICRON_STATUS_ECC_4TO6_BITFLIPS	(3 << 4)
+#define MICRON_STATUS_ECC_7TO8_BITFLIPS	(5 << 4)
+
+static SPINAND_OP_VARIANTS(read_cache_variants,
+		SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
+		SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
+		SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
+		SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
+		SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
+		SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
+
+static SPINAND_OP_VARIANTS(write_cache_variants,
+		SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
+		SPINAND_PROG_LOAD(true, 0, NULL, 0));
+
+static SPINAND_OP_VARIANTS(update_cache_variants,
+		SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
+		SPINAND_PROG_LOAD(false, 0, NULL, 0));
+
+static int mt29f2g01abagd_ooblayout_ecc(struct mtd_info *mtd, int section,
+					struct mtd_oob_region *region)
+{
+	if (section)
+		return -ERANGE;
+
+	region->offset = 64;
+	region->length = 64;
+
+	return 0;
+}
+
+static int mt29f2g01abagd_ooblayout_free(struct mtd_info *mtd, int section,
+					 struct mtd_oob_region *region)
+{
+	if (section)
+		return -ERANGE;
+
+	/* Reserve 2 bytes for the BBM. */
+	region->offset = 2;
+	region->length = 62;
+
+	return 0;
+}
+
+static const struct mtd_ooblayout_ops mt29f2g01abagd_ooblayout = {
+	.ecc = mt29f2g01abagd_ooblayout_ecc,
+	.free = mt29f2g01abagd_ooblayout_free,
+};
+
+static int mt29f2g01abagd_ecc_get_status(struct spinand_device *spinand,
+					 u8 status)
+{
+	switch (status & MICRON_STATUS_ECC_MASK) {
+	case STATUS_ECC_NO_BITFLIPS:
+		return 0;
+
+	case STATUS_ECC_UNCOR_ERROR:
+		return -EBADMSG;
+
+	case MICRON_STATUS_ECC_1TO3_BITFLIPS:
+		return 3;
+
+	case MICRON_STATUS_ECC_4TO6_BITFLIPS:
+		return 6;
+
+	case MICRON_STATUS_ECC_7TO8_BITFLIPS:
+		return 8;
+
+	default:
+		break;
+	}
+
+	return -EINVAL;
+}
+
+static const struct spinand_info micron_spinand_table[] = {
+	SPINAND_INFO("MT29F2G01ABAGD", 0x24,
+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     0,
+		     SPINAND_ECCINFO(&mt29f2g01abagd_ooblayout,
+				     mt29f2g01abagd_ecc_get_status)),
+};
+
+static int micron_spinand_detect(struct spinand_device *spinand)
+{
+	u8 *id = spinand->id.data;
+	int ret;
+
+	/*
+	 * Micron SPI NAND read ID need a dummy byte,
+	 * so the first byte in raw_id is dummy.
+	 */
+	if (id[1] != SPINAND_MFR_MICRON)
+		return 0;
+
+	ret = spinand_match_and_init(spinand, micron_spinand_table,
+				     ARRAY_SIZE(micron_spinand_table), id[2]);
+	if (ret)
+		return ret;
+
+	return 1;
+}
+
+static const struct spinand_manufacturer_ops micron_spinand_manuf_ops = {
+	.detect = micron_spinand_detect,
+};
+
+const struct spinand_manufacturer micron_spinand_manufacturer = {
+	.id = SPINAND_MFR_MICRON,
+	.name = "Micron",
+	.ops = &micron_spinand_manuf_ops,
+};
diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h
index 17a4584c0017..11a18c1993e8 100644
--- a/include/linux/mtd/spinand.h
+++ b/include/linux/mtd/spinand.h
@@ -192,6 +192,9 @@ struct spinand_manufacturer {
 	const struct spinand_manufacturer_ops *ops;
 };
 
+/* SPI NAND manufacturers */
+extern const struct spinand_manufacturer micron_spinand_manufacturer;
+
 /**
  * struct spinand_op_variants - SPI NAND operation variants
  * @ops: the list of variants for a given operation
-- 
2.14.1

[PATCH v7 5/5] mtd: nand: spi: Add initial support for Winbond W25M02GV

[Boris Brezillon]

From: Frieder Schrempf <frieder.schrempf@exceet.de>

Signed-off-by: Frieder Schrempf <frieder.schrempf@exceet.de>
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
---
 drivers/mtd/nand/spi/Makefile  |   2 +-
 drivers/mtd/nand/spi/core.c    |   1 +
 drivers/mtd/nand/spi/winbond.c | 141 +++++++++++++++++++++++++++++++++++++++++
 include/linux/mtd/spinand.h    |   1 +
 4 files changed, 144 insertions(+), 1 deletion(-)
 create mode 100644 drivers/mtd/nand/spi/winbond.c

diff --git a/drivers/mtd/nand/spi/Makefile b/drivers/mtd/nand/spi/Makefile
index 79a1f1e79221..983a94f7f205 100644
--- a/drivers/mtd/nand/spi/Makefile
+++ b/drivers/mtd/nand/spi/Makefile
@@ -1,2 +1,2 @@
-spinand-objs := core.o micron.o
+spinand-objs := core.o micron.o winbond.o
 obj-$(CONFIG_MTD_SPI_NAND) += spinand.o
diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c
index a4b8906d7084..057adb5e1a0c 100644
--- a/drivers/mtd/nand/spi/core.c
+++ b/drivers/mtd/nand/spi/core.c
@@ -769,6 +769,7 @@ static const struct nand_ops spinand_ops = {
 
 static const struct spinand_manufacturer *spinand_manufacturers[] = {
 	&micron_spinand_manufacturer,
+	&winbond_spinand_manufacturer,
 };
 
 static int spinand_manufacturer_detect(struct spinand_device *spinand)
diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c
new file mode 100644
index 000000000000..67baa1b32c00
--- /dev/null
+++ b/drivers/mtd/nand/spi/winbond.c
@@ -0,0 +1,141 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2017 exceet electronics GmbH
+ *
+ * Authors:
+ *	Frieder Schrempf <frieder.schrempf@exceet.de>
+ *	Boris Brezillon <boris.brezillon@bootlin.com>
+ */
+
+#include <linux/device.h>
+#include <linux/kernel.h>
+#include <linux/mtd/spinand.h>
+
+#define SPINAND_MFR_WINBOND		0xEF
+
+#define WINBOND_CFG_BUF_READ		BIT(3)
+
+static SPINAND_OP_VARIANTS(read_cache_variants,
+		SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
+		SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
+		SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
+		SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
+		SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
+		SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
+
+static SPINAND_OP_VARIANTS(write_cache_variants,
+		SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
+		SPINAND_PROG_LOAD(true, 0, NULL, 0));
+
+static SPINAND_OP_VARIANTS(update_cache_variants,
+		SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
+		SPINAND_PROG_LOAD(false, 0, NULL, 0));
+
+static int w25m02gv_ooblayout_ecc(struct mtd_info *mtd, int section,
+				  struct mtd_oob_region *region)
+{
+	if (section > 3)
+		return -ERANGE;
+
+	region->offset = (16 * section) + 8;
+	region->length = 8;
+
+	return 0;
+}
+
+static int w25m02gv_ooblayout_free(struct mtd_info *mtd, int section,
+				   struct mtd_oob_region *region)
+{
+	if (section > 3)
+		return -ERANGE;
+
+	region->offset = (16 * section) + 2;
+	region->length = 6;
+
+	return 0;
+}
+
+static const struct mtd_ooblayout_ops w25m02gv_ooblayout = {
+	.ecc = w25m02gv_ooblayout_ecc,
+	.free = w25m02gv_ooblayout_free,
+};
+
+static int w25m02gv_select_target(struct spinand_device *spinand,
+				  unsigned int target)
+{
+	struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(0xc2, 1),
+					  SPI_MEM_OP_NO_ADDR,
+					  SPI_MEM_OP_NO_DUMMY,
+					  SPI_MEM_OP_DATA_OUT(1,
+							spinand->scratchbuf,
+							1));
+
+	*spinand->scratchbuf = target;
+	return spi_mem_exec_op(spinand->spimem, &op);
+}
+
+static const struct spinand_info winbond_spinand_table[] = {
+	SPINAND_INFO("W25M02GV", 0xAB,
+		     NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 2),
+		     NAND_ECCREQ(1, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     0,
+		     SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL),
+		     SPINAND_SELECT_TARGET(w25m02gv_select_target)),
+};
+
+/**
+ * winbond_spinand_detect - initialize device related part in spinand_device
+ * struct if it is a Winbond device.
+ * @spinand: SPI NAND device structure
+ */
+static int winbond_spinand_detect(struct spinand_device *spinand)
+{
+	u8 *id = spinand->id.data;
+	int ret;
+
+	/*
+	 * Winbond SPI NAND read ID need a dummy byte,
+	 * so the first byte in raw_id is dummy.
+	 */
+	if (id[1] != SPINAND_MFR_WINBOND)
+		return 0;
+
+	ret = spinand_match_and_init(spinand, winbond_spinand_table,
+				     ARRAY_SIZE(winbond_spinand_table), id[2]);
+	if (ret)
+		return ret;
+
+	return 1;
+}
+
+static int winbond_spinand_init(struct spinand_device *spinand)
+{
+	struct nand_device *nand = spinand_to_nand(spinand);
+	unsigned int i;
+
+	/*
+	 * Make sure all dies are in buffer read mode and not continuous read
+	 * mode.
+	 */
+	for (i = 0; i < nand->memorg.ntargets; i++) {
+		spinand_select_target(spinand, i);
+		spinand_upd_cfg(spinand, WINBOND_CFG_BUF_READ,
+				WINBOND_CFG_BUF_READ);
+	}
+
+	return 0;
+}
+
+static const struct spinand_manufacturer_ops winbond_spinand_manuf_ops = {
+	.detect = winbond_spinand_detect,
+	.init = winbond_spinand_init,
+};
+
+const struct spinand_manufacturer winbond_spinand_manufacturer = {
+	.id = SPINAND_MFR_WINBOND,
+	.name = "Winbond",
+	.ops = &winbond_spinand_manuf_ops,
+};
diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h
index 11a18c1993e8..31d993628a0d 100644
--- a/include/linux/mtd/spinand.h
+++ b/include/linux/mtd/spinand.h
@@ -194,6 +194,7 @@ struct spinand_manufacturer {
 
 /* SPI NAND manufacturers */
 extern const struct spinand_manufacturer micron_spinand_manufacturer;
+extern const struct spinand_manufacturer winbond_spinand_manufacturer;
 
 /**
  * struct spinand_op_variants - SPI NAND operation variants
-- 
2.14.1

Re: [PATCH v7 5/5] mtd: nand: spi: Add initial support for Winbond W25M02GV

[Miquel Raynal]

Hi Boris,

On Tue, 15 May 2018 17:08:25 +0200, Boris Brezillon
<boris.brezillon@bootlin.com> wrote:

> From: Frieder Schrempf <frieder.schrempf@exceet.de>
> 
> Signed-off-by: Frieder Schrempf <frieder.schrempf@exceet.de>
> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
> ---

It looks like the commit message is missing?

Regards,
Miquèl

Re: [PATCH v7 5/5] mtd: nand: spi: Add initial support for Winbond W25M02GV

[Boris Brezillon]

On Wed, 16 May 2018 00:59:51 +0200
Miquel Raynal <miquel.raynal@bootlin.com> wrote:

> Hi Boris,
> 
> On Tue, 15 May 2018 17:08:25 +0200, Boris Brezillon
> <boris.brezillon@bootlin.com> wrote:
> 
> > From: Frieder Schrempf <frieder.schrempf@exceet.de>
> > 
> > Signed-off-by: Frieder Schrempf <frieder.schrempf@exceet.de>
> > Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
> > ---  
> 
> It looks like the commit message is missing?

Will add one.

Thanks,

Boris

RE: [PATCH v7 0/5] mtd: Add a SPI NAND driver

[Prabhakar Kushwaha]

Dear Boris,


> -----Original Message-----
> From: linux-mtd [mailto:linux-mtd-bounces@lists.infradead.org] On Behalf
> Of Boris Brezillon
> Sent: Tuesday, May 15, 2018 8:38 PM
> To: David Woodhouse <dwmw2@infradead.org>; Brian Norris
> <computersforpeace@gmail.com>; Boris Brezillon
> <boris.brezillon@bootlin.com>; Marek Vasut <marek.vasut@gmail.com>;
> Richard Weinberger <richard@nod.at>; linux-mtd@lists.infradead.org;
> Miquel Raynal <miquel.raynal@bootlin.com>
> Cc: Peter Pan <peterpansjtu@gmail.com>; Frieder Schrempf
> <frieder.schrempf@exceet.de>; Vignesh R <vigneshr@ti.com>; Xiangsheng
> Hou <xiangsheng.hou@mediatek.com>
> Subject: [PATCH v7 0/5] mtd: Add a SPI NAND driver
> 
> Hello,
> 
> This is a brand new version of the SPI NAND framework initially proposed by
> Peter. Note that this version has little in common with the previous one,
> mainly because it's been reworked to use the SPI mem interface (which
> allowed us to get rid of the complex NAND initialization/registration logic).
> 
> Also, this version now natively supports on-die ECC and multi-die chips
> (which was required to expose the 256MB of the W25M02GV chip). I know I
> initially asked Peter to not support on-die ECC in the first version of the
> framework so that we can work on a proper abstraction for ECC controllers,
> but I ended up implementing it, since all the chips seem to have on-die ECC
> and the implementation was not that complicated.
> 
> I'm not giving up on the "ECC controller abstraction" stuff, but with this initial
> implementation we at least have usable SPI NAND support, which should
> give us some time for complex setups with external ECC controllers.
> 
> Just a few details about the patches in this series:
> 
> Patch 1 is just extending the nand_page_io_req structure to pass
> information about the access mode (ECC enabled/disabled) so that we can
> use that in the SPI NAND framework to decide whether on-die ECC should be
> enabled or not.
> 
> Patch 2 is adding the core infrastructure to handle SPI NANDs, and patch 3 is
> decribing the SPI NAND bindings.
> 
> Patch 4 and 5 add support for 2 different chips, one from Micron and one
> from Winbond.
> 
> Comments/reviews are welcome.
> 
> Thanks,
> 
> Boris
> 
> v7 changes:
> - Use the spi-mem interface

This is putting requirement for having controller driver in  driver/spi. 
What about the controllers which are supporting NOR and NAND flash. How they are going to co-exist. 

Are we supposed to have 2 flavor of driver. One in driver/mtd/spi-nor and driver/spi?

--pk

Re: [PATCH v7 0/5] mtd: Add a SPI NAND driver

[Boris Brezillon]

On Thu, 17 May 2018 06:33:36 +0000
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> wrote:

> Dear Boris,
> 
> 
> > -----Original Message-----
> > From: linux-mtd [mailto:linux-mtd-bounces@lists.infradead.org] On Behalf
> > Of Boris Brezillon
> > Sent: Tuesday, May 15, 2018 8:38 PM
> > To: David Woodhouse <dwmw2@infradead.org>; Brian Norris
> > <computersforpeace@gmail.com>; Boris Brezillon
> > <boris.brezillon@bootlin.com>; Marek Vasut <marek.vasut@gmail.com>;
> > Richard Weinberger <richard@nod.at>; linux-mtd@lists.infradead.org;
> > Miquel Raynal <miquel.raynal@bootlin.com>
> > Cc: Peter Pan <peterpansjtu@gmail.com>; Frieder Schrempf
> > <frieder.schrempf@exceet.de>; Vignesh R <vigneshr@ti.com>; Xiangsheng
> > Hou <xiangsheng.hou@mediatek.com>
> > Subject: [PATCH v7 0/5] mtd: Add a SPI NAND driver
> > 
> > Hello,
> > 
> > This is a brand new version of the SPI NAND framework initially proposed by
> > Peter. Note that this version has little in common with the previous one,
> > mainly because it's been reworked to use the SPI mem interface (which
> > allowed us to get rid of the complex NAND initialization/registration logic).
> > 
> > Also, this version now natively supports on-die ECC and multi-die chips
> > (which was required to expose the 256MB of the W25M02GV chip). I know I
> > initially asked Peter to not support on-die ECC in the first version of the
> > framework so that we can work on a proper abstraction for ECC controllers,
> > but I ended up implementing it, since all the chips seem to have on-die ECC
> > and the implementation was not that complicated.
> > 
> > I'm not giving up on the "ECC controller abstraction" stuff, but with this initial
> > implementation we at least have usable SPI NAND support, which should
> > give us some time for complex setups with external ECC controllers.
> > 
> > Just a few details about the patches in this series:
> > 
> > Patch 1 is just extending the nand_page_io_req structure to pass
> > information about the access mode (ECC enabled/disabled) so that we can
> > use that in the SPI NAND framework to decide whether on-die ECC should be
> > enabled or not.
> > 
> > Patch 2 is adding the core infrastructure to handle SPI NANDs, and patch 3 is
> > decribing the SPI NAND bindings.
> > 
> > Patch 4 and 5 add support for 2 different chips, one from Micron and one
> > from Winbond.
> > 
> > Comments/reviews are welcome.
> > 
> > Thanks,
> > 
> > Boris
> > 
> > v7 changes:
> > - Use the spi-mem interface  
> 
> This is putting requirement for having controller driver in  driver/spi. 

Yes.

> What about the controllers which are supporting NOR and NAND flash. How they are going to co-exist.

Can you give an example (with a datasheet or a detailed description) of
what you call a controller that supports NOR or NAND. AFAICT, all SPI
controllers can support NANDs and NORs, because all they do is send
spi-mem operations to the device, no matter if the operation is NAND
or NOR related.

> 
> Are we supposed to have 2 flavor of driver. One in driver/mtd/spi-nor and driver/spi?

Definitely not. You should have one driver in drivers/spi/ and the SPI
NOR layer should access this controller through the m25p80 driver. If
you need features that are not yet supported by the spi-mem API, then
we should discuss it, 'cause the goal is to have all SPI controller
drivers in drivers/spi/ instead of creating one interface per memory
type.

RE: [PATCH v7 0/5] mtd: Add a SPI NAND driver

[Prabhakar Kushwaha]

> -----Original Message-----
> From: Boris Brezillon [mailto:boris.brezillon@bootlin.com]
> Sent: Thursday, May 17, 2018 12:35 PM
> To: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
> Cc: David Woodhouse <dwmw2@infradead.org>; Brian Norris
> <computersforpeace@gmail.com>; Marek Vasut
> <marek.vasut@gmail.com>; Richard Weinberger <richard@nod.at>; linux-
> mtd@lists.infradead.org; Miquel Raynal <miquel.raynal@bootlin.com>; Peter
> Pan <peterpansjtu@gmail.com>; Frieder Schrempf
> <frieder.schrempf@exceet.de>; Vignesh R <vigneshr@ti.com>; Xiangsheng
> Hou <xiangsheng.hou@mediatek.com>; Ashish Kumar
> <ashish.kumar@nxp.com>; Yogesh Narayan Gaur
> <yogeshnarayan.gaur@nxp.com>; Poonam Aggrwal
> <poonam.aggrwal@nxp.com>
> Subject: Re: [PATCH v7 0/5] mtd: Add a SPI NAND driver
> 
> On Thu, 17 May 2018 06:33:36 +0000
> Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> wrote:
> 
> > Dear Boris,
> >
> >
> > > -----Original Message-----
> > > From: linux-mtd [mailto:linux-mtd-bounces@lists.infradead.org] On
> > > Behalf Of Boris Brezillon
> > > Sent: Tuesday, May 15, 2018 8:38 PM
> > > To: David Woodhouse <dwmw2@infradead.org>; Brian Norris
> > > <computersforpeace@gmail.com>; Boris Brezillon
> > > <boris.brezillon@bootlin.com>; Marek Vasut <marek.vasut@gmail.com>;
> > > Richard Weinberger <richard@nod.at>; linux-mtd@lists.infradead.org;
> > > Miquel Raynal <miquel.raynal@bootlin.com>
> > > Cc: Peter Pan <peterpansjtu@gmail.com>; Frieder Schrempf
> > > <frieder.schrempf@exceet.de>; Vignesh R <vigneshr@ti.com>;
> > > Xiangsheng Hou <xiangsheng.hou@mediatek.com>
> > > Subject: [PATCH v7 0/5] mtd: Add a SPI NAND driver
> > >
> > > Hello,
> > >
> > > This is a brand new version of the SPI NAND framework initially
> > > proposed by Peter. Note that this version has little in common with
> > > the previous one, mainly because it's been reworked to use the SPI
> > > mem interface (which allowed us to get rid of the complex NAND
> initialization/registration logic).
> > >
> > > Also, this version now natively supports on-die ECC and multi-die
> > > chips (which was required to expose the 256MB of the W25M02GV chip).
> > > I know I initially asked Peter to not support on-die ECC in the
> > > first version of the framework so that we can work on a proper
> > > abstraction for ECC controllers, but I ended up implementing it,
> > > since all the chips seem to have on-die ECC and the implementation was
> not that complicated.
> > >
> > > I'm not giving up on the "ECC controller abstraction" stuff, but
> > > with this initial implementation we at least have usable SPI NAND
> > > support, which should give us some time for complex setups with
> external ECC controllers.
> > >
> > > Just a few details about the patches in this series:
> > >
> > > Patch 1 is just extending the nand_page_io_req structure to pass
> > > information about the access mode (ECC enabled/disabled) so that we
> > > can use that in the SPI NAND framework to decide whether on-die ECC
> > > should be enabled or not.
> > >
> > > Patch 2 is adding the core infrastructure to handle SPI NANDs, and
> > > patch 3 is decribing the SPI NAND bindings.
> > >
> > > Patch 4 and 5 add support for 2 different chips, one from Micron and
> > > one from Winbond.
> > >
> > > Comments/reviews are welcome.
> > >
> > > Thanks,
> > >
> > > Boris
> > >
> > > v7 changes:
> > > - Use the spi-mem interface
> >
> > This is putting requirement for having controller driver in  driver/spi.
> 
> Yes.
> 
> > What about the controllers which are supporting NOR and NAND flash.
> How they are going to co-exist.
> 
> Can you give an example (with a datasheet or a detailed description) of what
> you call a controller that supports NOR or NAND. AFAICT, all SPI controllers
> can support NANDs and NORs, because all they do is send spi-mem
> operations to the device, no matter if the operation is NAND or NOR related.
> 
> >
> > Are we supposed to have 2 flavor of driver. One in driver/mtd/spi-nor and
> driver/spi?
> 
> Definitely not. You should have one driver in drivers/spi/ and the SPI NOR
> layer should access this controller through the m25p80 driver. If you need
> features that are not yet supported by the spi-mem API, then we should
> discuss it, 'cause the goal is to have all SPI controller drivers in drivers/spi/
> instead of creating one interface per memory type.
> 

Currently NXP has fsl_qspi driver is placed in driver/mtd/spi-nor.  QSPI controller(hardware) can support both SPI NOR,  SPI NAND flashes.

fsl_qspi is currently supporting Serial NOR.  

As NXP will be adding support SPI NAND with fsl_qspi driver in near future.
This means  a transition is required from driver/mtd/spi-nor/fsl_qspi.c to driver/spi. 

Hence driver/spi/fsl_qspi has to support both SP NOR and SP NAND under control of mtd/nand or mtd/mp2580.c driver. 

--pk

Re: [PATCH v7 0/5] mtd: Add a SPI NAND driver

[Frieder Schrempf]

Hi Prabhakar,

On 17.05.2018 12:01, Prabhakar Kushwaha wrote:
> 
>> -----Original Message-----
>> From: Boris Brezillon [mailto:boris.brezillon@bootlin.com]
>> Sent: Thursday, May 17, 2018 12:35 PM
>> To: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
>> Cc: David Woodhouse <dwmw2@infradead.org>; Brian Norris
>> <computersforpeace@gmail.com>; Marek Vasut
>> <marek.vasut@gmail.com>; Richard Weinberger <richard@nod.at>; linux-
>> mtd@lists.infradead.org; Miquel Raynal <miquel.raynal@bootlin.com>; Peter
>> Pan <peterpansjtu@gmail.com>; Frieder Schrempf
>> <frieder.schrempf@exceet.de>; Vignesh R <vigneshr@ti.com>; Xiangsheng
>> Hou <xiangsheng.hou@mediatek.com>; Ashish Kumar
>> <ashish.kumar@nxp.com>; Yogesh Narayan Gaur
>> <yogeshnarayan.gaur@nxp.com>; Poonam Aggrwal
>> <poonam.aggrwal@nxp.com>
>> Subject: Re: [PATCH v7 0/5] mtd: Add a SPI NAND driver
>>
>> On Thu, 17 May 2018 06:33:36 +0000
>> Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> wrote:
>>
>>> Dear Boris,
>>>
>>>
>>>> -----Original Message-----
>>>> From: linux-mtd [mailto:linux-mtd-bounces@lists.infradead.org] On
>>>> Behalf Of Boris Brezillon
>>>> Sent: Tuesday, May 15, 2018 8:38 PM
>>>> To: David Woodhouse <dwmw2@infradead.org>; Brian Norris
>>>> <computersforpeace@gmail.com>; Boris Brezillon
>>>> <boris.brezillon@bootlin.com>; Marek Vasut <marek.vasut@gmail.com>;
>>>> Richard Weinberger <richard@nod.at>; linux-mtd@lists.infradead.org;
>>>> Miquel Raynal <miquel.raynal@bootlin.com>
>>>> Cc: Peter Pan <peterpansjtu@gmail.com>; Frieder Schrempf
>>>> <frieder.schrempf@exceet.de>; Vignesh R <vigneshr@ti.com>;
>>>> Xiangsheng Hou <xiangsheng.hou@mediatek.com>
>>>> Subject: [PATCH v7 0/5] mtd: Add a SPI NAND driver
>>>>
>>>> Hello,
>>>>
>>>> This is a brand new version of the SPI NAND framework initially
>>>> proposed by Peter. Note that this version has little in common with
>>>> the previous one, mainly because it's been reworked to use the SPI
>>>> mem interface (which allowed us to get rid of the complex NAND
>> initialization/registration logic).
>>>>
>>>> Also, this version now natively supports on-die ECC and multi-die
>>>> chips (which was required to expose the 256MB of the W25M02GV chip).
>>>> I know I initially asked Peter to not support on-die ECC in the
>>>> first version of the framework so that we can work on a proper
>>>> abstraction for ECC controllers, but I ended up implementing it,
>>>> since all the chips seem to have on-die ECC and the implementation was
>> not that complicated.
>>>>
>>>> I'm not giving up on the "ECC controller abstraction" stuff, but
>>>> with this initial implementation we at least have usable SPI NAND
>>>> support, which should give us some time for complex setups with
>> external ECC controllers.
>>>>
>>>> Just a few details about the patches in this series:
>>>>
>>>> Patch 1 is just extending the nand_page_io_req structure to pass
>>>> information about the access mode (ECC enabled/disabled) so that we
>>>> can use that in the SPI NAND framework to decide whether on-die ECC
>>>> should be enabled or not.
>>>>
>>>> Patch 2 is adding the core infrastructure to handle SPI NANDs, and
>>>> patch 3 is decribing the SPI NAND bindings.
>>>>
>>>> Patch 4 and 5 add support for 2 different chips, one from Micron and
>>>> one from Winbond.
>>>>
>>>> Comments/reviews are welcome.
>>>>
>>>> Thanks,
>>>>
>>>> Boris
>>>>
>>>> v7 changes:
>>>> - Use the spi-mem interface
>>>
>>> This is putting requirement for having controller driver in  driver/spi.
>>
>> Yes.
>>
>>> What about the controllers which are supporting NOR and NAND flash.
>> How they are going to co-exist.
>>
>> Can you give an example (with a datasheet or a detailed description) of what
>> you call a controller that supports NOR or NAND. AFAICT, all SPI controllers
>> can support NANDs and NORs, because all they do is send spi-mem
>> operations to the device, no matter if the operation is NAND or NOR related.
>>
>>>
>>> Are we supposed to have 2 flavor of driver. One in driver/mtd/spi-nor and
>> driver/spi?
>>
>> Definitely not. You should have one driver in drivers/spi/ and the SPI NOR
>> layer should access this controller through the m25p80 driver. If you need
>> features that are not yet supported by the spi-mem API, then we should
>> discuss it, 'cause the goal is to have all SPI controller drivers in drivers/spi/
>> instead of creating one interface per memory type.
>>
> 
> Currently NXP has fsl_qspi driver is placed in driver/mtd/spi-nor.  QSPI controller(hardware) can support both SPI NOR,  SPI NAND flashes.
> 
> fsl_qspi is currently supporting Serial NOR.
> 
> As NXP will be adding support SPI NAND with fsl_qspi driver in near future.
> This means  a transition is required from driver/mtd/spi-nor/fsl_qspi.c to driver/spi.

I'm currently working on this transition based on Boris' PoC driver [1]. 
I have to do some testing with SPI NOR and then I think I'm ready to 
prepare a first version. Have you already started working on this?

Also it would be nice to test this with hardware that uses multiple 
(2-4) SPI NAND / SPI NOR chips on both buses and using chip selects. Do 
you have such hardware available for testing?

> 
> Hence driver/spi/fsl_qspi has to support both SP NOR and SP NAND under control of mtd/nand or mtd/mp2580.c driver.

The new driver will use the spi-mem interface and therefore can be used 
by mtd/nand/spi and by m25p80.c. So it doesn't need to support two 
interfaces.

Regards,

Frieder

[1] 
https://github.com/bbrezillon/linux-0day/blob/spi-mem/drivers/spi/spi-fsl-qspi.c

> 
> --pk
> 
> 
> 
> 

Re: [PATCH v7 2/5] mtd: nand: Add core infrastructure to support SPI NANDs

[Frieder Schrempf]

Hi Boris,

On 15.05.2018 17:08, Boris Brezillon wrote:
> From: Peter Pan <peterpandong@micron.com>
> 
> Add a SPI NAND framework based on the generic NAND framework and the
> spi-mem infrastructure.
> 
> In its current state, this framework supports the following features:
> 
> - single/dual/quad IO modes
> - on-die ECC
> 
> Signed-off-by: Peter Pan <peterpandong@micron.com>
> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
> ---
>   drivers/mtd/nand/Kconfig      |    1 +
>   drivers/mtd/nand/Makefile     |    1 +
>   drivers/mtd/nand/spi/Kconfig  |    7 +
>   drivers/mtd/nand/spi/Makefile |    2 +
>   drivers/mtd/nand/spi/core.c   | 1122 +++++++++++++++++++++++++++++++++++++++++
>   include/linux/mtd/spinand.h   |  415 +++++++++++++++
>   include/linux/spi/spi-mem.h   |    4 +-
>   7 files changed, 1551 insertions(+), 1 deletion(-)
>   create mode 100644 drivers/mtd/nand/spi/Kconfig
>   create mode 100644 drivers/mtd/nand/spi/Makefile
>   create mode 100644 drivers/mtd/nand/spi/core.c
>   create mode 100644 include/linux/mtd/spinand.h
> 

[...]

> +
> +/**
> + * spinand_match_and_init() - Try to find a match between a device ID and an
> + *			      entry in a spinand_info table
> + * @spinand: SPI NAND object
> + * @table: SPI NAND device description table
> + * @table_size: size of the device description table
> + *
> + * Should be used by SPI NAND manufacturer drivers when they want to find a
> + * match between a device ID retrieved through the READ_ID command and an
> + * entry in the SPI NAND description table. If a match is found, the spinand
> + * object will be initialized with information provided by the matching
> + * spinand_info entry.
> + *
> + * Return: 0 on success, a negative error code otherwise.
> + */
> +int spinand_match_and_init(struct spinand_device *spinand,
> +			   const struct spinand_info *table,
> +			   unsigned int table_size, u8 devid)
> +{
> +	struct nand_device *nand = spinand_to_nand(spinand);
> +	unsigned int i;
> +
> +	for (i = 0; i < table_size; i++) {
> +		const struct spinand_info *info = &table[i];
> +		const struct spi_mem_op *op;
> +
> +		if (devid != info->devid)
> +			continue;
> +
> +		nand->memorg = table[i].memorg;
> +		nand->eccreq = table[i].eccreq;
> +		spinand->eccinfo = table[i].eccinfo;
> +		spinand->flags = table[i].flags;
> +		spinand->select_target = table[i].select_target;
> +
> +		op = spinand_select_op_variant(spinand,
> +					       info->op_variants.read_cache);
> +		if (!op)
> +			return -ENOTSUPP;
> +
> +		spinand->op_templates.read_cache = op;
> +
> +		op = spinand_select_op_variant(spinand,
> +					       info->op_variants.write_cache);
> +		if (!op)
> +			return -ENOTSUPP;
> +
> +		spinand->op_templates.write_cache = op;
> +
> +		op = spinand_select_op_variant(spinand,
> +					       info->op_variants.update_cache);
> +		spinand->op_templates.update_cache = op;
> +
> +		spinand_init_quad_enable(spinand);
> +
> +		return 0;
> +	}
> +
> +	return -ENOTSUPP;
> +}
> +
> +static int spinand_detect(struct spinand_device *spinand)
> +{
> +	struct device *dev = &spinand->spimem->spi->dev;
> +	struct nand_device *nand = &spinand->base;
> +	int ret;
> +
> +	ret = spinand_reset_op(spinand);
> +	if (ret)
> +		return ret;
> +
> +	ret = spinand_read_id_op(spinand, spinand->id.data);
> +	if (ret)
> +		return ret;
> +
> +	spinand->id.len = SPINAND_MAX_ID_LEN;
> +
> +	ret = spinand_manufacturer_detect(spinand);
> +	if (ret) {
> +		dev_err(dev, "unknown raw ID %*phN\n", SPINAND_MAX_ID_LEN,
> +			spinand->id.data);
> +		return ret;
> +	}
> +
> +	if (nand->memorg.ntargets > 1 && !spinand->select_target) {
> +		dev_err(dev,
> +			"SPI NANDs with more than one die must implement ->select_target()\n");
> +		return -EINVAL;
> +	}
> +
> +	dev_info(&spinand->spimem->spi->dev,
> +		 "%s SPI NAND was found.\n", spinand->manufacturer->name);
> +	dev_info(&spinand->spimem->spi->dev,
> +		 "%llu MiB, block size: %zu KiB, page size: %zu, OOB size: %u\n",
> +		 nanddev_size(nand) >> 20, nanddev_eraseblock_size(nand) >> 10,
> +		 nanddev_page_size(nand), nanddev_per_page_oobsize(nand));
> +
> +	return 0;
> +}
> +
> +static int spinand_noecc_ooblayout_ecc(struct mtd_info *mtd, int section,
> +				       struct mtd_oob_region *region)
> +{
> +	return -ERANGE;
> +}
> +
> +static int spinand_noecc_ooblayout_free(struct mtd_info *mtd, int section,
> +					struct mtd_oob_region *region)
> +{
> +	if (section)
> +		return -ERANGE;
> +
> +	/* Reserve 2 bytes for the BBM. */
> +	region->offset = 2;
> +	region->length = 62;
> +
> +	return 0;
> +}
> +
> +static const struct mtd_ooblayout_ops spinand_noecc_ooblayout = {
> +	.ecc = spinand_noecc_ooblayout_ecc,
> +	.free = spinand_noecc_ooblayout_free,
> +};
> +
> +static int spinand_init(struct spinand_device *spinand)
> +{
> +	struct device *dev = &spinand->spimem->spi->dev;
> +	struct mtd_info *mtd = spinand_to_mtd(spinand);
> +	struct nand_device *nand = mtd_to_nanddev(mtd);
> +	int ret, i;
> +
> +	/*
> +	 * We need a scratch buffer because the spi_mem interface requires that
> +	 * buf passed in spi_mem_op->data.buf be DMA-able.
> +	 */
> +	spinand->scratchbuf = kzalloc(SPINAND_MAX_ID_LEN, GFP_KERNEL);
> +	if (!spinand->scratchbuf)
> +		return -ENOMEM;
> +
> +	ret = spinand_detect(spinand);
> +	if (ret)
> +		goto err_free_bufs;
> +
> +	/*
> +	 * Use kzalloc() instead of devm_kzalloc() here, because some drivers
> +	 * may use this buffer for DMA access.
> +	 * Memory allocated by devm_ does not guarantee DMA-safe alignment.
> +	 */
> +	spinand->databuf = kzalloc(nanddev_page_size(nand) +
> +			       nanddev_per_page_oobsize(nand),
> +			       GFP_KERNEL);
> +	if (!spinand->databuf)
> +		goto err_free_bufs;
> +
> +	spinand->oobbuf = spinand->databuf + nanddev_page_size(nand);
> +
> +	ret = spinand_init_cfg_cache(spinand);

If the SPINAND_HAS_QE_BIT bit is set, then spinand_init_quad_enable() 
will try to use the config cache, but it hasn't been initialized at that 
time.

So spinand_init_cfg_cache() should probably be called earlier, before 
spinand_detect().

Regards,

Frieder

> +	if (ret)
> +		goto err_free_bufs;
> +
> +	ret = spinand_manufacturer_init(spinand);
> +	if (ret) {
> +		dev_err(dev,
> +			"Failed to initialize the SPI NAND chip (err = %d)\n",
> +			ret);
> +		goto err_free_bufs;
> +	}
> +
> +	/* After power up, all blocks are locked, so unlock it here. */
> +	for (i = 0; i < nand->memorg.ntargets; i++) {
> +		spinand_select_target(spinand, i);
> +		spinand_lock_block(spinand, BL_ALL_UNLOCKED);
> +	}
> +
> +	ret = nanddev_init(nand, &spinand_ops, THIS_MODULE);
> +	if (ret)
> +		goto err_free_bufs;
> +
> +	/*
> +	 * Right now, we don't support ECC, so let the whole oob
> +	 * area is available for user.
> +	 */
> +	mtd->_read_oob = spinand_mtd_read;
> +	mtd->_write_oob = spinand_mtd_write;
> +	mtd->_block_isbad = spinand_mtd_block_isbad;
> +	mtd->_block_markbad = spinand_mtd_block_markbad;
> +	mtd->_block_isreserved = spinand_mtd_block_isreserved;
> +	mtd->_erase = spinand_mtd_erase;
> +
> +	if (spinand->eccinfo.ooblayout)
> +		mtd_set_ooblayout(mtd, spinand->eccinfo.ooblayout);
> +	else
> +		mtd_set_ooblayout(mtd, &spinand_noecc_ooblayout);
> +
> +	ret = mtd_ooblayout_count_freebytes(mtd);
> +	if (ret < 0)
> +		goto err_cleanup_nanddev;
> +
> +	return 0;
> +
> +err_cleanup_nanddev:
> +	nanddev_cleanup(nand);
> +
> +err_free_bufs:
> +	kfree(spinand->databuf);
> +	kfree(spinand->scratchbuf);
> +	return ret;
> +}
> +
> +static void spinand_cleanup(struct spinand_device *spinand)
> +{
> +	struct nand_device *nand = &spinand->base;
> +
> +	spinand_manufacturer_cleanup(spinand);
> +	nanddev_cleanup(nand);
> +	kfree(spinand->databuf);
> +	kfree(spinand->scratchbuf);
> +}
> +
> +static int spinand_probe(struct spi_mem *mem)
> +{
> +	struct spinand_device *spinand;
> +	struct mtd_info *mtd;
> +	int ret;
> +
> +	spinand = devm_kzalloc(&mem->spi->dev, sizeof(*spinand),
> +			       GFP_KERNEL);
> +	if (!spinand)
> +		return -ENOMEM;
> +
> +	spinand->spimem = mem;
> +	spi_mem_set_drvdata(mem, spinand);
> +	spinand_set_of_node(spinand, mem->spi->dev.of_node);
> +	mutex_init(&spinand->lock);
> +	mtd = spinand_to_mtd(spinand);
> +	mtd->dev.parent = &mem->spi->dev;
> +
> +	ret = spinand_init(spinand);
> +	if (ret)
> +		return ret;
> +
> +	ret = mtd_device_register(mtd, NULL, 0);
> +	if (ret)
> +		goto err_spinand_cleanup;
> +
> +	return 0;
> +
> +err_spinand_cleanup:
> +	spinand_cleanup(spinand);
> +
> +	return ret;
> +}
> +
> +static int spinand_remove(struct spi_mem *mem)
> +{
> +	struct spinand_device *spinand;
> +	struct mtd_info *mtd;
> +	int ret;
> +
> +	spinand = spi_mem_get_drvdata(mem);
> +	mtd = spinand_to_mtd(spinand);
> +
> +	ret = mtd_device_unregister(mtd);
> +	if (ret)
> +		return ret;
> +
> +	spinand_cleanup(spinand);
> +
> +	return 0;
> +}
> +
> +static const struct spi_device_id spinand_ids[] = {
> +	{ .name = "spi-nand" },
> +	{ /* sentinel */ },
> +};
> +
> +#ifdef CONFIG_OF
> +static const struct of_device_id spinand_of_ids[] = {
> +	{ .compatible = "spi-nand" },
> +	{ /* sentinel */ },
> +};
> +#endif
> +
> +static struct spi_mem_driver spinand_drv = {
> +	.spidrv = {
> +		.id_table = spinand_ids,
> +		.driver = {
> +			.name = "spi-nand",
> +			.of_match_table = of_match_ptr(spinand_of_ids),
> +		},
> +	},
> +	.probe = spinand_probe,
> +	.remove = spinand_remove,
> +};
> +module_spi_mem_driver(spinand_drv);
> +
> +MODULE_DESCRIPTION("SPI NAND framework");
> +MODULE_AUTHOR("Peter Pan<peterpandong@micron.com>");
> +MODULE_LICENSE("GPL v2");

[...]

Re: [PATCH v7 2/5] mtd: nand: Add core infrastructure to support SPI NANDs

[Boris Brezillon]

On Tue, 29 May 2018 12:57:33 +0200
Frieder Schrempf <frieder.schrempf@exceet.de> wrote:

> > +static int spinand_init(struct spinand_device *spinand)
> > +{
> > +	struct device *dev = &spinand->spimem->spi->dev;
> > +	struct mtd_info *mtd = spinand_to_mtd(spinand);
> > +	struct nand_device *nand = mtd_to_nanddev(mtd);
> > +	int ret, i;
> > +
> > +	/*
> > +	 * We need a scratch buffer because the spi_mem interface requires that
> > +	 * buf passed in spi_mem_op->data.buf be DMA-able.
> > +	 */
> > +	spinand->scratchbuf = kzalloc(SPINAND_MAX_ID_LEN, GFP_KERNEL);
> > +	if (!spinand->scratchbuf)
> > +		return -ENOMEM;
> > +
> > +	ret = spinand_detect(spinand);
> > +	if (ret)
> > +		goto err_free_bufs;
> > +
> > +	/*
> > +	 * Use kzalloc() instead of devm_kzalloc() here, because some drivers
> > +	 * may use this buffer for DMA access.
> > +	 * Memory allocated by devm_ does not guarantee DMA-safe alignment.
> > +	 */
> > +	spinand->databuf = kzalloc(nanddev_page_size(nand) +
> > +			       nanddev_per_page_oobsize(nand),
> > +			       GFP_KERNEL);
> > +	if (!spinand->databuf)
> > +		goto err_free_bufs;
> > +
> > +	spinand->oobbuf = spinand->databuf + nanddev_page_size(nand);
> > +
> > +	ret = spinand_init_cfg_cache(spinand);  
> 
> If the SPINAND_HAS_QE_BIT bit is set, then spinand_init_quad_enable() 
> will try to use the config cache, but it hasn't been initialized at that 
> time.

Oops, you're right. I wonder how I could miss that one when testing it.
I guess you get a NULL pointer exception, right?

> 
> So spinand_init_cfg_cache() should probably be called earlier, before 
> spinand_detect().

I'd prefer to move the spinand_init_quad_enable() just after the
spinand_init_cfg_cache() one. Calling spinand_init_cfg_cache() does not
work because we don't know how many dies we have and the cfg cache has
one entry per die.

Re: [PATCH v7 2/5] mtd: nand: Add core infrastructure to support SPI NANDs

[Frieder Schrempf]

Hi Boris,

On 29.05.2018 15:35, Boris Brezillon wrote:
> On Tue, 29 May 2018 12:57:33 +0200
> Frieder Schrempf <frieder.schrempf@exceet.de> wrote:
> 
>>> +static int spinand_init(struct spinand_device *spinand)
>>> +{
>>> +	struct device *dev = &spinand->spimem->spi->dev;
>>> +	struct mtd_info *mtd = spinand_to_mtd(spinand);
>>> +	struct nand_device *nand = mtd_to_nanddev(mtd);
>>> +	int ret, i;
>>> +
>>> +	/*
>>> +	 * We need a scratch buffer because the spi_mem interface requires that
>>> +	 * buf passed in spi_mem_op->data.buf be DMA-able.
>>> +	 */
>>> +	spinand->scratchbuf = kzalloc(SPINAND_MAX_ID_LEN, GFP_KERNEL);
>>> +	if (!spinand->scratchbuf)
>>> +		return -ENOMEM;
>>> +
>>> +	ret = spinand_detect(spinand);
>>> +	if (ret)
>>> +		goto err_free_bufs;
>>> +
>>> +	/*
>>> +	 * Use kzalloc() instead of devm_kzalloc() here, because some drivers
>>> +	 * may use this buffer for DMA access.
>>> +	 * Memory allocated by devm_ does not guarantee DMA-safe alignment.
>>> +	 */
>>> +	spinand->databuf = kzalloc(nanddev_page_size(nand) +
>>> +			       nanddev_per_page_oobsize(nand),
>>> +			       GFP_KERNEL);
>>> +	if (!spinand->databuf)
>>> +		goto err_free_bufs;
>>> +
>>> +	spinand->oobbuf = spinand->databuf + nanddev_page_size(nand);
>>> +
>>> +	ret = spinand_init_cfg_cache(spinand);
>>
>> If the SPINAND_HAS_QE_BIT bit is set, then spinand_init_quad_enable()
>> will try to use the config cache, but it hasn't been initialized at that
>> time.
> 
> Oops, you're right. I wonder how I could miss that one when testing it.
> I guess you get a NULL pointer exception, right?

Yes.

> 
>>
>> So spinand_init_cfg_cache() should probably be called earlier, before
>> spinand_detect().
> 
> I'd prefer to move the spinand_init_quad_enable() just after the
> spinand_init_cfg_cache() one. Calling spinand_init_cfg_cache() does not
> work because we don't know how many dies we have and the cfg cache has
> one entry per die.

Yes true, so moving spinand_init_quad_enable() seems the way to go.

Re: [PATCH v7 2/5] mtd: nand: Add core infrastructure to support SPI NANDs

[Miquel Raynal]

Hi Boris,

On Tue, 15 May 2018 17:08:22 +0200, Boris Brezillon
<boris.brezillon@bootlin.com> wrote:

> +static bool spinand_isbad(struct nand_device *nand, const struct nand_pos *pos)
> +{
> +	struct spinand_device *spinand = nand_to_spinand(nand);
> +	struct nand_page_io_req req = {
> +		.pos = *pos,
> +		.ooblen = 2,
> +		.ooboffs = 0,
> +		.oobbuf.in = spinand->oobbuf,
> +		.mode = MTD_OPS_RAW,
> +	};
> +	int ret;
> +
> +	memset(spinand->oobbuf, 0, 2);
> +	spinand_select_target(spinand, pos->target);
> +	ret = spinand_read_page(spinand, &req, false);

I got a warning here because ret is not checked, maybe a:

        if (ret) {
                dev_err(dev, "...");
                return false;
        }

?

> +	if (spinand->oobbuf[0] != 0xff || spinand->oobbuf[1] != 0xff)
> +		return true;
> +
> +	return false;
> +}

Thanks,
Miquèl

Re: [PATCH v7 2/5] mtd: nand: Add core infrastructure to support SPI NANDs

[Boris Brezillon]

Hi Miquel,

On Thu, 31 May 2018 09:30:05 +0200
Miquel Raynal <miquel.raynal@bootlin.com> wrote:

> Hi Boris,
> 
> On Tue, 15 May 2018 17:08:22 +0200, Boris Brezillon
> <boris.brezillon@bootlin.com> wrote:
> 
> > +static bool spinand_isbad(struct nand_device *nand, const struct nand_pos *pos)
> > +{
> > +	struct spinand_device *spinand = nand_to_spinand(nand);
> > +	struct nand_page_io_req req = {
> > +		.pos = *pos,
> > +		.ooblen = 2,
> > +		.ooboffs = 0,
> > +		.oobbuf.in = spinand->oobbuf,
> > +		.mode = MTD_OPS_RAW,
> > +	};
> > +	int ret;
> > +
> > +	memset(spinand->oobbuf, 0, 2);
> > +	spinand_select_target(spinand, pos->target);
> > +	ret = spinand_read_page(spinand, &req, false);  
> 
> I got a warning here because ret is not checked, maybe a:
> 
>         if (ret) {
>                 dev_err(dev, "...");
>                 return false;
>         }

Or we could just ignore spinand_read_page() ret code since the first 2
bytes of spinand->oobbuf are initialized to 0, which means the block
will be considered bad if the read fails.

> 
> ?
> 
> > +	if (spinand->oobbuf[0] != 0xff || spinand->oobbuf[1] != 0xff)
> > +		return true;
> > +
> > +	return false;
> > +}  
> 
> Thanks,
> Miquèl

Re: [PATCH v7 1/5] mtd: nand: Pass mode information to nand_page_io_req

[Miquel Raynal]

Hi Boris,

On Tue, 15 May 2018 17:08:21 +0200, Boris Brezillon
<boris.brezillon@bootlin.com> wrote:

> The NAND sub-layers are likely to need the MTD_OPS_XXX mode information
> in order to decide if they should enable/disable ECC or how they should
> place the OOB bytes in the provided OOB buffer.
> 
> Add a field to nand_page_io_req to pass this information.
> 
> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
> ---

Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>

Re: [PATCH v7 1/5] mtd: nand: Pass mode information to nand_page_io_req

[Frieder Schrempf]

Hi Boris,

On 15.05.2018 17:08, Boris Brezillon wrote:
> The NAND sub-layers are likely to need the MTD_OPS_XXX mode information
> in order to decide if they should enable/disable ECC or how they should
> place the OOB bytes in the provided OOB buffer.
> 
> Add a field to nand_page_io_req to pass this information.
> 
> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
> ---

Tested-by: Frieder Schrempf <frieder.schrempf@exceet.de>
Reviewed-by: Frieder Schrempf <frieder.schrempf@exceet.de>

Re: [PATCH v7 2/5] mtd: nand: Add core infrastructure to support SPI NANDs

[Frieder Schrempf]

Hi Boris,

On 29.05.2018 16:59, Frieder Schrempf wrote:
> Hi Boris,
> 
> On 29.05.2018 15:35, Boris Brezillon wrote:
>> On Tue, 29 May 2018 12:57:33 +0200
>> Frieder Schrempf <frieder.schrempf@exceet.de> wrote:
>>
>>>> +static int spinand_init(struct spinand_device *spinand)
>>>> +{
>>>> +    struct device *dev = &spinand->spimem->spi->dev;
>>>> +    struct mtd_info *mtd = spinand_to_mtd(spinand);
>>>> +    struct nand_device *nand = mtd_to_nanddev(mtd);
>>>> +    int ret, i;
>>>> +
>>>> +    /*
>>>> +     * We need a scratch buffer because the spi_mem interface 
>>>> requires that
>>>> +     * buf passed in spi_mem_op->data.buf be DMA-able.
>>>> +     */
>>>> +    spinand->scratchbuf = kzalloc(SPINAND_MAX_ID_LEN, GFP_KERNEL);
>>>> +    if (!spinand->scratchbuf)
>>>> +        return -ENOMEM;
>>>> +
>>>> +    ret = spinand_detect(spinand);
>>>> +    if (ret)
>>>> +        goto err_free_bufs;
>>>> +
>>>> +    /*
>>>> +     * Use kzalloc() instead of devm_kzalloc() here, because some 
>>>> drivers
>>>> +     * may use this buffer for DMA access.
>>>> +     * Memory allocated by devm_ does not guarantee DMA-safe 
>>>> alignment.
>>>> +     */
>>>> +    spinand->databuf = kzalloc(nanddev_page_size(nand) +
>>>> +                   nanddev_per_page_oobsize(nand),
>>>> +                   GFP_KERNEL);
>>>> +    if (!spinand->databuf)
>>>> +        goto err_free_bufs;
>>>> +
>>>> +    spinand->oobbuf = spinand->databuf + nanddev_page_size(nand);
>>>> +
>>>> +    ret = spinand_init_cfg_cache(spinand);
>>>
>>> If the SPINAND_HAS_QE_BIT bit is set, then spinand_init_quad_enable()
>>> will try to use the config cache, but it hasn't been initialized at that
>>> time.
>>
>> Oops, you're right. I wonder how I could miss that one when testing it.
>> I guess you get a NULL pointer exception, right?
> 
> Yes.
> 
>>
>>>
>>> So spinand_init_cfg_cache() should probably be called earlier, before
>>> spinand_detect().
>>
>> I'd prefer to move the spinand_init_quad_enable() just after the
>> spinand_init_cfg_cache() one. Calling spinand_init_cfg_cache() does not
>> work because we don't know how many dies we have and the cfg cache has
>> one entry per die.
> 
> Yes true, so moving spinand_init_quad_enable() seems the way to go.

Except for this bug, my tests with Winbond W25M02GV and with Toshiba 
TC58CVG2S0H were successful.

Regards,

Frieder

Re: [PATCH v7 1/5] mtd: nand: Pass mode information to nand_page_io_req

[Boris Brezillon]

On Tue, 15 May 2018 17:08:21 +0200
Boris Brezillon <boris.brezillon@bootlin.com> wrote:

> The NAND sub-layers are likely to need the MTD_OPS_XXX mode information
> in order to decide if they should enable/disable ECC or how they should
> place the OOB bytes in the provided OOB buffer.
> 
> Add a field to nand_page_io_req to pass this information.
> 
> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>

Applied this one to nand/next. Will send a v8 fixing the issues
in other patches.

> ---
>  include/linux/mtd/nand.h | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
> index 792ea5c26329..abe975c87b90 100644
> --- a/include/linux/mtd/nand.h
> +++ b/include/linux/mtd/nand.h
> @@ -86,6 +86,7 @@ struct nand_pos {
>   * @ooboffs: the OOB offset within the page
>   * @ooblen: the number of OOB bytes to read from/write to this page
>   * @oobbuf: buffer to store OOB data in or get OOB data from
> + * @mode: one of the %MTD_OPS_XXX mode
>   *
>   * This object is used to pass per-page I/O requests to NAND sub-layers. This
>   * way all useful information are already formatted in a useful way and
> @@ -106,6 +107,7 @@ struct nand_page_io_req {
>  		const void *out;
>  		void *in;
>  	} oobbuf;
> +	int mode;
>  };
>  
>  /**
> @@ -599,6 +601,7 @@ static inline void nanddev_io_iter_init(struct nand_device *nand,
>  {
>  	struct mtd_info *mtd = nanddev_to_mtd(nand);
>  
> +	iter->req.mode = req->mode;
>  	iter->req.dataoffs = nanddev_offs_to_pos(nand, offs, &iter->req.pos);
>  	iter->req.ooboffs = req->ooboffs;
>  	iter->oobbytes_per_page = mtd_oobavail(mtd, req);