[PATCH 1/6] drm/i915/gtt: Avoid calling non-existent allocate_va_range

[PATCH 1/6] drm/i915/gtt: Avoid calling non-existent allocate_va_range

[Chris Wilson]

On hsw and older, we do not need to allocate the ppgtt on the fly and so
ppgtt->allocate_va_range() is NULL. Fixup ppgtt_bind_vma not to call it,
in that case!

v2: PIN_UPDATE still exists.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 34 ++++++++++++++++++-----------
 1 file changed, 21 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 7f4def556f40..344b572d0721 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -190,19 +190,11 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
 	return 1;
 }
 
-static int ppgtt_bind_vma(struct i915_vma *vma,
-			  enum i915_cache_level cache_level,
-			  u32 unused)
+static int gen6_ppgtt_bind_vma(struct i915_vma *vma,
+			       enum i915_cache_level cache_level,
+			       u32 unused)
 {
 	u32 pte_flags;
-	int ret;
-
-	if (!(vma->flags & I915_VMA_LOCAL_BIND)) {
-		ret = vma->vm->allocate_va_range(vma->vm, vma->node.start,
-						 vma->size);
-		if (ret)
-			return ret;
-	}
 
 	/* Currently applicable only to VLV */
 	pte_flags = 0;
@@ -214,6 +206,22 @@ static int ppgtt_bind_vma(struct i915_vma *vma,
 	return 0;
 }
 
+static int gen8_ppgtt_bind_vma(struct i915_vma *vma,
+			       enum i915_cache_level cache_level,
+			       u32 unused)
+{
+	int ret;
+
+	if (!(vma->flags & I915_VMA_LOCAL_BIND)) {
+		ret = vma->vm->allocate_va_range(vma->vm,
+						 vma->node.start, vma->size);
+		if (ret)
+			return ret;
+	}
+
+	return gen6_ppgtt_bind_vma(vma, cache_level, unused);
+}
+
 static void ppgtt_unbind_vma(struct i915_vma *vma)
 {
 	vma->vm->clear_range(vma->vm, vma->node.start, vma->size);
@@ -1657,8 +1665,8 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
 		gen8_ppgtt_notify_vgt(ppgtt, true);
 
 	ppgtt->base.cleanup = gen8_ppgtt_cleanup;
+	ppgtt->base.bind_vma = gen8_ppgtt_bind_vma;
 	ppgtt->base.unbind_vma = ppgtt_unbind_vma;
-	ppgtt->base.bind_vma = ppgtt_bind_vma;
 	ppgtt->base.set_pages = ppgtt_set_pages;
 	ppgtt->base.clear_pages = clear_pages;
 	ppgtt->debug_dump = gen8_dump_ppgtt;
@@ -2100,8 +2108,8 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
 
 	ppgtt->base.clear_range = gen6_ppgtt_clear_range;
 	ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
+	ppgtt->base.bind_vma = gen6_ppgtt_bind_vma;
 	ppgtt->base.unbind_vma = ppgtt_unbind_vma;
-	ppgtt->base.bind_vma = ppgtt_bind_vma;
 	ppgtt->base.set_pages = ppgtt_set_pages;
 	ppgtt->base.clear_pages = clear_pages;
 	ppgtt->base.cleanup = gen6_ppgtt_cleanup;
-- 
2.17.1

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[PATCH 2/6] drm/i915/gtt: Don't restore the non-existent PDE for GGTT

[Chris Wilson]

On resume, we have to rewrite all the PDE entries for gen7 ppgtts. If we
switch on full-ppgtt, there is then one address space with no PDE, the
GGTT. Currently under aliasing-ppgtt, the GGTT address space does have
an associated ppgtt and so the restore works just fine. We would have a
similar problem if we tried disabling aliasing-ppgtt
(i915.enable_ppgtt=0). So skip the empty ppgtt, as being non-existent it
doesn't need restoring.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 344b572d0721..992efe1881c8 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3665,6 +3665,8 @@ void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv)
 				ppgtt = dev_priv->mm.aliasing_ppgtt;
 			else
 				ppgtt = i915_vm_to_ppgtt(vm);
+			if (!ppgtt)
+				continue;
 
 			gen6_write_page_range(ppgtt, 0, ppgtt->base.total);
 		}
-- 
2.17.1

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Re: [PATCH 2/6] drm/i915/gtt: Don't restore the non-existent PDE for GGTT

[Joonas Lahtinen]

On Fri, 2018-06-01 at 10:35 +0100, Chris Wilson wrote:
> On resume, we have to rewrite all the PDE entries for gen7 ppgtts. If we
> switch on full-ppgtt, there is then one address space with no PDE, the
> GGTT. Currently under aliasing-ppgtt, the GGTT address space does have
> an associated ppgtt and so the restore works just fine. We would have a
> similar problem if we tried disabling aliasing-ppgtt
> (i915.enable_ppgtt=0). So skip the empty ppgtt, as being non-existent it
> doesn't need restoring.
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>

Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>

Regards, Joonas
-- 
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Open Source Technology Center
Intel Corporation
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Re: [PATCH 2/6] drm/i915/gtt: Don't restore the non-existent PDE for GGTT

[Chris Wilson]

Quoting Joonas Lahtinen (2018-06-01 13:56:56)
> On Fri, 2018-06-01 at 10:35 +0100, Chris Wilson wrote:
> > On resume, we have to rewrite all the PDE entries for gen7 ppgtts. If we
> > switch on full-ppgtt, there is then one address space with no PDE, the
> > GGTT. Currently under aliasing-ppgtt, the GGTT address space does have
> > an associated ppgtt and so the restore works just fine. We would have a
> > similar problem if we tried disabling aliasing-ppgtt
> > (i915.enable_ppgtt=0). So skip the empty ppgtt, as being non-existent it
> > doesn't need restoring.
> > 
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> 
> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>

Pushed the first pair as simple standalone NULL pointer fixes. Thanks
for the review,
-Chris
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[PATCH 3/6] drm/i915: Flush all writes before suspend

[Chris Wilson]

As we have already suspended the device, this should be a no-op except
for marking that all writes are indeed complete. The downside is that
we then have to walk all the lists of objects for what should be a no-op
(in some cases they will be mmio read to ensure the GGTT writes are
indeed flushed, and clflushes to ensure that cpu writes are in memory).

It seems prudent and the safer course for us to ensure all writes are
flushed to memory before suspend.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/i915_gem.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index f5c4ef052001..d91fb25a8a1f 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5066,6 +5066,13 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv)
 
 void i915_gem_suspend_late(struct drm_i915_private *i915)
 {
+	struct drm_i915_gem_object *obj;
+	struct list_head *phases[] = {
+		&i915->mm.unbound_list,
+		&i915->mm.bound_list,
+		NULL
+	}, **p;
+
 	/*
 	 * Neither the BIOS, ourselves or any other kernel
 	 * expects the system to be in execlists mode on startup,
@@ -5086,6 +5093,13 @@ void i915_gem_suspend_late(struct drm_i915_private *i915)
 	 * machine in an unusable condition.
 	 */
 
+	mutex_lock(&i915->drm.struct_mutex);
+	for (p = phases; *p; p++) {
+		list_for_each_entry(obj, *p, mm.link)
+			WARN_ON(i915_gem_object_set_to_gtt_domain(obj, false));
+	}
+	mutex_unlock(&i915->drm.struct_mutex);
+
 	intel_uc_sanitize(i915);
 	i915_gem_sanitize(i915);
 }
-- 
2.17.1

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Re: [PATCH 3/6] drm/i915: Flush all writes before suspend

[Joonas Lahtinen]

On Fri, 2018-06-01 at 10:35 +0100, Chris Wilson wrote:
> As we have already suspended the device, this should be a no-op except
> for marking that all writes are indeed complete. The downside is that
> we then have to walk all the lists of objects for what should be a no-op
> (in some cases they will be mmio read to ensure the GGTT writes are
> indeed flushed, and clflushes to ensure that cpu writes are in memory).
> 
> It seems prudent and the safer course for us to ensure all writes are
> flushed to memory before suspend.
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Mika Kuoppala <mika.kuoppala@intel.com>

<SNIP>

> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -5066,6 +5066,13 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv)
>  
>  void i915_gem_suspend_late(struct drm_i915_private *i915)
>  {
> +	struct drm_i915_gem_object *obj;
> +	struct list_head *phases[] = {
> +		&i915->mm.unbound_list,
> +		&i915->mm.bound_list,
> +		NULL
> +	}, **p;

I guess the p variable could be on a separate line, and maybe even
"phase".

> +
>  	/*
>  	 * Neither the BIOS, ourselves or any other kernel
>  	 * expects the system to be in execlists mode on startup,
> @@ -5086,6 +5093,13 @@ void i915_gem_suspend_late(struct drm_i915_private *i915)
>  	 * machine in an unusable condition.
>  	 */
>  
> +	mutex_lock(&i915->drm.struct_mutex);
> +	for (p = phases; *p; p++) {
> +		list_for_each_entry(obj, *p, mm.link)
> +			WARN_ON(i915_gem_object_set_to_gtt_domain(obj, false));
> +	}
> +	mutex_unlock(&i915->drm.struct_mutex);

Braces not exactly needed.

Reviewed-by: joonas Lahtinen <joonas.lahtinen@linux.intel.com>

Regards, Joonas
-- 
Joonas Lahtinen
Open Source Graphics Center
Intel Corporation
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[PATCH 4/6] drm/i915: Apply the full CPU domain markup before freezing

[Chris Wilson]

Let's not take any chances by using a shortcut to mark the objects as in
the CPU domain upon freezing (all pages will be written to disk and so
on restore all objects will start from the CPU domain). Currently, we
simply mark the objects as being in the CPU domain, bypassing the
flushes. Let's call the full domain transfer function so that we have
less special case code (and symmetry with the suspend path) even though
it will be mostly redundant.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/i915_gem.c | 19 ++++++++++---------
 1 file changed, 10 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index d91fb25a8a1f..ea69b4b26e32 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5713,16 +5713,17 @@ int i915_gem_freeze(struct drm_i915_private *dev_priv)
 	return 0;
 }
 
-int i915_gem_freeze_late(struct drm_i915_private *dev_priv)
+int i915_gem_freeze_late(struct drm_i915_private *i915)
 {
 	struct drm_i915_gem_object *obj;
 	struct list_head *phases[] = {
-		&dev_priv->mm.unbound_list,
-		&dev_priv->mm.bound_list,
+		&i915->mm.unbound_list,
+		&i915->mm.bound_list,
 		NULL
 	}, **p;
 
-	/* Called just before we write the hibernation image.
+	/*
+	 * Called just before we write the hibernation image.
 	 *
 	 * We need to update the domain tracking to reflect that the CPU
 	 * will be accessing all the pages to create and restore from the
@@ -5736,15 +5737,15 @@ int i915_gem_freeze_late(struct drm_i915_private *dev_priv)
 	 * the objects as well, see i915_gem_freeze()
 	 */
 
-	i915_gem_shrink(dev_priv, -1UL, NULL, I915_SHRINK_UNBOUND);
-	i915_gem_drain_freed_objects(dev_priv);
+	i915_gem_shrink(i915, -1UL, NULL, I915_SHRINK_UNBOUND);
+	i915_gem_drain_freed_objects(i915);
 
-	spin_lock(&dev_priv->mm.obj_lock);
+	mutex_lock(&i915->drm.struct_mutex);
 	for (p = phases; *p; p++) {
 		list_for_each_entry(obj, *p, mm.link)
-			__start_cpu_write(obj);
+			WARN_ON(i915_gem_object_set_to_cpu_domain(obj, true));
 	}
-	spin_unlock(&dev_priv->mm.obj_lock);
+	mutex_unlock(&i915->drm.struct_mutex);
 
 	return 0;
 }
-- 
2.17.1

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Re: [PATCH 4/6] drm/i915: Apply the full CPU domain markup before freezing

[Joonas Lahtinen]

On Fri, 2018-06-01 at 10:35 +0100, Chris Wilson wrote:
> Let's not take any chances by using a shortcut to mark the objects as in
> the CPU domain upon freezing (all pages will be written to disk and so
> on restore all objects will start from the CPU domain). Currently, we
> simply mark the objects as being in the CPU domain, bypassing the
> flushes. Let's call the full domain transfer function so that we have
> less special case code (and symmetry with the suspend path) even though
> it will be mostly redundant.
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Mika Kuoppala <mika.kuoppala@intel.com>

Right, so the naming sees to be symmetry to this function... I'm
assuming this has no performance impact, so:

Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>

Regards, Joonas
-- 
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Open Source Graphics Center
Intel Corporation
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[PATCH 5/6] drm/i915/gtt: Enable full-ppgtt by default for HSW

[Chris Wilson]

Let's see if we have all the kinks worked out and full-ppgtt now works
reliably on Haswell. If we can let userspace have full control over
their own ppgtt, it makes softpinning far more effective, in turn making
GPU dispatch far more efficient and more secure (due to better mm
segregation).

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 992efe1881c8..371f509736b1 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -179,7 +179,7 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
 		return 0;
 	}
 
-	if (HAS_LOGICAL_RING_CONTEXTS(dev_priv)) {
+	if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) || IS_HASWELL(dev_priv)) {
 		if (has_full_48bit_ppgtt)
 			return 3;
 
-- 
2.17.1

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[PATCH 6/6] drm/i915/gtt: Enable full-ppgtt by default everywhere!

[Chris Wilson]

Let's see if we have all the kinks worked out and full-ppgtt now works
reliably on gen7. If we can let userspace have full control over
their own ppgtt, it makes softpinning far more effective, in turn making
GPU dispatch far more efficient and more secure (due to better mm
segregation).

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 371f509736b1..88b3dbdc5799 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -179,13 +179,11 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
 		return 0;
 	}
 
-	if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) || IS_HASWELL(dev_priv)) {
-		if (has_full_48bit_ppgtt)
-			return 3;
+	if (has_full_48bit_ppgtt)
+		return 3;
 
-		if (has_full_ppgtt)
-			return 2;
-	}
+	if (has_full_ppgtt)
+		return 2;
 
 	return 1;
 }
-- 
2.17.1

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✗ Fi.CI.BAT: failure for series starting with [1/6] drm/i915/gtt: Avoid calling non-existent allocate_va_range

[Patchwork]

== Series Details ==

Series: series starting with [1/6] drm/i915/gtt: Avoid calling non-existent allocate_va_range
URL   : https://patchwork.freedesktop.org/series/44076/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4269 -> Patchwork_9167 =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_9167 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9167, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/44076/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_9167:

  === IGT changes ===

    ==== Possible regressions ====

    igt@debugfs_test@read_all_entries:
      fi-bdw-gvtdvm:      PASS -> DMESG-WARN +2

    igt@gem_ctx_create@basic-files:
      fi-byt-n2820:       PASS -> DMESG-FAIL
      fi-ivb-3520m:       PASS -> DMESG-FAIL
      fi-hsw-4770:        PASS -> FAIL +1
      fi-ivb-3770:        PASS -> FAIL
      fi-hsw-peppy:       PASS -> FAIL
      fi-hsw-4770r:       PASS -> FAIL +1
      fi-byt-j1900:       PASS -> FAIL
      fi-hsw-4200u:       PASS -> FAIL

    
== Known issues ==

  Here are the changes found in Patchwork_9167 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@drv_module_reload@basic-no-display:
      fi-elk-e7500:       PASS -> INCOMPLETE (fdo#103989)

    igt@gem_exec_nop@basic-parallel:
      fi-glk-j4005:       PASS -> DMESG-WARN (fdo#106000)

    igt@gem_exec_suspend@basic-s3:
      fi-bdw-gvtdvm:      PASS -> INCOMPLETE (fdo#105600)
      fi-skl-gvtdvm:      PASS -> INCOMPLETE (fdo#104108, fdo#105600)

    igt@gem_mmap_gtt@basic-small-bo-tiledx:
      fi-gdg-551:         PASS -> FAIL (fdo#102575)

    igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c-frame-sequence:
      fi-cfl-guc:         PASS -> FAIL (fdo#103481)

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
      fi-bxt-dsi:         PASS -> INCOMPLETE (fdo#103927)

    igt@prime_vgem@basic-fence-wait-default:
      fi-glk-j4005:       PASS -> DMESG-WARN (fdo#105719)

    
    ==== Possible fixes ====

    igt@drv_module_reload@basic-reload-inject:
      fi-glk-j4005:       DMESG-WARN (fdo#106725, fdo#106248) -> PASS

    igt@gem_exec_suspend@basic-s3:
      fi-skl-6700k2:      INCOMPLETE (fdo#104108, fdo#105524, k.org#199541) -> PASS

    igt@kms_busy@basic-flip-c:
      fi-glk-j4005:       FAIL (fdo#103182) -> PASS

    igt@kms_flip@basic-flip-vs-modeset:
      fi-glk-j4005:       DMESG-WARN (fdo#106097, fdo#106000) -> PASS

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
      fi-kbl-7567u:       FAIL (fdo#104724, fdo#103191) -> PASS

    
  fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
  fdo#103182 https://bugs.freedesktop.org/show_bug.cgi?id=103182
  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#103481 https://bugs.freedesktop.org/show_bug.cgi?id=103481
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
  fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
  fdo#105524 https://bugs.freedesktop.org/show_bug.cgi?id=105524
  fdo#105600 https://bugs.freedesktop.org/show_bug.cgi?id=105600
  fdo#105719 https://bugs.freedesktop.org/show_bug.cgi?id=105719
  fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000
  fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097
  fdo#106248 https://bugs.freedesktop.org/show_bug.cgi?id=106248
  fdo#106725 https://bugs.freedesktop.org/show_bug.cgi?id=106725
  k.org#199541 https://bugzilla.kernel.org/show_bug.cgi?id=199541


== Participating hosts (43 -> 40) ==

  Missing    (3): fi-ctg-p8600 fi-ilk-m540 fi-skl-6700hq 


== Build changes ==

    * Linux: CI_DRM_4269 -> Patchwork_9167

  CI_DRM_4269: 25dda01a94cbf70d599be9b0f74c61f310858fa3 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4503: ae0ea2a0cff1cf8516d18ada5b9db01c56b73ed9 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9167: 19b35ba0aad22e050de9b0972be4a4908ab31234 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

19b35ba0aad2 drm/i915/gtt: Enable full-ppgtt by default everywhere!
c67813caf64a drm/i915/gtt: Enable full-ppgtt by default for HSW
bc4cae2a312a drm/i915: Apply the full CPU domain markup before freezing
b948fc7be086 drm/i915: Flush all writes before suspend
7a319dcbc8e7 drm/i915/gtt: Don't restore the non-existent PDE for GGTT
3c8d71ace4a3 drm/i915/gtt: Avoid calling non-existent allocate_va_range

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9167/issues.html
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✗ Fi.CI.IGT: failure for series starting with [1/6] drm/i915/gtt: Avoid calling non-existent allocate_va_range

[Patchwork]

== Series Details ==

Series: series starting with [1/6] drm/i915/gtt: Avoid calling non-existent allocate_va_range
URL   : https://patchwork.freedesktop.org/series/44076/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4269_full -> Patchwork_9167_full =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_9167_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9167_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/44076/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_9167_full:

  === IGT changes ===

    ==== Possible regressions ====

    igt@gem_exec_parallel@default-fds:
      shard-hsw:          PASS -> FAIL +13

    
    ==== Warnings ====

    igt@gem_ppgtt@flink-and-close-vma-leak:
      shard-hsw:          SKIP -> PASS +2

    igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-xtiled:
      shard-snb:          PASS -> SKIP

    
== Known issues ==

  Here are the changes found in Patchwork_9167_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@drv_selftest@live_evict:
      shard-hsw:          PASS -> INCOMPLETE (fdo#103540) +3

    igt@drv_selftest@live_hangcheck:
      shard-kbl:          PASS -> DMESG-FAIL (fdo#106560)
      shard-apl:          PASS -> DMESG-FAIL (fdo#106560)

    igt@gem_eio@suspend:
      shard-snb:          PASS -> INCOMPLETE (fdo#105411)

    igt@kms_atomic_transition@1x-modeset-transitions-nonblocking:
      shard-glk:          PASS -> FAIL (fdo#105703)

    igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
      shard-glk:          PASS -> FAIL (fdo#100368)

    igt@kms_plane@plane-panning-bottom-right-pipe-c-planes:
      shard-apl:          PASS -> DMESG-WARN (fdo#106247)

    
    ==== Possible fixes ====

    igt@drv_selftest@live_gtt:
      shard-glk:          FAIL (fdo#105347) -> PASS

    igt@gem_eio@hibernate:
      shard-snb:          INCOMPLETE (fdo#105411) -> PASS

    igt@kms_cursor_legacy@flip-vs-cursor-legacy:
      shard-hsw:          FAIL (fdo#102670) -> PASS

    igt@kms_flip@2x-modeset-vs-vblank-race-interruptible:
      shard-hsw:          FAIL (fdo#103060) -> PASS

    igt@kms_flip_tiling@flip-y-tiled:
      shard-glk:          FAIL (fdo#103822, fdo#104724) -> PASS

    
  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102670 https://bugs.freedesktop.org/show_bug.cgi?id=102670
  fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
  fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
  fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
  fdo#105347 https://bugs.freedesktop.org/show_bug.cgi?id=105347
  fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411
  fdo#105703 https://bugs.freedesktop.org/show_bug.cgi?id=105703
  fdo#106247 https://bugs.freedesktop.org/show_bug.cgi?id=106247
  fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560


== Participating hosts (5 -> 5) ==

  No changes in participating hosts


== Build changes ==

    * Linux: CI_DRM_4269 -> Patchwork_9167

  CI_DRM_4269: 25dda01a94cbf70d599be9b0f74c61f310858fa3 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4503: ae0ea2a0cff1cf8516d18ada5b9db01c56b73ed9 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9167: 19b35ba0aad22e050de9b0972be4a4908ab31234 @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9167/shards.html
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Intel-gfx@lists.freedesktop.org
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