* [PATCH v2 1/2] drm/i915/icl: Add remaining registers and bitfields for MG PHY DDI
@ 2018-06-28 22:35 Manasi Navare
2018-06-28 22:35 ` [PATCH v2 2/2] drm/i915/icl: Implement voltage swing programming sequence " Manasi Navare
` (10 more replies)
0 siblings, 11 replies; 15+ messages in thread
From: Manasi Navare @ 2018-06-28 22:35 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
This patch adds the remaining register definitions and bit fields
required for MG PHy DDI buffer initializations and voltage
swing programming for MG PHy DDI ports.
While at it this patch also fixes the naming for previously defined
MG PHY registers in original commit id (c92f47b5ec977a "drm/i915/icl:
Add register defs for voltage swing sequences for MG PHY DDI").
Since the MG PHY registers are first defined in ICL platform, there
is no need for _ICL prefix.
v2:
* Change the MG_TX_DRVCTL registers names to match the spec (Anusha)
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 246 +++++++++++++++++++++++-----------------
1 file changed, 145 insertions(+), 101 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c30cfcd..6119acc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1872,121 +1872,165 @@ enum i915_power_well_id {
#define N_SCALAR(x) ((x) << 24)
#define N_SCALAR_MASK (0x7F << 24)
-#define _ICL_MG_PHY_PORT_LN(port, ln, ln0p1, ln0p2, ln1p1) \
+#define MG_PHY_PORT_LN(port, ln, ln0p1, ln0p2, ln1p1) \
_MMIO(_PORT((port) - PORT_C, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
-#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT1 0x16812C
-#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT1 0x16852C
-#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT2 0x16912C
-#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT2 0x16952C
-#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT3 0x16A12C
-#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT3 0x16A52C
-#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT4 0x16B12C
-#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT4 0x16B52C
-#define ICL_PORT_MG_TX1_LINK_PARAMS(port, ln) \
- _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
- _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
- _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT1)
-
-#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT1 0x1680AC
-#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT1 0x1684AC
-#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT2 0x1690AC
-#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT2 0x1694AC
-#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT3 0x16A0AC
-#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT3 0x16A4AC
-#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT4 0x16B0AC
-#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT4 0x16B4AC
-#define ICL_PORT_MG_TX2_LINK_PARAMS(port, ln) \
- _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
- _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
- _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT1)
+#define MG_TX_LINK_PARAMS_TX1LN0_PORT1 0x16812C
+#define MG_TX_LINK_PARAMS_TX1LN1_PORT1 0x16852C
+#define MG_TX_LINK_PARAMS_TX1LN0_PORT2 0x16912C
+#define MG_TX_LINK_PARAMS_TX1LN1_PORT2 0x16952C
+#define MG_TX_LINK_PARAMS_TX1LN0_PORT3 0x16A12C
+#define MG_TX_LINK_PARAMS_TX1LN1_PORT3 0x16A52C
+#define MG_TX_LINK_PARAMS_TX1LN0_PORT4 0x16B12C
+#define _MG_TX_LINK_PARAMS_TX1LN1_PORT4 0x16B52C
+#define MG_TX1_LINK_PARAMS(port, ln) \
+ MG_PHY_PORT_LN(port, ln, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
+ MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
+ MG_TX_LINK_PARAMS_TX1LN1_PORT1)
+
+#define MG_TX_LINK_PARAMS_TX2LN0_PORT1 0x1680AC
+#define MG_TX_LINK_PARAMS_TX2LN1_PORT1 0x1684AC
+#define MG_TX_LINK_PARAMS_TX2LN0_PORT2 0x1690AC
+#define MG_TX_LINK_PARAMS_TX2LN1_PORT2 0x1694AC
+#define MG_TX_LINK_PARAMS_TX2LN0_PORT3 0x16A0AC
+#define MG_TX_LINK_PARAMS_TX2LN1_PORT3 0x16A4AC
+#define MG_TX_LINK_PARAMS_TX2LN0_PORT4 0x16B0AC
+#define MG_TX_LINK_PARAMS_TX2LN1_PORT4 0x16B4AC
+#define MG_TX2_LINK_PARAMS(port, ln) \
+ MG_PHY_PORT_LN(port, ln, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
+ MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
+ MG_TX_LINK_PARAMS_TX2LN1_PORT1)
#define CRI_USE_FS32 (1 << 5)
-#define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT1 0x16814C
-#define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT1 0x16854C
-#define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT2 0x16914C
-#define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT2 0x16954C
-#define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT3 0x16A14C
-#define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT3 0x16A54C
-#define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT4 0x16B14C
-#define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT4 0x16B54C
-#define ICL_PORT_MG_TX1_PISO_READLOAD(port, ln) \
- _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
- _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT2, \
- _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT1)
-
-#define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT1 0x1680CC
-#define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT1 0x1684CC
-#define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT2 0x1690CC
-#define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT2 0x1694CC
-#define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT3 0x16A0CC
-#define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT3 0x16A4CC
-#define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT4 0x16B0CC
-#define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT4 0x16B4CC
-#define ICL_PORT_MG_TX2_PISO_READLOAD(port, ln) \
- _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
- _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT2, \
- _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT1)
+#define MG_TX_PISO_READLOAD_TX1LN0_PORT1 0x16814C
+#define MG_TX_PISO_READLOAD_TX1LN1_PORT1 0x16854C
+#define MG_TX_PISO_READLOAD_TX1LN0_PORT2 0x16914C
+#define MG_TX_PISO_READLOAD_TX1LN1_PORT2 0x16954C
+#define MG_TX_PISO_READLOAD_TX1LN0_PORT3 0x16A14C
+#define MG_TX_PISO_READLOAD_TX1LN1_PORT3 0x16A54C
+#define MG_TX_PISO_READLOAD_TX1LN0_PORT4 0x16B14C
+#define MG_TX_PISO_READLOAD_TX1LN1_PORT4 0x16B54C
+#define MG_TX1_PISO_READLOAD(port, ln) \
+ MG_PHY_PORT_LN(port, ln, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
+ MG_TX_PISO_READLOAD_TX1LN0_PORT2, \
+ MG_TX_PISO_READLOAD_TX1LN1_PORT1)
+
+#define MG_TX_PISO_READLOAD_TX2LN0_PORT1 0x1680CC
+#define MG_TX_PISO_READLOAD_TX2LN1_PORT1 0x1684CC
+#define MG_TX_PISO_READLOAD_TX2LN0_PORT2 0x1690CC
+#define MG_TX_PISO_READLOAD_TX2LN1_PORT2 0x1694CC
+#define MG_TX_PISO_READLOAD_TX2LN0_PORT3 0x16A0CC
+#define MG_TX_PISO_READLOAD_TX2LN1_PORT3 0x16A4CC
+#define MG_TX_PISO_READLOAD_TX2LN0_PORT4 0x16B0CC
+#define MG_TX_PISO_READLOAD_TX2LN1_PORT4 0x16B4CC
+#define MG_TX2_PISO_READLOAD(port, ln) \
+ MG_PHY_PORT_LN(port, ln, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
+ MG_TX_PISO_READLOAD_TX2LN0_PORT2, \
+ MG_TX_PISO_READLOAD_TX2LN1_PORT1)
#define CRI_CALCINIT (1 << 1)
-#define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT1 0x168148
-#define _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT1 0x168548
-#define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT2 0x169148
-#define _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT2 0x169548
-#define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT3 0x16A148
-#define _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT3 0x16A548
-#define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT4 0x16B148
-#define _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT4 0x16B548
-#define ICL_PORT_MG_TX1_SWINGCTRL(port, ln) \
- _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT1, \
- _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT2, \
- _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT1)
-
-#define _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT1 0x1680C8
-#define _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT1 0x1684C8
-#define _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT2 0x1690C8
-#define _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT2 0x1694C8
-#define _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT3 0x16A0C8
-#define _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT3 0x16A4C8
-#define _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT4 0x16B0C8
-#define _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT4 0x16B4C8
-#define ICL_PORT_MG_TX2_SWINGCTRL(port, ln) \
- _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT1, \
- _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT2, \
- _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT1)
+#define MG_TX_SWINGCTRL_TX1LN0_PORT1 0x168148
+#define MG_TX_SWINGCTRL_TX1LN1_PORT1 0x168548
+#define MG_TX_SWINGCTRL_TX1LN0_PORT2 0x169148
+#define MG_TX_SWINGCTRL_TX1LN1_PORT2 0x169548
+#define MG_TX_SWINGCTRL_TX1LN0_PORT3 0x16A148
+#define MG_TX_SWINGCTRL_TX1LN1_PORT3 0x16A548
+#define MG_TX_SWINGCTRL_TX1LN0_PORT4 0x16B148
+#define MG_TX_SWINGCTRL_TX1LN1_PORT4 0x16B548
+#define MG_TX1_SWINGCTRL(port, ln) \
+ MG_PHY_PORT_LN(port, ln, MG_TX_SWINGCTRL_TX1LN0_PORT1, \
+ MG_TX_SWINGCTRL_TX1LN0_PORT2, \
+ MG_TX_SWINGCTRL_TX1LN1_PORT1)
+
+#define MG_TX_SWINGCTRL_TX2LN0_PORT1 0x1680C8
+#define MG_TX_SWINGCTRL_TX2LN1_PORT1 0x1684C8
+#define MG_TX_SWINGCTRL_TX2LN0_PORT2 0x1690C8
+#define MG_TX_SWINGCTRL_TX2LN1_PORT2 0x1694C8
+#define MG_TX_SWINGCTRL_TX2LN0_PORT3 0x16A0C8
+#define MG_TX_SWINGCTRL_TX2LN1_PORT3 0x16A4C8
+#define MG_TX_SWINGCTRL_TX2LN0_PORT4 0x16B0C8
+#define MG_TX_SWINGCTRL_TX2LN1_PORT4 0x16B4C8
+#define MG_TX2_SWINGCTRL(port, ln) \
+ MG_PHY_PORT_LN(port, ln, MG_TX_SWINGCTRL_TX2LN0_PORT1, \
+ MG_TX_SWINGCTRL_TX2LN0_PORT2, \
+ MG_TX_SWINGCTRL_TX2LN1_PORT1)
#define CRI_TXDEEMPH_OVERRIDE_17_12(x) ((x) << 0)
#define CRI_TXDEEMPH_OVERRIDE_17_12_MASK (0x3F << 0)
-#define _ICL_MG_TX_DRVCTRL_TX1LN0_PORT1 0x168144
-#define _ICL_MG_TX_DRVCTRL_TX1LN1_PORT1 0x168544
-#define _ICL_MG_TX_DRVCTRL_TX1LN0_PORT2 0x169144
-#define _ICL_MG_TX_DRVCTRL_TX1LN1_PORT2 0x169544
-#define _ICL_MG_TX_DRVCTRL_TX1LN0_PORT3 0x16A144
-#define _ICL_MG_TX_DRVCTRL_TX1LN1_PORT3 0x16A544
-#define _ICL_MG_TX_DRVCTRL_TX1LN0_PORT4 0x16B144
-#define _ICL_MG_TX_DRVCTRL_TX1LN1_PORT4 0x16B544
-#define ICL_PORT_MG_TX1_DRVCTRL(port, ln) \
- _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_DRVCTRL_TX1LN0_PORT1, \
- _ICL_MG_TX_DRVCTRL_TX1LN0_PORT2, \
- _ICL_MG_TX_DRVCTRL_TX1LN1_PORT1)
-
-#define _ICL_MG_TX_DRVCTRL_TX2LN0_PORT1 0x1680C4
-#define _ICL_MG_TX_DRVCTRL_TX2LN1_PORT1 0x1684C4
-#define _ICL_MG_TX_DRVCTRL_TX2LN0_PORT2 0x1690C4
-#define _ICL_MG_TX_DRVCTRL_TX2LN1_PORT2 0x1694C4
-#define _ICL_MG_TX_DRVCTRL_TX2LN0_PORT3 0x16A0C4
-#define _ICL_MG_TX_DRVCTRL_TX2LN1_PORT3 0x16A4C4
-#define _ICL_MG_TX_DRVCTRL_TX2LN0_PORT4 0x16B0C4
-#define _ICL_MG_TX_DRVCTRL_TX2LN1_PORT4 0x16B4C4
-#define ICL_PORT_MG_TX2_DRVCTRL(port, ln) \
- _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_DRVCTRL_TX2LN0_PORT1, \
- _ICL_MG_TX_DRVCTRL_TX2LN0_PORT2, \
- _ICL_MG_TX_DRVCTRL_TX2LN1_PORT1)
+#define MG_TX_DRVCTRL_TX1LN0_TXPORT1 0x168144
+#define MG_TX_DRVCTRL_TX1LN1_TXPORT1 0x168544
+#define MG_TX_DRVCTRL_TX1LN0_TXPORT2 0x169144
+#define MG_TX_DRVCTRL_TX1LN1_TXPORT2 0x169544
+#define MG_TX_DRVCTRL_TX1LN0_TXPORT3 0x16A144
+#define MG_TX_DRVCTRL_TX1LN1_TXPORT3 0x16A544
+#define MG_TX_DRVCTRL_TX1LN0_TXPORT4 0x16B144
+#define MG_TX_DRVCTRL_TX1LN1_TXPORT4 0x16B544
+#define MG_TX1_DRVCTRL(port, ln) \
+ MG_PHY_PORT_LN(port, ln, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \
+ MG_TX_DRVCTRL_TX1LN0_TXPORT2, \
+ MG_TX_DRVCTRL_TX1LN1_TXPORT1)
+
+#define MG_TX_DRVCTRL_TX2LN0_PORT1 0x1680C4
+#define MG_TX_DRVCTRL_TX2LN1_PORT1 0x1684C4
+#define MG_TX_DRVCTRL_TX2LN0_PORT2 0x1690C4
+#define MG_TX_DRVCTRL_TX2LN1_PORT2 0x1694C4
+#define MG_TX_DRVCTRL_TX2LN0_PORT3 0x16A0C4
+#define MG_TX_DRVCTRL_TX2LN1_PORT3 0x16A4C4
+#define MG_TX_DRVCTRL_TX2LN0_PORT4 0x16B0C4
+#define MG_TX_DRVCTRL_TX2LN1_PORT4 0x16B4C4
+#define MG_TX2_DRVCTRL(port, ln) \
+ MG_PHY_PORT_LN(port, ln, MG_TX_DRVCTRL_TX2LN0_PORT1, \
+ MG_TX_DRVCTRL_TX2LN0_PORT2, \
+ MG_TX_DRVCTRL_TX2LN1_PORT1)
#define CRI_TXDEEMPH_OVERRIDE_11_6(x) ((x) << 24)
#define CRI_TXDEEMPH_OVERRIDE_11_6_MASK (0x3F << 24)
#define CRI_TXDEEMPH_OVERRIDE_EN (1 << 22)
#define CRI_TXDEEMPH_OVERRIDE_5_0(x) ((x) << 16)
#define CRI_TXDEEMPH_OVERRIDE_5_0_MASK (0x3F << 16)
+#define CRI_LOADGEN_SEL(x) ((x) << 12)
+#define CRI_LOADGEN_SEL_MASK (0x3 << 12)
+
+#define MG_CLKHUB_LN0_PORT1 0x16839C
+#define MG_CLKHUB_LN1_PORT1 0x16879C
+#define MG_CLKHUB_LN0_PORT2 0x16939C
+#define MG_CLKHUB_LN1_PORT2 0x16979C
+#define MG_CLKHUB_LN0_PORT3 0x16A39C
+#define MG_CLKHUB_LN1_PORT3 0x16A79C
+#define MG_CLKHUB_LN0_PORT4 0x16B39C
+#define MG_CLKHUB_LN1_PORT4 0x16B79C
+#define MG_CLKHUB(port, ln) \
+ MG_PHY_PORT_LN(port, ln, MG_CLKHUB_LN0_PORT1, \
+ MG_CLKHUB_LN0_PORT2, \
+ MG_CLKHUB_LN1_PORT1)
+#define CFG_LOW_RATE_LKREN_EN (1 << 11)
+
+#define MG_TX_DCC_TX1LN0_PORT1 0x168110
+#define MG_TX_DCC_TX1LN1_PORT1 0x168510
+#define MG_TX_DCC_TX1LNO_PORT2 0x169110
+#define MG_TX_DCC_TX1LN1_PORT2 0x169510
+#define MG_TX_DCC_TX1LNO_PORT3 0x16A110
+#define MG_TX_DCC_TX1LN1_PORT3 0x16A510
+#define MG_TX_DCC_TX1LNO_PORT4 0x16B110
+#define MG_TX_DCC_TX1LN1_PORT4 0x16B510
+#define MG_TX1_DCC(port, ln) \
+ MG_PHY_PORT_LN(port, ln, MG_TX_DCC_TX1LN0_PORT1, \
+ MG_TX_DCC_TX1LNO_PORT2, \
+ MG_TX_DCC_TX1LN1_PORT1)
+#define MG_TX_DCC_TX2LN0_PORT1 0x168090
+#define MG_TX_DCC_TX2LN1_PORT1 0x168490
+#define MG_TX_DCC_TX2LNO_PORT2 0x169090
+#define MG_TX_DCC_TX2LN1_PORT2 0x169490
+#define MG_TX_DCC_TX2LNO_PORT3 0x16A090
+#define MG_TX_DCC_TX2LN1_PORT3 0x16A490
+#define MG_TX_DCC_TX2LNO_PORT4 0x16B090
+#define MG_TX_DCC_TX2LN1_PORT4 0x16B490
+#define MG_TX2_DCC(port, ln) \
+ MG_PHY_PORT_LN(port, ln, MG_TX_DCC_TX2LN0_PORT1, \
+ MG_TX_DCC_TX2LNO_PORT2, \
+ MG_TX_DCC_TX2LN1_PORT1)
+#define CFG_AMI_CK_DIV_OVERRIDE_EN (1 << 24)
+#define CFG_AMI_CK_DIV_OVERRIDE_VAL(x) ((x) << 25)
+#define CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK (0x3 << 25)
/* The spec defines this only for BXT PHY0, but lets assume that this
* would exist for PHY1 too if it had a second channel.
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v2 2/2] drm/i915/icl: Implement voltage swing programming sequence for MG PHY DDI
2018-06-28 22:35 [PATCH v2 1/2] drm/i915/icl: Add remaining registers and bitfields for MG PHY DDI Manasi Navare
@ 2018-06-28 22:35 ` Manasi Navare
2018-07-16 23:48 ` Paulo Zanoni
2018-06-28 23:26 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/2] drm/i915/icl: Add remaining registers and bitfields " Patchwork
` (9 subsequent siblings)
10 siblings, 1 reply; 15+ messages in thread
From: Manasi Navare @ 2018-06-28 22:35 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni, Rodrigo Vivi
This sequence is used to setup voltage swing before enabling MG PHY DDI
as well as for changing the voltage during DisplayPort Link training.
For ICL, there are two types of DDIs. This sequence needs to be used
for MG PHY DDI which is ports C-F.
v6 (From Manasi):
* Add programming for MG_CLKHUB and MG_TX_DCC as per the
spec updates
v5 (from Paulo):
* Checkpatch.
v4 (from Paulo):
* Fix bogus error message
* Fix copy+paste bugs (missing s/TX1/TX2/ after copy+paste)
* Use the new mask names
* Stay under 80 columns
* Add some blank lines
v3:
* Clear the regs before writing (Paulo)
v2:
* Rename to MG PHY in the function def (Jani Nikula)
* Rebase on top of new revision of other patches in series
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 135 +++++++++++++++++++++++++++++++++++++--
1 file changed, 129 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 0319825..c91e96e 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2459,7 +2459,128 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
}
-static void icl_ddi_vswing_sequence(struct intel_encoder *encoder, u32 level,
+static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
+ int link_clock,
+ u32 level)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum port port = encoder->port;
+ const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
+ u32 n_entries, val;
+ int ln;
+
+ n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
+ ddi_translations = icl_mg_phy_ddi_translations;
+ /* The table does not have values for level 3 and level 9. */
+ if (level >= n_entries || level == 3 || level == 9) {
+ DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.",
+ level, n_entries - 2);
+ level = n_entries - 2;
+ }
+
+ /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
+ for (ln = 0; ln < 2; ln++) {
+ val = I915_READ(MG_TX1_LINK_PARAMS(port, ln));
+ val &= ~CRI_USE_FS32;
+ I915_WRITE(MG_TX1_LINK_PARAMS(port, ln), val);
+
+ val = I915_READ(MG_TX2_LINK_PARAMS(port, ln));
+ val &= ~CRI_USE_FS32;
+ I915_WRITE(MG_TX2_LINK_PARAMS(port, ln), val);
+ }
+
+ /* Program MG_TX_SWINGCTRL with values from vswing table */
+ for (ln = 0; ln < 2; ln++) {
+ val = I915_READ(MG_TX1_SWINGCTRL(port, ln));
+ val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
+ val |= CRI_TXDEEMPH_OVERRIDE_17_12(
+ ddi_translations[level].cri_txdeemph_override_17_12);
+ I915_WRITE(MG_TX1_SWINGCTRL(port, ln), val);
+
+ val = I915_READ(MG_TX2_SWINGCTRL(port, ln));
+ val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
+ val |= CRI_TXDEEMPH_OVERRIDE_17_12(
+ ddi_translations[level].cri_txdeemph_override_17_12);
+ I915_WRITE(MG_TX2_SWINGCTRL(port, ln), val);
+ }
+
+ /* Program MG_TX_DRVCTRL with values from vswing table */
+ for (ln = 0; ln < 2; ln++) {
+ val = I915_READ(MG_TX1_DRVCTRL(port, ln));
+ val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
+ CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
+ val |= CRI_TXDEEMPH_OVERRIDE_5_0(
+ ddi_translations[level].cri_txdeemph_override_5_0) |
+ CRI_TXDEEMPH_OVERRIDE_11_6(
+ ddi_translations[level].cri_txdeemph_override_11_6) |
+ CRI_TXDEEMPH_OVERRIDE_EN;
+ I915_WRITE(MG_TX1_DRVCTRL(port, ln), val);
+
+ val = I915_READ(MG_TX2_DRVCTRL(port, ln));
+ val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
+ CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
+ val |= CRI_TXDEEMPH_OVERRIDE_5_0(
+ ddi_translations[level].cri_txdeemph_override_5_0) |
+ CRI_TXDEEMPH_OVERRIDE_11_6(
+ ddi_translations[level].cri_txdeemph_override_11_6) |
+ CRI_TXDEEMPH_OVERRIDE_EN;
+ I915_WRITE(MG_TX2_DRVCTRL(port, ln), val);
+
+ /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
+ }
+
+ /*
+ * Program MG_CLKHUB<LN, port being used> with value from frequency table
+ * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
+ * values from table for which TX1 and TX2 enabled.
+ */
+ for (ln = 0; ln < 2; ln++) {
+ val = I915_READ(MG_CLKHUB(port, ln));
+ if (link_clock < 300000)
+ val |= CFG_LOW_RATE_LKREN_EN;
+ else
+ val &= ~CFG_LOW_RATE_LKREN_EN;
+ I915_WRITE(MG_CLKHUB(port, ln), val);
+ }
+
+ /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
+ for (ln = 0; ln < 2; ln++) {
+ val = I915_READ(MG_TX1_DCC(port, ln));
+ val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
+ if (link_clock <= 500000) {
+ val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
+ } else {
+ val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
+ CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
+ }
+ I915_WRITE(MG_TX1_DCC(port, ln), val);
+
+ val = I915_READ(MG_TX2_DCC(port, ln));
+ val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
+ if (link_clock <= 500000) {
+ val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
+ } else {
+ val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
+ CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
+ }
+ I915_WRITE(MG_TX2_DCC(port, ln), val);
+ }
+
+ /* Program MG_TX_PISO_READLOAD with values from vswing table */
+ for (ln = 0; ln < 2; ln++) {
+ val = I915_READ(MG_TX1_PISO_READLOAD(port, ln));
+ val |= CRI_CALCINIT;
+ I915_WRITE(MG_TX1_PISO_READLOAD(port, ln), val);
+
+ val = I915_READ(MG_TX2_PISO_READLOAD(port, ln));
+ val |= CRI_CALCINIT;
+ I915_WRITE(MG_TX2_PISO_READLOAD(port, ln), val);
+ }
+}
+
+static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
+ int link_clock,
+ u32 level,
enum intel_output_type type)
{
enum port port = encoder->port;
@@ -2467,8 +2588,7 @@ static void icl_ddi_vswing_sequence(struct intel_encoder *encoder, u32 level,
if (port == PORT_A || port == PORT_B)
icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
else
- /* Not Implemented Yet */
- WARN_ON(1);
+ icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
}
static uint32_t translate_signal_level(int signal_levels)
@@ -2503,7 +2623,8 @@ u32 bxt_signal_levels(struct intel_dp *intel_dp)
int level = intel_ddi_dp_level(intel_dp);
if (IS_ICELAKE(dev_priv))
- icl_ddi_vswing_sequence(encoder, level, encoder->type);
+ icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
+ level, encoder->type);
else if (IS_CANNONLAKE(dev_priv))
cnl_ddi_vswing_sequence(encoder, level, encoder->type);
else
@@ -2684,7 +2805,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
if (IS_ICELAKE(dev_priv))
- icl_ddi_vswing_sequence(encoder, level, encoder->type);
+ icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
+ level, encoder->type);
else if (IS_CANNONLAKE(dev_priv))
cnl_ddi_vswing_sequence(encoder, level, encoder->type);
else if (IS_GEN9_LP(dev_priv))
@@ -2719,7 +2841,8 @@ static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
if (IS_ICELAKE(dev_priv))
- icl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
+ icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
+ level, INTEL_OUTPUT_HDMI);
else if (IS_CANNONLAKE(dev_priv))
cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
else if (IS_GEN9_LP(dev_priv))
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 15+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/2] drm/i915/icl: Add remaining registers and bitfields for MG PHY DDI
2018-06-28 22:35 [PATCH v2 1/2] drm/i915/icl: Add remaining registers and bitfields for MG PHY DDI Manasi Navare
2018-06-28 22:35 ` [PATCH v2 2/2] drm/i915/icl: Implement voltage swing programming sequence " Manasi Navare
@ 2018-06-28 23:26 ` Patchwork
2018-06-28 23:42 ` ✓ Fi.CI.BAT: success " Patchwork
` (8 subsequent siblings)
10 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2018-06-28 23:26 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/icl: Add remaining registers and bitfields for MG PHY DDI
URL : https://patchwork.freedesktop.org/series/45623/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d33376c8e4f5 drm/i915/icl: Add remaining registers and bitfields for MG PHY DDI
-:33: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'ln0p1' - possible side-effects?
#33: FILE: drivers/gpu/drm/i915/i915_reg.h:1875:
+#define MG_PHY_PORT_LN(port, ln, ln0p1, ln0p2, ln1p1) \
_MMIO(_PORT((port) - PORT_C, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
total: 0 errors, 0 warnings, 1 checks, 266 lines checked
8ab9898f17b1 drm/i915/icl: Implement voltage swing programming sequence for MG PHY DDI
-:79: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#79: FILE: drivers/gpu/drm/i915/intel_ddi.c:2496:
+ val |= CRI_TXDEEMPH_OVERRIDE_17_12(
-:85: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#85: FILE: drivers/gpu/drm/i915/intel_ddi.c:2502:
+ val |= CRI_TXDEEMPH_OVERRIDE_17_12(
-:95: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#95: FILE: drivers/gpu/drm/i915/intel_ddi.c:2512:
+ val |= CRI_TXDEEMPH_OVERRIDE_5_0(
-:97: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#97: FILE: drivers/gpu/drm/i915/intel_ddi.c:2514:
+ CRI_TXDEEMPH_OVERRIDE_11_6(
-:105: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#105: FILE: drivers/gpu/drm/i915/intel_ddi.c:2522:
+ val |= CRI_TXDEEMPH_OVERRIDE_5_0(
-:107: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#107: FILE: drivers/gpu/drm/i915/intel_ddi.c:2524:
+ CRI_TXDEEMPH_OVERRIDE_11_6(
total: 0 errors, 0 warnings, 6 checks, 165 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/i915/icl: Add remaining registers and bitfields for MG PHY DDI
2018-06-28 22:35 [PATCH v2 1/2] drm/i915/icl: Add remaining registers and bitfields for MG PHY DDI Manasi Navare
2018-06-28 22:35 ` [PATCH v2 2/2] drm/i915/icl: Implement voltage swing programming sequence " Manasi Navare
2018-06-28 23:26 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/2] drm/i915/icl: Add remaining registers and bitfields " Patchwork
@ 2018-06-28 23:42 ` Patchwork
2018-06-29 5:46 ` ✓ Fi.CI.IGT: " Patchwork
` (7 subsequent siblings)
10 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2018-06-28 23:42 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/icl: Add remaining registers and bitfields for MG PHY DDI
URL : https://patchwork.freedesktop.org/series/45623/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4402 -> Patchwork_9478 =
== Summary - SUCCESS ==
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/45623/revisions/1/mbox/
== Known issues ==
Here are the changes found in Patchwork_9478 that come from known issues:
=== IGT changes ===
==== Possible fixes ====
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
fi-snb-2520m: INCOMPLETE (fdo#103713) -> PASS
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
fi-bxt-dsi: INCOMPLETE (fdo#103927) -> PASS
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
== Participating hosts (43 -> 39) ==
Missing (4): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u
== Build changes ==
* Linux: CI_DRM_4402 -> Patchwork_9478
CI_DRM_4402: 5897aa5f98a6519589af4ef97ef7e599209f91ad @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4531: a14bc8b4d69eaca189665de505e6b10cbfbb7730 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9478: 8ab9898f17b129bc287b09c4bc0400510cee5523 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
8ab9898f17b1 drm/i915/icl: Implement voltage swing programming sequence for MG PHY DDI
d33376c8e4f5 drm/i915/icl: Add remaining registers and bitfields for MG PHY DDI
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9478/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* ✓ Fi.CI.IGT: success for series starting with [v2,1/2] drm/i915/icl: Add remaining registers and bitfields for MG PHY DDI
2018-06-28 22:35 [PATCH v2 1/2] drm/i915/icl: Add remaining registers and bitfields for MG PHY DDI Manasi Navare
` (2 preceding siblings ...)
2018-06-28 23:42 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2018-06-29 5:46 ` Patchwork
2018-06-29 20:47 ` [PATCH v2 1/2] " Srivatsa, Anusha
` (6 subsequent siblings)
10 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2018-06-29 5:46 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/icl: Add remaining registers and bitfields for MG PHY DDI
URL : https://patchwork.freedesktop.org/series/45623/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4402_full -> Patchwork_9478_full =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_9478_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_9478_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_9478_full:
=== IGT changes ===
==== Warnings ====
igt@gem_exec_schedule@deep-bsd1:
shard-kbl: PASS -> SKIP +1
igt@pm_rc6_residency@rc6-accuracy:
shard-kbl: SKIP -> PASS
== Known issues ==
Here are the changes found in Patchwork_9478_full that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@drv_selftest@live_gtt:
shard-glk: PASS -> INCOMPLETE (fdo#103359, k.org#198133)
igt@gem_exec_schedule@pi-ringfull-bsd1:
shard-kbl: NOTRUN -> FAIL (fdo#103158)
igt@kms_available_modes_crc@available_mode_test_crc:
shard-kbl: NOTRUN -> FAIL (fdo#106641)
igt@kms_flip@2x-flip-vs-blocking-wf-vblank:
shard-glk: PASS -> FAIL (fdo#100368)
igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
shard-glk: PASS -> FAIL (fdo#105189) +1
igt@kms_flip@modeset-vs-vblank-race:
shard-glk: PASS -> FAIL (fdo#103060)
igt@kms_sysfs_edid_timing:
shard-kbl: NOTRUN -> FAIL (fdo#100047)
igt@kms_vblank@pipe-a-accuracy-idle:
shard-glk: PASS -> FAIL (fdo#102583)
==== Possible fixes ====
igt@kms_flip@plain-flip-fb-recreate:
shard-glk: FAIL (fdo#100368) -> PASS
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#102583 https://bugs.freedesktop.org/show_bug.cgi?id=102583
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#103158 https://bugs.freedesktop.org/show_bug.cgi?id=103158
fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
fdo#105189 https://bugs.freedesktop.org/show_bug.cgi?id=105189
fdo#106641 https://bugs.freedesktop.org/show_bug.cgi?id=106641
k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133
== Participating hosts (5 -> 5) ==
No changes in participating hosts
== Build changes ==
* Linux: CI_DRM_4402 -> Patchwork_9478
CI_DRM_4402: 5897aa5f98a6519589af4ef97ef7e599209f91ad @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4531: a14bc8b4d69eaca189665de505e6b10cbfbb7730 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9478: 8ab9898f17b129bc287b09c4bc0400510cee5523 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9478/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 1/2] drm/i915/icl: Add remaining registers and bitfields for MG PHY DDI
2018-06-28 22:35 [PATCH v2 1/2] drm/i915/icl: Add remaining registers and bitfields for MG PHY DDI Manasi Navare
` (3 preceding siblings ...)
2018-06-29 5:46 ` ✓ Fi.CI.IGT: " Patchwork
@ 2018-06-29 20:47 ` Srivatsa, Anusha
2018-06-29 21:33 ` ✗ Fi.CI.BAT: failure for series starting with [v2,1/2] drm/i915/icl: Add remaining registers and bitfields for MG PHY DDI (rev2) Patchwork
` (5 subsequent siblings)
10 siblings, 0 replies; 15+ messages in thread
From: Srivatsa, Anusha @ 2018-06-29 20:47 UTC (permalink / raw)
To: Navare, Manasi D, intel-gfx; +Cc: Zanoni, Paulo R
________________________________________
From: Intel-gfx [intel-gfx-bounces@lists.freedesktop.org] on behalf of Manasi Navare [manasi.d.navare@intel.com]
Sent: Thursday, June 28, 2018 3:35 PM
To: intel-gfx@lists.freedesktop.org
Cc: Zanoni, Paulo R
Subject: [Intel-gfx] [PATCH v2 1/2] drm/i915/icl: Add remaining registers and bitfields for MG PHY DDI
This patch adds the remaining register definitions and bit fields
required for MG PHy DDI buffer initializations and voltage
swing programming for MG PHy DDI ports.
While at it this patch also fixes the naming for previously defined
MG PHY registers in original commit id (c92f47b5ec977a "drm/i915/icl:
Add register defs for voltage swing sequences for MG PHY DDI").
Since the MG PHY registers are first defined in ICL platform, there
is no need for _ICL prefix.
v2:
* Change the MG_TX_DRVCTL registers names to match the spec (Anusha)
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
checked with Spec. Patch looks good.
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 246 +++++++++++++++++++++++-----------------
1 file changed, 145 insertions(+), 101 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c30cfcd..6119acc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1872,121 +1872,165 @@ enum i915_power_well_id {
#define N_SCALAR(x) ((x) << 24)
#define N_SCALAR_MASK (0x7F << 24)
-#define _ICL_MG_PHY_PORT_LN(port, ln, ln0p1, ln0p2, ln1p1) \
+#define MG_PHY_PORT_LN(port, ln, ln0p1, ln0p2, ln1p1) \
_MMIO(_PORT((port) - PORT_C, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
-#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT1 0x16812C
-#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT1 0x16852C
-#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT2 0x16912C
-#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT2 0x16952C
-#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT3 0x16A12C
-#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT3 0x16A52C
-#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT4 0x16B12C
-#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT4 0x16B52C
-#define ICL_PORT_MG_TX1_LINK_PARAMS(port, ln) \
- _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
- _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
- _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT1)
-
-#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT1 0x1680AC
-#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT1 0x1684AC
-#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT2 0x1690AC
-#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT2 0x1694AC
-#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT3 0x16A0AC
-#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT3 0x16A4AC
-#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT4 0x16B0AC
-#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT4 0x16B4AC
-#define ICL_PORT_MG_TX2_LINK_PARAMS(port, ln) \
- _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
- _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
- _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT1)
+#define MG_TX_LINK_PARAMS_TX1LN0_PORT1 0x16812C
+#define MG_TX_LINK_PARAMS_TX1LN1_PORT1 0x16852C
+#define MG_TX_LINK_PARAMS_TX1LN0_PORT2 0x16912C
+#define MG_TX_LINK_PARAMS_TX1LN1_PORT2 0x16952C
+#define MG_TX_LINK_PARAMS_TX1LN0_PORT3 0x16A12C
+#define MG_TX_LINK_PARAMS_TX1LN1_PORT3 0x16A52C
+#define MG_TX_LINK_PARAMS_TX1LN0_PORT4 0x16B12C
+#define _MG_TX_LINK_PARAMS_TX1LN1_PORT4 0x16B52C
+#define MG_TX1_LINK_PARAMS(port, ln) \
+ MG_PHY_PORT_LN(port, ln, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
+ MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
+ MG_TX_LINK_PARAMS_TX1LN1_PORT1)
+
+#define MG_TX_LINK_PARAMS_TX2LN0_PORT1 0x1680AC
+#define MG_TX_LINK_PARAMS_TX2LN1_PORT1 0x1684AC
+#define MG_TX_LINK_PARAMS_TX2LN0_PORT2 0x1690AC
+#define MG_TX_LINK_PARAMS_TX2LN1_PORT2 0x1694AC
+#define MG_TX_LINK_PARAMS_TX2LN0_PORT3 0x16A0AC
+#define MG_TX_LINK_PARAMS_TX2LN1_PORT3 0x16A4AC
+#define MG_TX_LINK_PARAMS_TX2LN0_PORT4 0x16B0AC
+#define MG_TX_LINK_PARAMS_TX2LN1_PORT4 0x16B4AC
+#define MG_TX2_LINK_PARAMS(port, ln) \
+ MG_PHY_PORT_LN(port, ln, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
+ MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
+ MG_TX_LINK_PARAMS_TX2LN1_PORT1)
#define CRI_USE_FS32 (1 << 5)
-#define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT1 0x16814C
-#define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT1 0x16854C
-#define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT2 0x16914C
-#define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT2 0x16954C
-#define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT3 0x16A14C
-#define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT3 0x16A54C
-#define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT4 0x16B14C
-#define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT4 0x16B54C
-#define ICL_PORT_MG_TX1_PISO_READLOAD(port, ln) \
- _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
- _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT2, \
- _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT1)
-
-#define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT1 0x1680CC
-#define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT1 0x1684CC
-#define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT2 0x1690CC
-#define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT2 0x1694CC
-#define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT3 0x16A0CC
-#define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT3 0x16A4CC
-#define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT4 0x16B0CC
-#define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT4 0x16B4CC
-#define ICL_PORT_MG_TX2_PISO_READLOAD(port, ln) \
- _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
- _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT2, \
- _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT1)
+#define MG_TX_PISO_READLOAD_TX1LN0_PORT1 0x16814C
+#define MG_TX_PISO_READLOAD_TX1LN1_PORT1 0x16854C
+#define MG_TX_PISO_READLOAD_TX1LN0_PORT2 0x16914C
+#define MG_TX_PISO_READLOAD_TX1LN1_PORT2 0x16954C
+#define MG_TX_PISO_READLOAD_TX1LN0_PORT3 0x16A14C
+#define MG_TX_PISO_READLOAD_TX1LN1_PORT3 0x16A54C
+#define MG_TX_PISO_READLOAD_TX1LN0_PORT4 0x16B14C
+#define MG_TX_PISO_READLOAD_TX1LN1_PORT4 0x16B54C
+#define MG_TX1_PISO_READLOAD(port, ln) \
+ MG_PHY_PORT_LN(port, ln, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
+ MG_TX_PISO_READLOAD_TX1LN0_PORT2, \
+ MG_TX_PISO_READLOAD_TX1LN1_PORT1)
+
+#define MG_TX_PISO_READLOAD_TX2LN0_PORT1 0x1680CC
+#define MG_TX_PISO_READLOAD_TX2LN1_PORT1 0x1684CC
+#define MG_TX_PISO_READLOAD_TX2LN0_PORT2 0x1690CC
+#define MG_TX_PISO_READLOAD_TX2LN1_PORT2 0x1694CC
+#define MG_TX_PISO_READLOAD_TX2LN0_PORT3 0x16A0CC
+#define MG_TX_PISO_READLOAD_TX2LN1_PORT3 0x16A4CC
+#define MG_TX_PISO_READLOAD_TX2LN0_PORT4 0x16B0CC
+#define MG_TX_PISO_READLOAD_TX2LN1_PORT4 0x16B4CC
+#define MG_TX2_PISO_READLOAD(port, ln) \
+ MG_PHY_PORT_LN(port, ln, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
+ MG_TX_PISO_READLOAD_TX2LN0_PORT2, \
+ MG_TX_PISO_READLOAD_TX2LN1_PORT1)
#define CRI_CALCINIT (1 << 1)
-#define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT1 0x168148
-#define _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT1 0x168548
-#define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT2 0x169148
-#define _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT2 0x169548
-#define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT3 0x16A148
-#define _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT3 0x16A548
-#define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT4 0x16B148
-#define _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT4 0x16B548
-#define ICL_PORT_MG_TX1_SWINGCTRL(port, ln) \
- _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT1, \
- _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT2, \
- _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT1)
-
-#define _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT1 0x1680C8
-#define _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT1 0x1684C8
-#define _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT2 0x1690C8
-#define _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT2 0x1694C8
-#define _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT3 0x16A0C8
-#define _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT3 0x16A4C8
-#define _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT4 0x16B0C8
-#define _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT4 0x16B4C8
-#define ICL_PORT_MG_TX2_SWINGCTRL(port, ln) \
- _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT1, \
- _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT2, \
- _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT1)
+#define MG_TX_SWINGCTRL_TX1LN0_PORT1 0x168148
+#define MG_TX_SWINGCTRL_TX1LN1_PORT1 0x168548
+#define MG_TX_SWINGCTRL_TX1LN0_PORT2 0x169148
+#define MG_TX_SWINGCTRL_TX1LN1_PORT2 0x169548
+#define MG_TX_SWINGCTRL_TX1LN0_PORT3 0x16A148
+#define MG_TX_SWINGCTRL_TX1LN1_PORT3 0x16A548
+#define MG_TX_SWINGCTRL_TX1LN0_PORT4 0x16B148
+#define MG_TX_SWINGCTRL_TX1LN1_PORT4 0x16B548
+#define MG_TX1_SWINGCTRL(port, ln) \
+ MG_PHY_PORT_LN(port, ln, MG_TX_SWINGCTRL_TX1LN0_PORT1, \
+ MG_TX_SWINGCTRL_TX1LN0_PORT2, \
+ MG_TX_SWINGCTRL_TX1LN1_PORT1)
+
+#define MG_TX_SWINGCTRL_TX2LN0_PORT1 0x1680C8
+#define MG_TX_SWINGCTRL_TX2LN1_PORT1 0x1684C8
+#define MG_TX_SWINGCTRL_TX2LN0_PORT2 0x1690C8
+#define MG_TX_SWINGCTRL_TX2LN1_PORT2 0x1694C8
+#define MG_TX_SWINGCTRL_TX2LN0_PORT3 0x16A0C8
+#define MG_TX_SWINGCTRL_TX2LN1_PORT3 0x16A4C8
+#define MG_TX_SWINGCTRL_TX2LN0_PORT4 0x16B0C8
+#define MG_TX_SWINGCTRL_TX2LN1_PORT4 0x16B4C8
+#define MG_TX2_SWINGCTRL(port, ln) \
+ MG_PHY_PORT_LN(port, ln, MG_TX_SWINGCTRL_TX2LN0_PORT1, \
+ MG_TX_SWINGCTRL_TX2LN0_PORT2, \
+ MG_TX_SWINGCTRL_TX2LN1_PORT1)
#define CRI_TXDEEMPH_OVERRIDE_17_12(x) ((x) << 0)
#define CRI_TXDEEMPH_OVERRIDE_17_12_MASK (0x3F << 0)
-#define _ICL_MG_TX_DRVCTRL_TX1LN0_PORT1 0x168144
-#define _ICL_MG_TX_DRVCTRL_TX1LN1_PORT1 0x168544
-#define _ICL_MG_TX_DRVCTRL_TX1LN0_PORT2 0x169144
-#define _ICL_MG_TX_DRVCTRL_TX1LN1_PORT2 0x169544
-#define _ICL_MG_TX_DRVCTRL_TX1LN0_PORT3 0x16A144
-#define _ICL_MG_TX_DRVCTRL_TX1LN1_PORT3 0x16A544
-#define _ICL_MG_TX_DRVCTRL_TX1LN0_PORT4 0x16B144
-#define _ICL_MG_TX_DRVCTRL_TX1LN1_PORT4 0x16B544
-#define ICL_PORT_MG_TX1_DRVCTRL(port, ln) \
- _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_DRVCTRL_TX1LN0_PORT1, \
- _ICL_MG_TX_DRVCTRL_TX1LN0_PORT2, \
- _ICL_MG_TX_DRVCTRL_TX1LN1_PORT1)
-
-#define _ICL_MG_TX_DRVCTRL_TX2LN0_PORT1 0x1680C4
-#define _ICL_MG_TX_DRVCTRL_TX2LN1_PORT1 0x1684C4
-#define _ICL_MG_TX_DRVCTRL_TX2LN0_PORT2 0x1690C4
-#define _ICL_MG_TX_DRVCTRL_TX2LN1_PORT2 0x1694C4
-#define _ICL_MG_TX_DRVCTRL_TX2LN0_PORT3 0x16A0C4
-#define _ICL_MG_TX_DRVCTRL_TX2LN1_PORT3 0x16A4C4
-#define _ICL_MG_TX_DRVCTRL_TX2LN0_PORT4 0x16B0C4
-#define _ICL_MG_TX_DRVCTRL_TX2LN1_PORT4 0x16B4C4
-#define ICL_PORT_MG_TX2_DRVCTRL(port, ln) \
- _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_DRVCTRL_TX2LN0_PORT1, \
- _ICL_MG_TX_DRVCTRL_TX2LN0_PORT2, \
- _ICL_MG_TX_DRVCTRL_TX2LN1_PORT1)
+#define MG_TX_DRVCTRL_TX1LN0_TXPORT1 0x168144
+#define MG_TX_DRVCTRL_TX1LN1_TXPORT1 0x168544
+#define MG_TX_DRVCTRL_TX1LN0_TXPORT2 0x169144
+#define MG_TX_DRVCTRL_TX1LN1_TXPORT2 0x169544
+#define MG_TX_DRVCTRL_TX1LN0_TXPORT3 0x16A144
+#define MG_TX_DRVCTRL_TX1LN1_TXPORT3 0x16A544
+#define MG_TX_DRVCTRL_TX1LN0_TXPORT4 0x16B144
+#define MG_TX_DRVCTRL_TX1LN1_TXPORT4 0x16B544
+#define MG_TX1_DRVCTRL(port, ln) \
+ MG_PHY_PORT_LN(port, ln, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \
+ MG_TX_DRVCTRL_TX1LN0_TXPORT2, \
+ MG_TX_DRVCTRL_TX1LN1_TXPORT1)
+
+#define MG_TX_DRVCTRL_TX2LN0_PORT1 0x1680C4
+#define MG_TX_DRVCTRL_TX2LN1_PORT1 0x1684C4
+#define MG_TX_DRVCTRL_TX2LN0_PORT2 0x1690C4
+#define MG_TX_DRVCTRL_TX2LN1_PORT2 0x1694C4
+#define MG_TX_DRVCTRL_TX2LN0_PORT3 0x16A0C4
+#define MG_TX_DRVCTRL_TX2LN1_PORT3 0x16A4C4
+#define MG_TX_DRVCTRL_TX2LN0_PORT4 0x16B0C4
+#define MG_TX_DRVCTRL_TX2LN1_PORT4 0x16B4C4
+#define MG_TX2_DRVCTRL(port, ln) \
+ MG_PHY_PORT_LN(port, ln, MG_TX_DRVCTRL_TX2LN0_PORT1, \
+ MG_TX_DRVCTRL_TX2LN0_PORT2, \
+ MG_TX_DRVCTRL_TX2LN1_PORT1)
#define CRI_TXDEEMPH_OVERRIDE_11_6(x) ((x) << 24)
#define CRI_TXDEEMPH_OVERRIDE_11_6_MASK (0x3F << 24)
#define CRI_TXDEEMPH_OVERRIDE_EN (1 << 22)
#define CRI_TXDEEMPH_OVERRIDE_5_0(x) ((x) << 16)
#define CRI_TXDEEMPH_OVERRIDE_5_0_MASK (0x3F << 16)
+#define CRI_LOADGEN_SEL(x) ((x) << 12)
+#define CRI_LOADGEN_SEL_MASK (0x3 << 12)
+#define MG_CLKHUB_LN0_PORT1 0x16839C
+#define MG_CLKHUB_LN1_PORT1 0x16879C
+#define MG_CLKHUB_LN0_PORT2 0x16939C
+#define MG_CLKHUB_LN1_PORT2 0x16979C
+#define MG_CLKHUB_LN0_PORT3 0x16A39C
+#define MG_CLKHUB_LN1_PORT3 0x16A79C
+#define MG_CLKHUB_LN0_PORT4 0x16B39C
+#define MG_CLKHUB_LN1_PORT4 0x16B79C
+#define MG_CLKHUB(port, ln) \
+ MG_PHY_PORT_LN(port, ln, MG_CLKHUB_LN0_PORT1, \
+ MG_CLKHUB_LN0_PORT2, \
+ MG_CLKHUB_LN1_PORT1)
+#define CFG_LOW_RATE_LKREN_EN (1 << 11)
+
+#define MG_TX_DCC_TX1LN0_PORT1 0x168110
+#define MG_TX_DCC_TX1LN1_PORT1 0x168510
+#define MG_TX_DCC_TX1LNO_PORT2 0x169110
+#define MG_TX_DCC_TX1LN1_PORT2 0x169510
+#define MG_TX_DCC_TX1LNO_PORT3 0x16A110
+#define MG_TX_DCC_TX1LN1_PORT3 0x16A510
+#define MG_TX_DCC_TX1LNO_PORT4 0x16B110
+#define MG_TX_DCC_TX1LN1_PORT4 0x16B510
+#define MG_TX1_DCC(port, ln) \
+ MG_PHY_PORT_LN(port, ln, MG_TX_DCC_TX1LN0_PORT1, \
+ MG_TX_DCC_TX1LNO_PORT2, \
+ MG_TX_DCC_TX1LN1_PORT1)
+#define MG_TX_DCC_TX2LN0_PORT1 0x168090
+#define MG_TX_DCC_TX2LN1_PORT1 0x168490
+#define MG_TX_DCC_TX2LNO_PORT2 0x169090
+#define MG_TX_DCC_TX2LN1_PORT2 0x169490
+#define MG_TX_DCC_TX2LNO_PORT3 0x16A090
+#define MG_TX_DCC_TX2LN1_PORT3 0x16A490
+#define MG_TX_DCC_TX2LNO_PORT4 0x16B090
+#define MG_TX_DCC_TX2LN1_PORT4 0x16B490
+#define MG_TX2_DCC(port, ln) \
+ MG_PHY_PORT_LN(port, ln, MG_TX_DCC_TX2LN0_PORT1, \
+ MG_TX_DCC_TX2LNO_PORT2, \
+ MG_TX_DCC_TX2LN1_PORT1)
+#define CFG_AMI_CK_DIV_OVERRIDE_EN (1 << 24)
+#define CFG_AMI_CK_DIV_OVERRIDE_VAL(x) ((x) << 25)
+#define CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK (0x3 << 25)
/* The spec defines this only for BXT PHY0, but lets assume that this
* would exist for PHY1 too if it had a second channel.
--
2.7.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 15+ messages in thread
* ✗ Fi.CI.BAT: failure for series starting with [v2,1/2] drm/i915/icl: Add remaining registers and bitfields for MG PHY DDI (rev2)
2018-06-28 22:35 [PATCH v2 1/2] drm/i915/icl: Add remaining registers and bitfields for MG PHY DDI Manasi Navare
` (4 preceding siblings ...)
2018-06-29 20:47 ` [PATCH v2 1/2] " Srivatsa, Anusha
@ 2018-06-29 21:33 ` Patchwork
2018-07-03 18:07 ` [PATCH v2 1/2] drm/i915/icl: Add remaining registers and bitfields for MG PHY DDI Srivatsa, Anusha
` (4 subsequent siblings)
10 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2018-06-29 21:33 UTC (permalink / raw)
To: Srivatsa, Anusha; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/icl: Add remaining registers and bitfields for MG PHY DDI (rev2)
URL : https://patchwork.freedesktop.org/series/45623/
State : failure
== Summary ==
Applying: drm/i915/icl: Add remaining registers and bitfields for MG PHY DDI
error: corrupt patch at line 273
error: could not build fake ancestor
Patch failed at 0001 drm/i915/icl: Add remaining registers and bitfields for MG PHY DDI
Use 'git am --show-current-patch' to see the failed patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 1/2] drm/i915/icl: Add remaining registers and bitfields for MG PHY DDI
2018-06-28 22:35 [PATCH v2 1/2] drm/i915/icl: Add remaining registers and bitfields for MG PHY DDI Manasi Navare
` (5 preceding siblings ...)
2018-06-29 21:33 ` ✗ Fi.CI.BAT: failure for series starting with [v2,1/2] drm/i915/icl: Add remaining registers and bitfields for MG PHY DDI (rev2) Patchwork
@ 2018-07-03 18:07 ` Srivatsa, Anusha
2018-07-13 0:00 ` Paulo Zanoni
` (3 subsequent siblings)
10 siblings, 0 replies; 15+ messages in thread
From: Srivatsa, Anusha @ 2018-07-03 18:07 UTC (permalink / raw)
To: Navare, Manasi D, intel-gfx; +Cc: Zanoni, Paulo R
>-----Original Message-----
>From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of
>Manasi Navare
>Sent: Thursday, June 28, 2018 3:36 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Zanoni, Paulo R <paulo.r.zanoni@intel.com>
>Subject: [Intel-gfx] [PATCH v2 1/2] drm/i915/icl: Add remaining registers and
>bitfields for MG PHY DDI
>
>This patch adds the remaining register definitions and bit fields required for MG
>PHy DDI buffer initializations and voltage swing programming for MG PHy DDI
>ports.
>
>While at it this patch also fixes the naming for previously defined MG PHY
>registers in original commit id (c92f47b5ec977a "drm/i915/icl:
>Add register defs for voltage swing sequences for MG PHY DDI").
>Since the MG PHY registers are first defined in ICL platform, there is no need for
>_ICL prefix.
>
>v2:
>* Change the MG_TX_DRVCTL registers names to match the spec (Anusha)
>
>Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
>Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
>Cc: James Ausmus <james.ausmus@intel.com>
Sending review again since it didn’t hit patchwork the last time.
Compared the register definitions with the BSpec.
Looks good.
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>---
> drivers/gpu/drm/i915/i915_reg.h | 246 +++++++++++++++++++++++----------------
>-
> 1 file changed, 145 insertions(+), 101 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index c30cfcd..6119acc 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -1872,121 +1872,165 @@ enum i915_power_well_id {
> #define N_SCALAR(x) ((x) << 24)
> #define N_SCALAR_MASK (0x7F << 24)
>
>-#define _ICL_MG_PHY_PORT_LN(port, ln, ln0p1, ln0p2, ln1p1) \
>+#define MG_PHY_PORT_LN(port, ln, ln0p1, ln0p2, ln1p1) \
> _MMIO(_PORT((port) - PORT_C, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
>
>-#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT1 0x16812C
>-#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT1 0x16852C
>-#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT2 0x16912C
>-#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT2 0x16952C
>-#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT3 0x16A12C
>-#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT3 0x16A52C
>-#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT4 0x16B12C
>-#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT4 0x16B52C
>-#define ICL_PORT_MG_TX1_LINK_PARAMS(port, ln) \
>- _ICL_MG_PHY_PORT_LN(port, ln,
>_ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
>-
>_ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
>-
>_ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT1)
>-
>-#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT1 0x1680AC
>-#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT1 0x1684AC
>-#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT2 0x1690AC
>-#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT2 0x1694AC
>-#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT3 0x16A0AC
>-#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT3 0x16A4AC
>-#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT4 0x16B0AC
>-#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT4 0x16B4AC
>-#define ICL_PORT_MG_TX2_LINK_PARAMS(port, ln) \
>- _ICL_MG_PHY_PORT_LN(port, ln,
>_ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
>-
>_ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
>-
>_ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT1)
>+#define MG_TX_LINK_PARAMS_TX1LN0_PORT1 0x16812C
>+#define MG_TX_LINK_PARAMS_TX1LN1_PORT1 0x16852C
>+#define MG_TX_LINK_PARAMS_TX1LN0_PORT2 0x16912C
>+#define MG_TX_LINK_PARAMS_TX1LN1_PORT2 0x16952C
>+#define MG_TX_LINK_PARAMS_TX1LN0_PORT3 0x16A12C
>+#define MG_TX_LINK_PARAMS_TX1LN1_PORT3 0x16A52C
>+#define MG_TX_LINK_PARAMS_TX1LN0_PORT4 0x16B12C
>+#define _MG_TX_LINK_PARAMS_TX1LN1_PORT4 0x16B52C
>+#define MG_TX1_LINK_PARAMS(port, ln) \
>+ MG_PHY_PORT_LN(port, ln, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
>+ MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
>+ MG_TX_LINK_PARAMS_TX1LN1_PORT1)
>+
>+#define MG_TX_LINK_PARAMS_TX2LN0_PORT1 0x1680AC
>+#define MG_TX_LINK_PARAMS_TX2LN1_PORT1 0x1684AC
>+#define MG_TX_LINK_PARAMS_TX2LN0_PORT2 0x1690AC
>+#define MG_TX_LINK_PARAMS_TX2LN1_PORT2 0x1694AC
>+#define MG_TX_LINK_PARAMS_TX2LN0_PORT3 0x16A0AC
>+#define MG_TX_LINK_PARAMS_TX2LN1_PORT3 0x16A4AC
>+#define MG_TX_LINK_PARAMS_TX2LN0_PORT4 0x16B0AC
>+#define MG_TX_LINK_PARAMS_TX2LN1_PORT4 0x16B4AC
>+#define MG_TX2_LINK_PARAMS(port, ln) \
>+ MG_PHY_PORT_LN(port, ln, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
>+ MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
>+ MG_TX_LINK_PARAMS_TX2LN1_PORT1)
> #define CRI_USE_FS32 (1 << 5)
>
>-#define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT1 0x16814C
>-#define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT1 0x16854C
>-#define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT2 0x16914C
>-#define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT2 0x16954C
>-#define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT3 0x16A14C
>-#define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT3 0x16A54C
>-#define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT4 0x16B14C
>-#define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT4 0x16B54C
>-#define ICL_PORT_MG_TX1_PISO_READLOAD(port, ln) \
>- _ICL_MG_PHY_PORT_LN(port, ln,
>_ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
>-
>_ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT2, \
>-
>_ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT1)
>-
>-#define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT1 0x1680CC
>-#define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT1 0x1684CC
>-#define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT2 0x1690CC
>-#define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT2 0x1694CC
>-#define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT3 0x16A0CC
>-#define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT3 0x16A4CC
>-#define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT4 0x16B0CC
>-#define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT4 0x16B4CC
>-#define ICL_PORT_MG_TX2_PISO_READLOAD(port, ln) \
>- _ICL_MG_PHY_PORT_LN(port, ln,
>_ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
>-
>_ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT2, \
>-
>_ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT1)
>+#define MG_TX_PISO_READLOAD_TX1LN0_PORT1 0x16814C
>+#define MG_TX_PISO_READLOAD_TX1LN1_PORT1 0x16854C
>+#define MG_TX_PISO_READLOAD_TX1LN0_PORT2 0x16914C
>+#define MG_TX_PISO_READLOAD_TX1LN1_PORT2 0x16954C
>+#define MG_TX_PISO_READLOAD_TX1LN0_PORT3 0x16A14C
>+#define MG_TX_PISO_READLOAD_TX1LN1_PORT3 0x16A54C
>+#define MG_TX_PISO_READLOAD_TX1LN0_PORT4 0x16B14C
>+#define MG_TX_PISO_READLOAD_TX1LN1_PORT4 0x16B54C
>+#define MG_TX1_PISO_READLOAD(port, ln) \
>+ MG_PHY_PORT_LN(port, ln, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
>+ MG_TX_PISO_READLOAD_TX1LN0_PORT2, \
>+ MG_TX_PISO_READLOAD_TX1LN1_PORT1)
>+
>+#define MG_TX_PISO_READLOAD_TX2LN0_PORT1 0x1680CC
>+#define MG_TX_PISO_READLOAD_TX2LN1_PORT1 0x1684CC
>+#define MG_TX_PISO_READLOAD_TX2LN0_PORT2 0x1690CC
>+#define MG_TX_PISO_READLOAD_TX2LN1_PORT2 0x1694CC
>+#define MG_TX_PISO_READLOAD_TX2LN0_PORT3 0x16A0CC
>+#define MG_TX_PISO_READLOAD_TX2LN1_PORT3 0x16A4CC
>+#define MG_TX_PISO_READLOAD_TX2LN0_PORT4 0x16B0CC
>+#define MG_TX_PISO_READLOAD_TX2LN1_PORT4 0x16B4CC
>+#define MG_TX2_PISO_READLOAD(port, ln) \
>+ MG_PHY_PORT_LN(port, ln, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
>+ MG_TX_PISO_READLOAD_TX2LN0_PORT2, \
>+ MG_TX_PISO_READLOAD_TX2LN1_PORT1)
> #define CRI_CALCINIT (1 << 1)
>
>-#define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT1 0x168148
>-#define _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT1 0x168548
>-#define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT2 0x169148
>-#define _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT2 0x169548
>-#define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT3 0x16A148
>-#define _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT3 0x16A548
>-#define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT4 0x16B148
>-#define _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT4 0x16B548
>-#define ICL_PORT_MG_TX1_SWINGCTRL(port, ln) \
>- _ICL_MG_PHY_PORT_LN(port, ln,
>_ICL_MG_TX_SWINGCTRL_TX1LN0_PORT1, \
>- _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT2, \
>- _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT1)
>-
>-#define _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT1 0x1680C8
>-#define _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT1 0x1684C8
>-#define _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT2 0x1690C8
>-#define _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT2 0x1694C8
>-#define _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT3 0x16A0C8
>-#define _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT3 0x16A4C8
>-#define _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT4 0x16B0C8
>-#define _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT4 0x16B4C8
>-#define ICL_PORT_MG_TX2_SWINGCTRL(port, ln) \
>- _ICL_MG_PHY_PORT_LN(port, ln,
>_ICL_MG_TX_SWINGCTRL_TX2LN0_PORT1, \
>- _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT2, \
>- _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT1)
>+#define MG_TX_SWINGCTRL_TX1LN0_PORT1 0x168148
>+#define MG_TX_SWINGCTRL_TX1LN1_PORT1 0x168548
>+#define MG_TX_SWINGCTRL_TX1LN0_PORT2 0x169148
>+#define MG_TX_SWINGCTRL_TX1LN1_PORT2 0x169548
>+#define MG_TX_SWINGCTRL_TX1LN0_PORT3 0x16A148
>+#define MG_TX_SWINGCTRL_TX1LN1_PORT3 0x16A548
>+#define MG_TX_SWINGCTRL_TX1LN0_PORT4 0x16B148
>+#define MG_TX_SWINGCTRL_TX1LN1_PORT4 0x16B548
>+#define MG_TX1_SWINGCTRL(port, ln) \
>+ MG_PHY_PORT_LN(port, ln, MG_TX_SWINGCTRL_TX1LN0_PORT1, \
>+ MG_TX_SWINGCTRL_TX1LN0_PORT2, \
>+ MG_TX_SWINGCTRL_TX1LN1_PORT1)
>+
>+#define MG_TX_SWINGCTRL_TX2LN0_PORT1 0x1680C8
>+#define MG_TX_SWINGCTRL_TX2LN1_PORT1 0x1684C8
>+#define MG_TX_SWINGCTRL_TX2LN0_PORT2 0x1690C8
>+#define MG_TX_SWINGCTRL_TX2LN1_PORT2 0x1694C8
>+#define MG_TX_SWINGCTRL_TX2LN0_PORT3 0x16A0C8
>+#define MG_TX_SWINGCTRL_TX2LN1_PORT3 0x16A4C8
>+#define MG_TX_SWINGCTRL_TX2LN0_PORT4 0x16B0C8
>+#define MG_TX_SWINGCTRL_TX2LN1_PORT4 0x16B4C8
>+#define MG_TX2_SWINGCTRL(port, ln) \
>+ MG_PHY_PORT_LN(port, ln, MG_TX_SWINGCTRL_TX2LN0_PORT1, \
>+ MG_TX_SWINGCTRL_TX2LN0_PORT2, \
>+ MG_TX_SWINGCTRL_TX2LN1_PORT1)
> #define CRI_TXDEEMPH_OVERRIDE_17_12(x) ((x) << 0)
> #define CRI_TXDEEMPH_OVERRIDE_17_12_MASK (0x3F << 0)
>
>-#define _ICL_MG_TX_DRVCTRL_TX1LN0_PORT1
> 0x168144
>-#define _ICL_MG_TX_DRVCTRL_TX1LN1_PORT1
> 0x168544
>-#define _ICL_MG_TX_DRVCTRL_TX1LN0_PORT2
> 0x169144
>-#define _ICL_MG_TX_DRVCTRL_TX1LN1_PORT2
> 0x169544
>-#define _ICL_MG_TX_DRVCTRL_TX1LN0_PORT3
> 0x16A144
>-#define _ICL_MG_TX_DRVCTRL_TX1LN1_PORT3
> 0x16A544
>-#define _ICL_MG_TX_DRVCTRL_TX1LN0_PORT4
> 0x16B144
>-#define _ICL_MG_TX_DRVCTRL_TX1LN1_PORT4
> 0x16B544
>-#define ICL_PORT_MG_TX1_DRVCTRL(port, ln) \
>- _ICL_MG_PHY_PORT_LN(port, ln,
>_ICL_MG_TX_DRVCTRL_TX1LN0_PORT1, \
>- _ICL_MG_TX_DRVCTRL_TX1LN0_PORT2, \
>- _ICL_MG_TX_DRVCTRL_TX1LN1_PORT1)
>-
>-#define _ICL_MG_TX_DRVCTRL_TX2LN0_PORT1
> 0x1680C4
>-#define _ICL_MG_TX_DRVCTRL_TX2LN1_PORT1
> 0x1684C4
>-#define _ICL_MG_TX_DRVCTRL_TX2LN0_PORT2
> 0x1690C4
>-#define _ICL_MG_TX_DRVCTRL_TX2LN1_PORT2
> 0x1694C4
>-#define _ICL_MG_TX_DRVCTRL_TX2LN0_PORT3
> 0x16A0C4
>-#define _ICL_MG_TX_DRVCTRL_TX2LN1_PORT3
> 0x16A4C4
>-#define _ICL_MG_TX_DRVCTRL_TX2LN0_PORT4
> 0x16B0C4
>-#define _ICL_MG_TX_DRVCTRL_TX2LN1_PORT4
> 0x16B4C4
>-#define ICL_PORT_MG_TX2_DRVCTRL(port, ln) \
>- _ICL_MG_PHY_PORT_LN(port, ln,
>_ICL_MG_TX_DRVCTRL_TX2LN0_PORT1, \
>- _ICL_MG_TX_DRVCTRL_TX2LN0_PORT2, \
>- _ICL_MG_TX_DRVCTRL_TX2LN1_PORT1)
>+#define MG_TX_DRVCTRL_TX1LN0_TXPORT1 0x168144
>+#define MG_TX_DRVCTRL_TX1LN1_TXPORT1 0x168544
>+#define MG_TX_DRVCTRL_TX1LN0_TXPORT2 0x169144
>+#define MG_TX_DRVCTRL_TX1LN1_TXPORT2 0x169544
>+#define MG_TX_DRVCTRL_TX1LN0_TXPORT3 0x16A144
>+#define MG_TX_DRVCTRL_TX1LN1_TXPORT3 0x16A544
>+#define MG_TX_DRVCTRL_TX1LN0_TXPORT4 0x16B144
>+#define MG_TX_DRVCTRL_TX1LN1_TXPORT4 0x16B544
>+#define MG_TX1_DRVCTRL(port, ln) \
>+ MG_PHY_PORT_LN(port, ln, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \
>+ MG_TX_DRVCTRL_TX1LN0_TXPORT2, \
>+ MG_TX_DRVCTRL_TX1LN1_TXPORT1)
>+
>+#define MG_TX_DRVCTRL_TX2LN0_PORT1 0x1680C4
>+#define MG_TX_DRVCTRL_TX2LN1_PORT1 0x1684C4
>+#define MG_TX_DRVCTRL_TX2LN0_PORT2 0x1690C4
>+#define MG_TX_DRVCTRL_TX2LN1_PORT2 0x1694C4
>+#define MG_TX_DRVCTRL_TX2LN0_PORT3 0x16A0C4
>+#define MG_TX_DRVCTRL_TX2LN1_PORT3 0x16A4C4
>+#define MG_TX_DRVCTRL_TX2LN0_PORT4 0x16B0C4
>+#define MG_TX_DRVCTRL_TX2LN1_PORT4 0x16B4C4
>+#define MG_TX2_DRVCTRL(port, ln) \
>+ MG_PHY_PORT_LN(port, ln, MG_TX_DRVCTRL_TX2LN0_PORT1, \
>+ MG_TX_DRVCTRL_TX2LN0_PORT2, \
>+ MG_TX_DRVCTRL_TX2LN1_PORT1)
> #define CRI_TXDEEMPH_OVERRIDE_11_6(x) ((x) << 24)
> #define CRI_TXDEEMPH_OVERRIDE_11_6_MASK (0x3F
><< 24)
> #define CRI_TXDEEMPH_OVERRIDE_EN (1 << 22)
> #define CRI_TXDEEMPH_OVERRIDE_5_0(x) ((x) << 16)
> #define CRI_TXDEEMPH_OVERRIDE_5_0_MASK (0x3F << 16)
>+#define CRI_LOADGEN_SEL(x) ((x) << 12)
>+#define CRI_LOADGEN_SEL_MASK (0x3 << 12)
>+
>+#define MG_CLKHUB_LN0_PORT1 0x16839C
>+#define MG_CLKHUB_LN1_PORT1 0x16879C
>+#define MG_CLKHUB_LN0_PORT2 0x16939C
>+#define MG_CLKHUB_LN1_PORT2 0x16979C
>+#define MG_CLKHUB_LN0_PORT3 0x16A39C
>+#define MG_CLKHUB_LN1_PORT3 0x16A79C
>+#define MG_CLKHUB_LN0_PORT4 0x16B39C
>+#define MG_CLKHUB_LN1_PORT4 0x16B79C
>+#define MG_CLKHUB(port, ln) \
>+ MG_PHY_PORT_LN(port, ln, MG_CLKHUB_LN0_PORT1, \
>+ MG_CLKHUB_LN0_PORT2, \
>+ MG_CLKHUB_LN1_PORT1)
>+#define CFG_LOW_RATE_LKREN_EN (1 << 11)
>+
>+#define MG_TX_DCC_TX1LN0_PORT1 0x168110
>+#define MG_TX_DCC_TX1LN1_PORT1 0x168510
>+#define MG_TX_DCC_TX1LNO_PORT2 0x169110
>+#define MG_TX_DCC_TX1LN1_PORT2 0x169510
>+#define MG_TX_DCC_TX1LNO_PORT3 0x16A110
>+#define MG_TX_DCC_TX1LN1_PORT3 0x16A510
>+#define MG_TX_DCC_TX1LNO_PORT4 0x16B110
>+#define MG_TX_DCC_TX1LN1_PORT4 0x16B510
>+#define MG_TX1_DCC(port, ln) \
>+ MG_PHY_PORT_LN(port, ln, MG_TX_DCC_TX1LN0_PORT1, \
>+ MG_TX_DCC_TX1LNO_PORT2, \
>+ MG_TX_DCC_TX1LN1_PORT1)
>+#define MG_TX_DCC_TX2LN0_PORT1 0x168090
>+#define MG_TX_DCC_TX2LN1_PORT1 0x168490
>+#define MG_TX_DCC_TX2LNO_PORT2 0x169090
>+#define MG_TX_DCC_TX2LN1_PORT2 0x169490
>+#define MG_TX_DCC_TX2LNO_PORT3 0x16A090
>+#define MG_TX_DCC_TX2LN1_PORT3 0x16A490
>+#define MG_TX_DCC_TX2LNO_PORT4 0x16B090
>+#define MG_TX_DCC_TX2LN1_PORT4 0x16B490
>+#define MG_TX2_DCC(port, ln) \
>+ MG_PHY_PORT_LN(port, ln, MG_TX_DCC_TX2LN0_PORT1, \
>+ MG_TX_DCC_TX2LNO_PORT2, \
>+ MG_TX_DCC_TX2LN1_PORT1)
>+#define CFG_AMI_CK_DIV_OVERRIDE_EN (1 << 24)
>+#define CFG_AMI_CK_DIV_OVERRIDE_VAL(x) ((x) << 25)
>+#define CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK (0x3 << 25)
>
> /* The spec defines this only for BXT PHY0, but lets assume that this
> * would exist for PHY1 too if it had a second channel.
>--
>2.7.4
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 1/2] drm/i915/icl: Add remaining registers and bitfields for MG PHY DDI
2018-06-28 22:35 [PATCH v2 1/2] drm/i915/icl: Add remaining registers and bitfields for MG PHY DDI Manasi Navare
` (6 preceding siblings ...)
2018-07-03 18:07 ` [PATCH v2 1/2] drm/i915/icl: Add remaining registers and bitfields for MG PHY DDI Srivatsa, Anusha
@ 2018-07-13 0:00 ` Paulo Zanoni
2018-07-13 18:44 ` Manasi Navare
2018-07-13 19:43 ` [PATCH v3] " Manasi Navare
` (2 subsequent siblings)
10 siblings, 1 reply; 15+ messages in thread
From: Paulo Zanoni @ 2018-07-13 0:00 UTC (permalink / raw)
To: Manasi Navare, intel-gfx
Em Qui, 2018-06-28 às 15:35 -0700, Manasi Navare escreveu:
> This patch adds the remaining register definitions and bit fields
> required for MG PHy DDI buffer initializations and voltage
> swing programming for MG PHy DDI ports.
>
> While at it this patch also fixes the naming for previously defined
> MG PHY registers in original commit id (c92f47b5ec977a "drm/i915/icl:
> Add register defs for voltage swing sequences for MG PHY DDI").
> Since the MG PHY registers are first defined in ICL platform, there
> is no need for _ICL prefix.
IMHO drive-by "do this other trivial thing"s are fine when it's only 1
or 2 small chunks affected. In this case it's half of the patch, so I
would prefer having it in a separate patch. But let's leave it as-is
here since at least the registers being touched are not used.
More below.
>
> v2:
> * Change the MG_TX_DRVCTL registers names to match the spec (Anusha)
>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: James Ausmus <james.ausmus@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 246 +++++++++++++++++++++++-------
> ----------
> 1 file changed, 145 insertions(+), 101 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index c30cfcd..6119acc 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1872,121 +1872,165 @@ enum i915_power_well_id {
> #define N_SCALAR(x) ((x) << 24)
> #define N_SCALAR_MASK (0x7F << 24)
>
> -#define _ICL_MG_PHY_PORT_LN(port, ln, ln0p1, ln0p2, ln1p1) \
> +#define MG_PHY_PORT_LN(port, ln, ln0p1, ln0p2, ln1p1) \
> _MMIO(_PORT((port) - PORT_C, ln0p1, ln0p2) + (ln) * ((ln1p1)
> - (ln0p1)))
>
> -#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT1 0x16812C
> -#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT1 0x16852C
> -#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT2 0x16912C
> -#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT2 0x16952C
> -#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT3 0x16A12C
> -#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT3 0x16A52C
> -#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT4 0x16B12C
> -#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT4 0x16B52C
> -#define ICL_PORT_MG_TX1_LINK_PARAMS(port, ln) \
> - _ICL_MG_PHY_PORT_LN(port, ln,
> _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
> - _ICL_MG_TX_LINK_PARAMS_TX1LN0_
> PORT2, \
> - _ICL_MG_TX_LINK_PARAMS_TX1LN1_
> PORT1)
> -
> -#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT1 0x1680AC
> -#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT1 0x1684AC
> -#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT2 0x1690AC
> -#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT2 0x1694AC
> -#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT3 0x16A0AC
> -#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT3 0x16A4AC
> -#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT4 0x16B0AC
> -#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT4 0x16B4AC
> -#define ICL_PORT_MG_TX2_LINK_PARAMS(port, ln) \
> - _ICL_MG_PHY_PORT_LN(port, ln,
> _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
> - _ICL_MG_TX_LINK_PARAMS_TX2LN0_
> PORT2, \
> - _ICL_MG_TX_LINK_PARAMS_TX2LN1_
> PORT1)
> +#define MG_TX_LINK_PARAMS_TX1LN0_PORT1 0x16812C
> +#define MG_TX_LINK_PARAMS_TX1LN1_PORT1 0x16852C
> +#define MG_TX_LINK_PARAMS_TX1LN0_PORT2 0x16912C
> +#define MG_TX_LINK_PARAMS_TX1LN1_PORT2 0x16952C
> +#define MG_TX_LINK_PARAMS_TX1LN0_PORT3 0x16A12C
> +#define MG_TX_LINK_PARAMS_TX1LN1_PORT3 0x16A52C
> +#define MG_TX_LINK_PARAMS_TX1LN0_PORT4 0x16B12C
> +#define _MG_TX_LINK_PARAMS_TX1LN1_PORT4 0x16B52C
You left an underline on the line above.
> +#define MG_TX1_LINK_PARAMS(port, ln) \
> + MG_PHY_PORT_LN(port, ln, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
> + MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
> + MG_TX_LINK_PARAMS_TX1LN1_PORT1)
> +
> +#define MG_TX_LINK_PARAMS_TX2LN0_PORT1 0x1680AC
> +#define MG_TX_LINK_PARAMS_TX2LN1_PORT1 0x1684AC
> +#define MG_TX_LINK_PARAMS_TX2LN0_PORT2 0x1690AC
> +#define MG_TX_LINK_PARAMS_TX2LN1_PORT2 0x1694AC
> +#define MG_TX_LINK_PARAMS_TX2LN0_PORT3 0x16A0AC
> +#define MG_TX_LINK_PARAMS_TX2LN1_PORT3 0x16A4AC
> +#define MG_TX_LINK_PARAMS_TX2LN0_PORT4 0x16B0AC
> +#define MG_TX_LINK_PARAMS_TX2LN1_PORT4 0x16B4AC
> +#define MG_TX2_LINK_PARAMS(port, ln) \
> + MG_PHY_PORT_LN(port, ln, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
> + MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
> + MG_TX_LINK_PARAMS_TX2LN1_PORT1)
> #define CRI_USE_FS32 (1 << 5)
>
> -#define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT1 0x16814
> C
> -#define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT1 0x16854
> C
> -#define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT2 0x16914
> C
> -#define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT2 0x16954
> C
> -#define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT3 0x16A14
> C
> -#define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT3 0x16A54
> C
> -#define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT4 0x16B14
> C
> -#define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT4 0x16B54
> C
> -#define ICL_PORT_MG_TX1_PISO_READLOAD(port, ln) \
> - _ICL_MG_PHY_PORT_LN(port, ln,
> _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
> - _ICL_MG_TX_PISO_READLOAD_TX1LN
> 0_PORT2, \
> - _ICL_MG_TX_PISO_READLOAD_TX1LN
> 1_PORT1)
> -
> -#define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT1 0x1680C
> C
> -#define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT1 0x1684C
> C
> -#define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT2 0x1690C
> C
> -#define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT2 0x1694C
> C
> -#define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT3 0x16A0C
> C
> -#define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT3 0x16A4C
> C
> -#define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT4 0x16B0C
> C
> -#define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT4 0x16B4C
> C
> -#define ICL_PORT_MG_TX2_PISO_READLOAD(port, ln) \
> - _ICL_MG_PHY_PORT_LN(port, ln,
> _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
> - _ICL_MG_TX_PISO_READLOAD_TX2LN
> 0_PORT2, \
> - _ICL_MG_TX_PISO_READLOAD_TX2LN
> 1_PORT1)
> +#define MG_TX_PISO_READLOAD_TX1LN0_PORT1 0x16814C
> +#define MG_TX_PISO_READLOAD_TX1LN1_PORT1 0x16854C
> +#define MG_TX_PISO_READLOAD_TX1LN0_PORT2 0x16914C
> +#define MG_TX_PISO_READLOAD_TX1LN1_PORT2 0x16954C
> +#define MG_TX_PISO_READLOAD_TX1LN0_PORT3 0x16A14C
> +#define MG_TX_PISO_READLOAD_TX1LN1_PORT3 0x16A54C
> +#define MG_TX_PISO_READLOAD_TX1LN0_PORT4 0x16B14C
> +#define MG_TX_PISO_READLOAD_TX1LN1_PORT4 0x16B54C
> +#define MG_TX1_PISO_READLOAD(port, ln) \
> + MG_PHY_PORT_LN(port, ln, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
> + MG_TX_PISO_READLOAD_TX1LN0_PORT2, \
> + MG_TX_PISO_READLOAD_TX1LN1_PORT1)
> +
> +#define MG_TX_PISO_READLOAD_TX2LN0_PORT1 0x1680CC
> +#define MG_TX_PISO_READLOAD_TX2LN1_PORT1 0x1684CC
> +#define MG_TX_PISO_READLOAD_TX2LN0_PORT2 0x1690CC
> +#define MG_TX_PISO_READLOAD_TX2LN1_PORT2 0x1694CC
> +#define MG_TX_PISO_READLOAD_TX2LN0_PORT3 0x16A0CC
> +#define MG_TX_PISO_READLOAD_TX2LN1_PORT3 0x16A4CC
> +#define MG_TX_PISO_READLOAD_TX2LN0_PORT4 0x16B0CC
> +#define MG_TX_PISO_READLOAD_TX2LN1_PORT4 0x16B4CC
> +#define MG_TX2_PISO_READLOAD(port, ln) \
> + MG_PHY_PORT_LN(port, ln, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
> + MG_TX_PISO_READLOAD_TX2LN0_PORT2, \
> + MG_TX_PISO_READLOAD_TX2LN1_PORT1)
> #define CRI_CALCINIT (1 << 1)
>
> -#define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT1 0x168148
> -#define _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT1 0x168548
> -#define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT2 0x169148
> -#define _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT2 0x169548
> -#define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT3 0x16A148
> -#define _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT3 0x16A548
> -#define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT4 0x16B148
> -#define _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT4 0x16B548
> -#define ICL_PORT_MG_TX1_SWINGCTRL(port, ln) \
> - _ICL_MG_PHY_PORT_LN(port, ln,
> _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT1, \
> - _ICL_MG_TX_SWINGCTRL_TX1LN0_PO
> RT2, \
> - _ICL_MG_TX_SWINGCTRL_TX1LN1_PO
> RT1)
> -
> -#define _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT1 0x1680C8
> -#define _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT1 0x1684C8
> -#define _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT2 0x1690C8
> -#define _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT2 0x1694C8
> -#define _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT3 0x16A0C8
> -#define _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT3 0x16A4C8
> -#define _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT4 0x16B0C8
> -#define _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT4 0x16B4C8
> -#define ICL_PORT_MG_TX2_SWINGCTRL(port, ln) \
> - _ICL_MG_PHY_PORT_LN(port, ln,
> _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT1, \
> - _ICL_MG_TX_SWINGCTRL_TX2LN0_PO
> RT2, \
> - _ICL_MG_TX_SWINGCTRL_TX2LN1_PO
> RT1)
> +#define MG_TX_SWINGCTRL_TX1LN0_PORT1 0x168148
> +#define MG_TX_SWINGCTRL_TX1LN1_PORT1 0x168548
> +#define MG_TX_SWINGCTRL_TX1LN0_PORT2 0x169148
> +#define MG_TX_SWINGCTRL_TX1LN1_PORT2 0x169548
> +#define MG_TX_SWINGCTRL_TX1LN0_PORT3 0x16A148
> +#define MG_TX_SWINGCTRL_TX1LN1_PORT3 0x16A548
> +#define MG_TX_SWINGCTRL_TX1LN0_PORT4 0x16B148
> +#define MG_TX_SWINGCTRL_TX1LN1_PORT4 0x16B548
> +#define MG_TX1_SWINGCTRL(port, ln) \
> + MG_PHY_PORT_LN(port, ln, MG_TX_SWINGCTRL_TX1LN0_PORT1, \
> + MG_TX_SWINGCTRL_TX1LN0_PORT2, \
> + MG_TX_SWINGCTRL_TX1LN1_PORT1)
> +
> +#define MG_TX_SWINGCTRL_TX2LN0_PORT1 0x1680C8
> +#define MG_TX_SWINGCTRL_TX2LN1_PORT1 0x1684C8
> +#define MG_TX_SWINGCTRL_TX2LN0_PORT2 0x1690C8
> +#define MG_TX_SWINGCTRL_TX2LN1_PORT2 0x1694C8
> +#define MG_TX_SWINGCTRL_TX2LN0_PORT3 0x16A0C8
> +#define MG_TX_SWINGCTRL_TX2LN1_PORT3 0x16A4C8
> +#define MG_TX_SWINGCTRL_TX2LN0_PORT4 0x16B0C8
> +#define MG_TX_SWINGCTRL_TX2LN1_PORT4 0x16B4C8
> +#define MG_TX2_SWINGCTRL(port, ln) \
> + MG_PHY_PORT_LN(port, ln, MG_TX_SWINGCTRL_TX2LN0_PORT1, \
> + MG_TX_SWINGCTRL_TX2LN0_PORT2, \
> + MG_TX_SWINGCTRL_TX2LN1_PORT1)
> #define CRI_TXDEEMPH_OVERRIDE_17_12(x) ((x)
> << 0)
> #define CRI_TXDEEMPH_OVERRIDE_17_12_MASK (0x3F << 0)
>
> -#define _ICL_MG_TX_DRVCTRL_TX1LN0_PORT1 0x168
> 144
> -#define _ICL_MG_TX_DRVCTRL_TX1LN1_PORT1 0x168
> 544
> -#define _ICL_MG_TX_DRVCTRL_TX1LN0_PORT2 0x169
> 144
> -#define _ICL_MG_TX_DRVCTRL_TX1LN1_PORT2 0x169
> 544
> -#define _ICL_MG_TX_DRVCTRL_TX1LN0_PORT3 0x16A
> 144
> -#define _ICL_MG_TX_DRVCTRL_TX1LN1_PORT3 0x16A
> 544
> -#define _ICL_MG_TX_DRVCTRL_TX1LN0_PORT4 0x16B
> 144
> -#define _ICL_MG_TX_DRVCTRL_TX1LN1_PORT4 0x16B
> 544
> -#define ICL_PORT_MG_TX1_DRVCTRL(port, ln) \
> - _ICL_MG_PHY_PORT_LN(port, ln,
> _ICL_MG_TX_DRVCTRL_TX1LN0_PORT1, \
> - _ICL_MG_TX_DRVCTRL_TX1LN0_PORT
> 2, \
> - _ICL_MG_TX_DRVCTRL_TX1LN1_PORT
> 1)
> -
> -#define _ICL_MG_TX_DRVCTRL_TX2LN0_PORT1 0x168
> 0C4
> -#define _ICL_MG_TX_DRVCTRL_TX2LN1_PORT1 0x168
> 4C4
> -#define _ICL_MG_TX_DRVCTRL_TX2LN0_PORT2 0x169
> 0C4
> -#define _ICL_MG_TX_DRVCTRL_TX2LN1_PORT2 0x169
> 4C4
> -#define _ICL_MG_TX_DRVCTRL_TX2LN0_PORT3 0x16A
> 0C4
> -#define _ICL_MG_TX_DRVCTRL_TX2LN1_PORT3 0x16A
> 4C4
> -#define _ICL_MG_TX_DRVCTRL_TX2LN0_PORT4 0x16B
> 0C4
> -#define _ICL_MG_TX_DRVCTRL_TX2LN1_PORT4 0x16B
> 4C4
> -#define ICL_PORT_MG_TX2_DRVCTRL(port, ln) \
> - _ICL_MG_PHY_PORT_LN(port, ln,
> _ICL_MG_TX_DRVCTRL_TX2LN0_PORT1, \
> - _ICL_MG_TX_DRVCTRL_TX2LN0_PORT
> 2, \
> - _ICL_MG_TX_DRVCTRL_TX2LN1_PORT
> 1)
> +#define MG_TX_DRVCTRL_TX1LN0_TXPORT1 0x168144
> +#define MG_TX_DRVCTRL_TX1LN1_TXPORT1 0x168544
> +#define MG_TX_DRVCTRL_TX1LN0_TXPORT2 0x169144
> +#define MG_TX_DRVCTRL_TX1LN1_TXPORT2 0x169544
> +#define MG_TX_DRVCTRL_TX1LN0_TXPORT3 0x16A144
> +#define MG_TX_DRVCTRL_TX1LN1_TXPORT3 0x16A544
> +#define MG_TX_DRVCTRL_TX1LN0_TXPORT4 0x16B144
> +#define MG_TX_DRVCTRL_TX1LN1_TXPORT4 0x16B544
> +#define MG_TX1_DRVCTRL(port, ln) \
> + MG_PHY_PORT_LN(port, ln, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \
> + MG_TX_DRVCTRL_TX1LN0_TXPORT2, \
> + MG_TX_DRVCTRL_TX1LN1_TXPORT1)
> +
> +#define MG_TX_DRVCTRL_TX2LN0_PORT1 0x1680C4
> +#define MG_TX_DRVCTRL_TX2LN1_PORT1 0x1684C4
> +#define MG_TX_DRVCTRL_TX2LN0_PORT2 0x1690C4
> +#define MG_TX_DRVCTRL_TX2LN1_PORT2 0x1694C4
> +#define MG_TX_DRVCTRL_TX2LN0_PORT3 0x16A0C4
> +#define MG_TX_DRVCTRL_TX2LN1_PORT3 0x16A4C4
> +#define MG_TX_DRVCTRL_TX2LN0_PORT4 0x16B0C4
> +#define MG_TX_DRVCTRL_TX2LN1_PORT4 0x16B4C4
> +#define MG_TX2_DRVCTRL(port, ln) \
> + MG_PHY_PORT_LN(port, ln, MG_TX_DRVCTRL_TX2LN0_PORT1, \
> + MG_TX_DRVCTRL_TX2LN0_PORT2, \
> + MG_TX_DRVCTRL_TX2LN1_PORT1)
> #define CRI_TXDEEMPH_OVERRIDE_11_6(x) ((x) <<
> 24)
> #define CRI_TXDEEMPH_OVERRIDE_11_6_MASK (0x3F
> << 24)
> #define CRI_TXDEEMPH_OVERRIDE_EN (1 << 22)
> #define CRI_TXDEEMPH_OVERRIDE_5_0(x) ((x) <<
> 16)
> #define CRI_TXDEEMPH_OVERRIDE_5_0_MASK (0x3F
> << 16)
> +#define CRI_LOADGEN_SEL(x) ((x) <<
> 12)
> +#define CRI_LOADGEN_SEL_MASK (0x3 <<
> 12)
Since you're drive-by fixing things you may as well add the two
additional spaces required for bit macros (between #define and the
macro name), and then also add the spaces in the new registers defined
later. This applies to the registers above too.
> +
> +#define MG_CLKHUB_LN0_PORT1 0x16839C
> +#define MG_CLKHUB_LN1_PORT1 0x16879C
> +#define MG_CLKHUB_LN0_PORT2 0x16939C
> +#define MG_CLKHUB_LN1_PORT2 0x16979C
> +#define MG_CLKHUB_LN0_PORT3 0x16A39C
> +#define MG_CLKHUB_LN1_PORT3 0x16A79C
> +#define MG_CLKHUB_LN0_PORT4 0x16B39C
> +#define MG_CLKHUB_LN1_PORT4 0x16B79C
> +#define MG_CLKHUB(port, ln) \
> + MG_PHY_PORT_LN(port, ln, MG_CLKHUB_LN0_PORT1, \
> + MG_CLKHUB_LN0_PORT2, \
> + MG_CLKHUB_LN1_PORT1)
> +#define CFG_LOW_RATE_LKREN_EN (1 <<
> 11)
> +
> +#define MG_TX_DCC_TX1LN0_PORT1 0x168110
> +#define MG_TX_DCC_TX1LN1_PORT1 0x168510
> +#define MG_TX_DCC_TX1LNO_PORT2 0x169110
Here and in many cases below: s/O/0/
> +#define MG_TX_DCC_TX1LN1_PORT2 0x169510
> +#define MG_TX_DCC_TX1LNO_PORT3 0x16A110
> +#define MG_TX_DCC_TX1LN1_PORT3 0x16A510
> +#define MG_TX_DCC_TX1LNO_PORT4 0x16B110
> +#define MG_TX_DCC_TX1LN1_PORT4 0x16B510
> +#define MG_TX1_DCC(port, ln) \
> + MG_PHY_PORT_LN(port, ln, MG_TX_DCC_TX1LN0_PORT1, \
> + MG_TX_DCC_TX1LNO_PORT2, \
> + MG_TX_DCC_TX1LN1_PORT1)
> +#define MG_TX_DCC_TX2LN0_PORT1 0x168090
> +#define MG_TX_DCC_TX2LN1_PORT1 0x168490
> +#define MG_TX_DCC_TX2LNO_PORT2 0x169090
> +#define MG_TX_DCC_TX2LN1_PORT2 0x169490
> +#define MG_TX_DCC_TX2LNO_PORT3 0x16A090
> +#define MG_TX_DCC_TX2LN1_PORT3 0x16A490
> +#define MG_TX_DCC_TX2LNO_PORT4 0x16B090
> +#define MG_TX_DCC_TX2LN1_PORT4 0x16B490
> +#define MG_TX2_DCC(port, ln) \
> + MG_PHY_PORT_LN(port, ln, MG_TX_DCC_TX2LN0_PORT1, \
> + MG_TX_DCC_TX2LNO_PORT2, \
> + MG_TX_DCC_TX2LN1_PORT1)
> +#define CFG_AMI_CK_DIV_OVERRIDE_EN (1 << 24)
Definitions for bit 24 should go below definitions for bit 25. See the
big comment at the top of the file.
Otherwise, looks good.
> +#define CFG_AMI_CK_DIV_OVERRIDE_VAL(x) ((x) << 25)
> +#define CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK (0x3 << 25)
>
> /* The spec defines this only for BXT PHY0, but lets assume that
> this
> * would exist for PHY1 too if it had a second channel.
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^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 1/2] drm/i915/icl: Add remaining registers and bitfields for MG PHY DDI
2018-07-13 0:00 ` Paulo Zanoni
@ 2018-07-13 18:44 ` Manasi Navare
0 siblings, 0 replies; 15+ messages in thread
From: Manasi Navare @ 2018-07-13 18:44 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
Thanks for the review comments.
On Thu, Jul 12, 2018 at 05:00:42PM -0700, Paulo Zanoni wrote:
> Em Qui, 2018-06-28 às 15:35 -0700, Manasi Navare escreveu:
> > This patch adds the remaining register definitions and bit fields
> > required for MG PHy DDI buffer initializations and voltage
> > swing programming for MG PHy DDI ports.
> >
> > While at it this patch also fixes the naming for previously defined
> > MG PHY registers in original commit id (c92f47b5ec977a "drm/i915/icl:
> > Add register defs for voltage swing sequences for MG PHY DDI").
> > Since the MG PHY registers are first defined in ICL platform, there
> > is no need for _ICL prefix.
>
> IMHO drive-by "do this other trivial thing"s are fine when it's only 1
> or 2 small chunks affected. In this case it's half of the patch, so I
> would prefer having it in a separate patch. But let's leave it as-is
> here since at least the registers being touched are not used.
>
> More below.
>
> >
> > v2:
> > * Change the MG_TX_DRVCTL registers names to match the spec (Anusha)
> >
> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > Cc: James Ausmus <james.ausmus@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 246 +++++++++++++++++++++++-------
> > ----------
> > 1 file changed, 145 insertions(+), 101 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index c30cfcd..6119acc 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1872,121 +1872,165 @@ enum i915_power_well_id {
> > #define N_SCALAR(x) ((x) << 24)
> > #define N_SCALAR_MASK (0x7F << 24)
> >
> > -#define _ICL_MG_PHY_PORT_LN(port, ln, ln0p1, ln0p2, ln1p1) \
> > +#define MG_PHY_PORT_LN(port, ln, ln0p1, ln0p2, ln1p1) \
> > _MMIO(_PORT((port) - PORT_C, ln0p1, ln0p2) + (ln) * ((ln1p1)
> > - (ln0p1)))
> >
> > -#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT1 0x16812C
> > -#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT1 0x16852C
> > -#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT2 0x16912C
> > -#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT2 0x16952C
> > -#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT3 0x16A12C
> > -#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT3 0x16A52C
> > -#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT4 0x16B12C
> > -#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT4 0x16B52C
> > -#define ICL_PORT_MG_TX1_LINK_PARAMS(port, ln) \
> > - _ICL_MG_PHY_PORT_LN(port, ln,
> > _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
> > - _ICL_MG_TX_LINK_PARAMS_TX1LN0_
> > PORT2, \
> > - _ICL_MG_TX_LINK_PARAMS_TX1LN1_
> > PORT1)
> > -
> > -#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT1 0x1680AC
> > -#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT1 0x1684AC
> > -#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT2 0x1690AC
> > -#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT2 0x1694AC
> > -#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT3 0x16A0AC
> > -#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT3 0x16A4AC
> > -#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT4 0x16B0AC
> > -#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT4 0x16B4AC
> > -#define ICL_PORT_MG_TX2_LINK_PARAMS(port, ln) \
> > - _ICL_MG_PHY_PORT_LN(port, ln,
> > _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
> > - _ICL_MG_TX_LINK_PARAMS_TX2LN0_
> > PORT2, \
> > - _ICL_MG_TX_LINK_PARAMS_TX2LN1_
> > PORT1)
> > +#define MG_TX_LINK_PARAMS_TX1LN0_PORT1 0x16812C
> > +#define MG_TX_LINK_PARAMS_TX1LN1_PORT1 0x16852C
> > +#define MG_TX_LINK_PARAMS_TX1LN0_PORT2 0x16912C
> > +#define MG_TX_LINK_PARAMS_TX1LN1_PORT2 0x16952C
> > +#define MG_TX_LINK_PARAMS_TX1LN0_PORT3 0x16A12C
> > +#define MG_TX_LINK_PARAMS_TX1LN1_PORT3 0x16A52C
> > +#define MG_TX_LINK_PARAMS_TX1LN0_PORT4 0x16B12C
> > +#define _MG_TX_LINK_PARAMS_TX1LN1_PORT4 0x16B52C
>
> You left an underline on the line above.
Will take care of this in the next revision.
>
>
>
> > +#define MG_TX1_LINK_PARAMS(port, ln) \
> > + MG_PHY_PORT_LN(port, ln, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
> > + MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
> > + MG_TX_LINK_PARAMS_TX1LN1_PORT1)
> > +
> > +#define MG_TX_LINK_PARAMS_TX2LN0_PORT1 0x1680AC
> > +#define MG_TX_LINK_PARAMS_TX2LN1_PORT1 0x1684AC
> > +#define MG_TX_LINK_PARAMS_TX2LN0_PORT2 0x1690AC
> > +#define MG_TX_LINK_PARAMS_TX2LN1_PORT2 0x1694AC
> > +#define MG_TX_LINK_PARAMS_TX2LN0_PORT3 0x16A0AC
> > +#define MG_TX_LINK_PARAMS_TX2LN1_PORT3 0x16A4AC
> > +#define MG_TX_LINK_PARAMS_TX2LN0_PORT4 0x16B0AC
> > +#define MG_TX_LINK_PARAMS_TX2LN1_PORT4 0x16B4AC
> > +#define MG_TX2_LINK_PARAMS(port, ln) \
> > + MG_PHY_PORT_LN(port, ln, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
> > + MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
> > + MG_TX_LINK_PARAMS_TX2LN1_PORT1)
> > #define CRI_USE_FS32 (1 << 5)
> >
> > -#define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT1 0x16814
> > C
> > -#define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT1 0x16854
> > C
> > -#define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT2 0x16914
> > C
> > -#define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT2 0x16954
> > C
> > -#define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT3 0x16A14
> > C
> > -#define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT3 0x16A54
> > C
> > -#define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT4 0x16B14
> > C
> > -#define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT4 0x16B54
> > C
> > -#define ICL_PORT_MG_TX1_PISO_READLOAD(port, ln) \
> > - _ICL_MG_PHY_PORT_LN(port, ln,
> > _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
> > - _ICL_MG_TX_PISO_READLOAD_TX1LN
> > 0_PORT2, \
> > - _ICL_MG_TX_PISO_READLOAD_TX1LN
> > 1_PORT1)
> > -
> > -#define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT1 0x1680C
> > C
> > -#define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT1 0x1684C
> > C
> > -#define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT2 0x1690C
> > C
> > -#define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT2 0x1694C
> > C
> > -#define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT3 0x16A0C
> > C
> > -#define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT3 0x16A4C
> > C
> > -#define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT4 0x16B0C
> > C
> > -#define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT4 0x16B4C
> > C
> > -#define ICL_PORT_MG_TX2_PISO_READLOAD(port, ln) \
> > - _ICL_MG_PHY_PORT_LN(port, ln,
> > _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
> > - _ICL_MG_TX_PISO_READLOAD_TX2LN
> > 0_PORT2, \
> > - _ICL_MG_TX_PISO_READLOAD_TX2LN
> > 1_PORT1)
> > +#define MG_TX_PISO_READLOAD_TX1LN0_PORT1 0x16814C
> > +#define MG_TX_PISO_READLOAD_TX1LN1_PORT1 0x16854C
> > +#define MG_TX_PISO_READLOAD_TX1LN0_PORT2 0x16914C
> > +#define MG_TX_PISO_READLOAD_TX1LN1_PORT2 0x16954C
> > +#define MG_TX_PISO_READLOAD_TX1LN0_PORT3 0x16A14C
> > +#define MG_TX_PISO_READLOAD_TX1LN1_PORT3 0x16A54C
> > +#define MG_TX_PISO_READLOAD_TX1LN0_PORT4 0x16B14C
> > +#define MG_TX_PISO_READLOAD_TX1LN1_PORT4 0x16B54C
> > +#define MG_TX1_PISO_READLOAD(port, ln) \
> > + MG_PHY_PORT_LN(port, ln, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
> > + MG_TX_PISO_READLOAD_TX1LN0_PORT2, \
> > + MG_TX_PISO_READLOAD_TX1LN1_PORT1)
> > +
> > +#define MG_TX_PISO_READLOAD_TX2LN0_PORT1 0x1680CC
> > +#define MG_TX_PISO_READLOAD_TX2LN1_PORT1 0x1684CC
> > +#define MG_TX_PISO_READLOAD_TX2LN0_PORT2 0x1690CC
> > +#define MG_TX_PISO_READLOAD_TX2LN1_PORT2 0x1694CC
> > +#define MG_TX_PISO_READLOAD_TX2LN0_PORT3 0x16A0CC
> > +#define MG_TX_PISO_READLOAD_TX2LN1_PORT3 0x16A4CC
> > +#define MG_TX_PISO_READLOAD_TX2LN0_PORT4 0x16B0CC
> > +#define MG_TX_PISO_READLOAD_TX2LN1_PORT4 0x16B4CC
> > +#define MG_TX2_PISO_READLOAD(port, ln) \
> > + MG_PHY_PORT_LN(port, ln, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
> > + MG_TX_PISO_READLOAD_TX2LN0_PORT2, \
> > + MG_TX_PISO_READLOAD_TX2LN1_PORT1)
> > #define CRI_CALCINIT (1 << 1)
> >
> > -#define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT1 0x168148
> > -#define _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT1 0x168548
> > -#define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT2 0x169148
> > -#define _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT2 0x169548
> > -#define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT3 0x16A148
> > -#define _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT3 0x16A548
> > -#define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT4 0x16B148
> > -#define _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT4 0x16B548
> > -#define ICL_PORT_MG_TX1_SWINGCTRL(port, ln) \
> > - _ICL_MG_PHY_PORT_LN(port, ln,
> > _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT1, \
> > - _ICL_MG_TX_SWINGCTRL_TX1LN0_PO
> > RT2, \
> > - _ICL_MG_TX_SWINGCTRL_TX1LN1_PO
> > RT1)
> > -
> > -#define _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT1 0x1680C8
> > -#define _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT1 0x1684C8
> > -#define _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT2 0x1690C8
> > -#define _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT2 0x1694C8
> > -#define _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT3 0x16A0C8
> > -#define _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT3 0x16A4C8
> > -#define _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT4 0x16B0C8
> > -#define _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT4 0x16B4C8
> > -#define ICL_PORT_MG_TX2_SWINGCTRL(port, ln) \
> > - _ICL_MG_PHY_PORT_LN(port, ln,
> > _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT1, \
> > - _ICL_MG_TX_SWINGCTRL_TX2LN0_PO
> > RT2, \
> > - _ICL_MG_TX_SWINGCTRL_TX2LN1_PO
> > RT1)
> > +#define MG_TX_SWINGCTRL_TX1LN0_PORT1 0x168148
> > +#define MG_TX_SWINGCTRL_TX1LN1_PORT1 0x168548
> > +#define MG_TX_SWINGCTRL_TX1LN0_PORT2 0x169148
> > +#define MG_TX_SWINGCTRL_TX1LN1_PORT2 0x169548
> > +#define MG_TX_SWINGCTRL_TX1LN0_PORT3 0x16A148
> > +#define MG_TX_SWINGCTRL_TX1LN1_PORT3 0x16A548
> > +#define MG_TX_SWINGCTRL_TX1LN0_PORT4 0x16B148
> > +#define MG_TX_SWINGCTRL_TX1LN1_PORT4 0x16B548
> > +#define MG_TX1_SWINGCTRL(port, ln) \
> > + MG_PHY_PORT_LN(port, ln, MG_TX_SWINGCTRL_TX1LN0_PORT1, \
> > + MG_TX_SWINGCTRL_TX1LN0_PORT2, \
> > + MG_TX_SWINGCTRL_TX1LN1_PORT1)
> > +
> > +#define MG_TX_SWINGCTRL_TX2LN0_PORT1 0x1680C8
> > +#define MG_TX_SWINGCTRL_TX2LN1_PORT1 0x1684C8
> > +#define MG_TX_SWINGCTRL_TX2LN0_PORT2 0x1690C8
> > +#define MG_TX_SWINGCTRL_TX2LN1_PORT2 0x1694C8
> > +#define MG_TX_SWINGCTRL_TX2LN0_PORT3 0x16A0C8
> > +#define MG_TX_SWINGCTRL_TX2LN1_PORT3 0x16A4C8
> > +#define MG_TX_SWINGCTRL_TX2LN0_PORT4 0x16B0C8
> > +#define MG_TX_SWINGCTRL_TX2LN1_PORT4 0x16B4C8
> > +#define MG_TX2_SWINGCTRL(port, ln) \
> > + MG_PHY_PORT_LN(port, ln, MG_TX_SWINGCTRL_TX2LN0_PORT1, \
> > + MG_TX_SWINGCTRL_TX2LN0_PORT2, \
> > + MG_TX_SWINGCTRL_TX2LN1_PORT1)
> > #define CRI_TXDEEMPH_OVERRIDE_17_12(x) ((x)
> > << 0)
> > #define CRI_TXDEEMPH_OVERRIDE_17_12_MASK (0x3F << 0)
> >
> > -#define _ICL_MG_TX_DRVCTRL_TX1LN0_PORT1 0x168
> > 144
> > -#define _ICL_MG_TX_DRVCTRL_TX1LN1_PORT1 0x168
> > 544
> > -#define _ICL_MG_TX_DRVCTRL_TX1LN0_PORT2 0x169
> > 144
> > -#define _ICL_MG_TX_DRVCTRL_TX1LN1_PORT2 0x169
> > 544
> > -#define _ICL_MG_TX_DRVCTRL_TX1LN0_PORT3 0x16A
> > 144
> > -#define _ICL_MG_TX_DRVCTRL_TX1LN1_PORT3 0x16A
> > 544
> > -#define _ICL_MG_TX_DRVCTRL_TX1LN0_PORT4 0x16B
> > 144
> > -#define _ICL_MG_TX_DRVCTRL_TX1LN1_PORT4 0x16B
> > 544
> > -#define ICL_PORT_MG_TX1_DRVCTRL(port, ln) \
> > - _ICL_MG_PHY_PORT_LN(port, ln,
> > _ICL_MG_TX_DRVCTRL_TX1LN0_PORT1, \
> > - _ICL_MG_TX_DRVCTRL_TX1LN0_PORT
> > 2, \
> > - _ICL_MG_TX_DRVCTRL_TX1LN1_PORT
> > 1)
> > -
> > -#define _ICL_MG_TX_DRVCTRL_TX2LN0_PORT1 0x168
> > 0C4
> > -#define _ICL_MG_TX_DRVCTRL_TX2LN1_PORT1 0x168
> > 4C4
> > -#define _ICL_MG_TX_DRVCTRL_TX2LN0_PORT2 0x169
> > 0C4
> > -#define _ICL_MG_TX_DRVCTRL_TX2LN1_PORT2 0x169
> > 4C4
> > -#define _ICL_MG_TX_DRVCTRL_TX2LN0_PORT3 0x16A
> > 0C4
> > -#define _ICL_MG_TX_DRVCTRL_TX2LN1_PORT3 0x16A
> > 4C4
> > -#define _ICL_MG_TX_DRVCTRL_TX2LN0_PORT4 0x16B
> > 0C4
> > -#define _ICL_MG_TX_DRVCTRL_TX2LN1_PORT4 0x16B
> > 4C4
> > -#define ICL_PORT_MG_TX2_DRVCTRL(port, ln) \
> > - _ICL_MG_PHY_PORT_LN(port, ln,
> > _ICL_MG_TX_DRVCTRL_TX2LN0_PORT1, \
> > - _ICL_MG_TX_DRVCTRL_TX2LN0_PORT
> > 2, \
> > - _ICL_MG_TX_DRVCTRL_TX2LN1_PORT
> > 1)
> > +#define MG_TX_DRVCTRL_TX1LN0_TXPORT1 0x168144
> > +#define MG_TX_DRVCTRL_TX1LN1_TXPORT1 0x168544
> > +#define MG_TX_DRVCTRL_TX1LN0_TXPORT2 0x169144
> > +#define MG_TX_DRVCTRL_TX1LN1_TXPORT2 0x169544
> > +#define MG_TX_DRVCTRL_TX1LN0_TXPORT3 0x16A144
> > +#define MG_TX_DRVCTRL_TX1LN1_TXPORT3 0x16A544
> > +#define MG_TX_DRVCTRL_TX1LN0_TXPORT4 0x16B144
> > +#define MG_TX_DRVCTRL_TX1LN1_TXPORT4 0x16B544
> > +#define MG_TX1_DRVCTRL(port, ln) \
> > + MG_PHY_PORT_LN(port, ln, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \
> > + MG_TX_DRVCTRL_TX1LN0_TXPORT2, \
> > + MG_TX_DRVCTRL_TX1LN1_TXPORT1)
> > +
> > +#define MG_TX_DRVCTRL_TX2LN0_PORT1 0x1680C4
> > +#define MG_TX_DRVCTRL_TX2LN1_PORT1 0x1684C4
> > +#define MG_TX_DRVCTRL_TX2LN0_PORT2 0x1690C4
> > +#define MG_TX_DRVCTRL_TX2LN1_PORT2 0x1694C4
> > +#define MG_TX_DRVCTRL_TX2LN0_PORT3 0x16A0C4
> > +#define MG_TX_DRVCTRL_TX2LN1_PORT3 0x16A4C4
> > +#define MG_TX_DRVCTRL_TX2LN0_PORT4 0x16B0C4
> > +#define MG_TX_DRVCTRL_TX2LN1_PORT4 0x16B4C4
> > +#define MG_TX2_DRVCTRL(port, ln) \
> > + MG_PHY_PORT_LN(port, ln, MG_TX_DRVCTRL_TX2LN0_PORT1, \
> > + MG_TX_DRVCTRL_TX2LN0_PORT2, \
> > + MG_TX_DRVCTRL_TX2LN1_PORT1)
> > #define CRI_TXDEEMPH_OVERRIDE_11_6(x) ((x) <<
> > 24)
> > #define CRI_TXDEEMPH_OVERRIDE_11_6_MASK (0x3F
> > << 24)
> > #define CRI_TXDEEMPH_OVERRIDE_EN (1 << 22)
> > #define CRI_TXDEEMPH_OVERRIDE_5_0(x) ((x) <<
> > 16)
> > #define CRI_TXDEEMPH_OVERRIDE_5_0_MASK (0x3F
> > << 16)
> > +#define CRI_LOADGEN_SEL(x) ((x) <<
> > 12)
> > +#define CRI_LOADGEN_SEL_MASK (0x3 <<
> > 12)
>
> Since you're drive-by fixing things you may as well add the two
> additional spaces required for bit macros (between #define and the
> macro name), and then also add the spaces in the new registers defined
> later. This applies to the registers above too.
>
Yes I agree, will add the spaces for the MASK #defines.
>
> > +
> > +#define MG_CLKHUB_LN0_PORT1 0x16839C
> > +#define MG_CLKHUB_LN1_PORT1 0x16879C
> > +#define MG_CLKHUB_LN0_PORT2 0x16939C
> > +#define MG_CLKHUB_LN1_PORT2 0x16979C
> > +#define MG_CLKHUB_LN0_PORT3 0x16A39C
> > +#define MG_CLKHUB_LN1_PORT3 0x16A79C
> > +#define MG_CLKHUB_LN0_PORT4 0x16B39C
> > +#define MG_CLKHUB_LN1_PORT4 0x16B79C
> > +#define MG_CLKHUB(port, ln) \
> > + MG_PHY_PORT_LN(port, ln, MG_CLKHUB_LN0_PORT1, \
> > + MG_CLKHUB_LN0_PORT2, \
> > + MG_CLKHUB_LN1_PORT1)
> > +#define CFG_LOW_RATE_LKREN_EN (1 <<
> > 11)
> > +
> > +#define MG_TX_DCC_TX1LN0_PORT1 0x168110
> > +#define MG_TX_DCC_TX1LN1_PORT1 0x168510
> > +#define MG_TX_DCC_TX1LNO_PORT2 0x169110
>
> Here and in many cases below: s/O/0/
Thanks for pointing this out, will fix this.
>
>
> > +#define MG_TX_DCC_TX1LN1_PORT2 0x169510
> > +#define MG_TX_DCC_TX1LNO_PORT3 0x16A110
> > +#define MG_TX_DCC_TX1LN1_PORT3 0x16A510
> > +#define MG_TX_DCC_TX1LNO_PORT4 0x16B110
> > +#define MG_TX_DCC_TX1LN1_PORT4 0x16B510
> > +#define MG_TX1_DCC(port, ln) \
> > + MG_PHY_PORT_LN(port, ln, MG_TX_DCC_TX1LN0_PORT1, \
> > + MG_TX_DCC_TX1LNO_PORT2, \
> > + MG_TX_DCC_TX1LN1_PORT1)
> > +#define MG_TX_DCC_TX2LN0_PORT1 0x168090
> > +#define MG_TX_DCC_TX2LN1_PORT1 0x168490
> > +#define MG_TX_DCC_TX2LNO_PORT2 0x169090
> > +#define MG_TX_DCC_TX2LN1_PORT2 0x169490
> > +#define MG_TX_DCC_TX2LNO_PORT3 0x16A090
> > +#define MG_TX_DCC_TX2LN1_PORT3 0x16A490
> > +#define MG_TX_DCC_TX2LNO_PORT4 0x16B090
> > +#define MG_TX_DCC_TX2LN1_PORT4 0x16B490
> > +#define MG_TX2_DCC(port, ln) \
> > + MG_PHY_PORT_LN(port, ln, MG_TX_DCC_TX2LN0_PORT1, \
> > + MG_TX_DCC_TX2LNO_PORT2, \
> > + MG_TX_DCC_TX2LN1_PORT1)
> > +#define CFG_AMI_CK_DIV_OVERRIDE_EN (1 << 24)
>
> Definitions for bit 24 should go below definitions for bit 25. See the
> big comment at the top of the file.
>
Cool, will shuffle the order or bit macros.
Manasi
> Otherwise, looks good.
>
>
> > +#define CFG_AMI_CK_DIV_OVERRIDE_VAL(x) ((x) << 25)
> > +#define CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK (0x3 << 25)
> >
> > /* The spec defines this only for BXT PHY0, but lets assume that
> > this
> > * would exist for PHY1 too if it had a second channel.
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^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v3] drm/i915/icl: Add remaining registers and bitfields for MG PHY DDI
2018-06-28 22:35 [PATCH v2 1/2] drm/i915/icl: Add remaining registers and bitfields for MG PHY DDI Manasi Navare
` (7 preceding siblings ...)
2018-07-13 0:00 ` Paulo Zanoni
@ 2018-07-13 19:43 ` Manasi Navare
2018-07-16 21:01 ` Paulo Zanoni
2018-07-13 19:50 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3] drm/i915/icl: Add remaining registers and bitfields for MG PHY DDI (rev3) Patchwork
2018-07-13 20:06 ` ✓ Fi.CI.BAT: success " Patchwork
10 siblings, 1 reply; 15+ messages in thread
From: Manasi Navare @ 2018-07-13 19:43 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
This patch adds the remaining register definitions and bit fields
required for MG PHy DDI buffer initializations and voltage
swing programming for MG PHy DDI ports.
While at it this patch also fixes the naming for previously defined
MG PHY registers in original commit id (c92f47b5ec977a "drm/i915/icl:
Add register defs for voltage swing sequences for MG PHY DDI").
Since the MG PHY registers are first defined in ICL platform, there
is no need for _ICL prefix.
v3:
* Fix register names, add spaces for MASK defines, correct the order
of #defines (Paulo)
v2:
* Change the MG_TX_DRVCTL registers names to match the spec (Anusha)
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 266 +++++++++++++++++++++++-----------------
1 file changed, 155 insertions(+), 111 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c30cfcd..1e4ed68 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1872,121 +1872,165 @@ enum i915_power_well_id {
#define N_SCALAR(x) ((x) << 24)
#define N_SCALAR_MASK (0x7F << 24)
-#define _ICL_MG_PHY_PORT_LN(port, ln, ln0p1, ln0p2, ln1p1) \
+#define MG_PHY_PORT_LN(port, ln, ln0p1, ln0p2, ln1p1) \
_MMIO(_PORT((port) - PORT_C, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
-#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT1 0x16812C
-#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT1 0x16852C
-#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT2 0x16912C
-#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT2 0x16952C
-#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT3 0x16A12C
-#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT3 0x16A52C
-#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT4 0x16B12C
-#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT4 0x16B52C
-#define ICL_PORT_MG_TX1_LINK_PARAMS(port, ln) \
- _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
- _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
- _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT1)
-
-#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT1 0x1680AC
-#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT1 0x1684AC
-#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT2 0x1690AC
-#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT2 0x1694AC
-#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT3 0x16A0AC
-#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT3 0x16A4AC
-#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT4 0x16B0AC
-#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT4 0x16B4AC
-#define ICL_PORT_MG_TX2_LINK_PARAMS(port, ln) \
- _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
- _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
- _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT1)
-#define CRI_USE_FS32 (1 << 5)
-
-#define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT1 0x16814C
-#define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT1 0x16854C
-#define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT2 0x16914C
-#define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT2 0x16954C
-#define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT3 0x16A14C
-#define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT3 0x16A54C
-#define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT4 0x16B14C
-#define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT4 0x16B54C
-#define ICL_PORT_MG_TX1_PISO_READLOAD(port, ln) \
- _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
- _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT2, \
- _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT1)
-
-#define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT1 0x1680CC
-#define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT1 0x1684CC
-#define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT2 0x1690CC
-#define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT2 0x1694CC
-#define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT3 0x16A0CC
-#define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT3 0x16A4CC
-#define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT4 0x16B0CC
-#define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT4 0x16B4CC
-#define ICL_PORT_MG_TX2_PISO_READLOAD(port, ln) \
- _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
- _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT2, \
- _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT1)
+#define MG_TX_LINK_PARAMS_TX1LN0_PORT1 0x16812C
+#define MG_TX_LINK_PARAMS_TX1LN1_PORT1 0x16852C
+#define MG_TX_LINK_PARAMS_TX1LN0_PORT2 0x16912C
+#define MG_TX_LINK_PARAMS_TX1LN1_PORT2 0x16952C
+#define MG_TX_LINK_PARAMS_TX1LN0_PORT3 0x16A12C
+#define MG_TX_LINK_PARAMS_TX1LN1_PORT3 0x16A52C
+#define MG_TX_LINK_PARAMS_TX1LN0_PORT4 0x16B12C
+#define MG_TX_LINK_PARAMS_TX1LN1_PORT4 0x16B52C
+#define MG_TX1_LINK_PARAMS(port, ln) \
+ MG_PHY_PORT_LN(port, ln, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
+ MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
+ MG_TX_LINK_PARAMS_TX1LN1_PORT1)
+
+#define MG_TX_LINK_PARAMS_TX2LN0_PORT1 0x1680AC
+#define MG_TX_LINK_PARAMS_TX2LN1_PORT1 0x1684AC
+#define MG_TX_LINK_PARAMS_TX2LN0_PORT2 0x1690AC
+#define MG_TX_LINK_PARAMS_TX2LN1_PORT2 0x1694AC
+#define MG_TX_LINK_PARAMS_TX2LN0_PORT3 0x16A0AC
+#define MG_TX_LINK_PARAMS_TX2LN1_PORT3 0x16A4AC
+#define MG_TX_LINK_PARAMS_TX2LN0_PORT4 0x16B0AC
+#define MG_TX_LINK_PARAMS_TX2LN1_PORT4 0x16B4AC
+#define MG_TX2_LINK_PARAMS(port, ln) \
+ MG_PHY_PORT_LN(port, ln, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
+ MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
+ MG_TX_LINK_PARAMS_TX2LN1_PORT1)
+#define CRI_USE_FS32 (1 << 5)
+
+#define MG_TX_PISO_READLOAD_TX1LN0_PORT1 0x16814C
+#define MG_TX_PISO_READLOAD_TX1LN1_PORT1 0x16854C
+#define MG_TX_PISO_READLOAD_TX1LN0_PORT2 0x16914C
+#define MG_TX_PISO_READLOAD_TX1LN1_PORT2 0x16954C
+#define MG_TX_PISO_READLOAD_TX1LN0_PORT3 0x16A14C
+#define MG_TX_PISO_READLOAD_TX1LN1_PORT3 0x16A54C
+#define MG_TX_PISO_READLOAD_TX1LN0_PORT4 0x16B14C
+#define MG_TX_PISO_READLOAD_TX1LN1_PORT4 0x16B54C
+#define MG_TX1_PISO_READLOAD(port, ln) \
+ MG_PHY_PORT_LN(port, ln, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
+ MG_TX_PISO_READLOAD_TX1LN0_PORT2, \
+ MG_TX_PISO_READLOAD_TX1LN1_PORT1)
+
+#define MG_TX_PISO_READLOAD_TX2LN0_PORT1 0x1680CC
+#define MG_TX_PISO_READLOAD_TX2LN1_PORT1 0x1684CC
+#define MG_TX_PISO_READLOAD_TX2LN0_PORT2 0x1690CC
+#define MG_TX_PISO_READLOAD_TX2LN1_PORT2 0x1694CC
+#define MG_TX_PISO_READLOAD_TX2LN0_PORT3 0x16A0CC
+#define MG_TX_PISO_READLOAD_TX2LN1_PORT3 0x16A4CC
+#define MG_TX_PISO_READLOAD_TX2LN0_PORT4 0x16B0CC
+#define MG_TX_PISO_READLOAD_TX2LN1_PORT4 0x16B4CC
+#define MG_TX2_PISO_READLOAD(port, ln) \
+ MG_PHY_PORT_LN(port, ln, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
+ MG_TX_PISO_READLOAD_TX2LN0_PORT2, \
+ MG_TX_PISO_READLOAD_TX2LN1_PORT1)
#define CRI_CALCINIT (1 << 1)
-#define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT1 0x168148
-#define _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT1 0x168548
-#define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT2 0x169148
-#define _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT2 0x169548
-#define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT3 0x16A148
-#define _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT3 0x16A548
-#define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT4 0x16B148
-#define _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT4 0x16B548
-#define ICL_PORT_MG_TX1_SWINGCTRL(port, ln) \
- _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT1, \
- _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT2, \
- _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT1)
-
-#define _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT1 0x1680C8
-#define _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT1 0x1684C8
-#define _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT2 0x1690C8
-#define _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT2 0x1694C8
-#define _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT3 0x16A0C8
-#define _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT3 0x16A4C8
-#define _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT4 0x16B0C8
-#define _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT4 0x16B4C8
-#define ICL_PORT_MG_TX2_SWINGCTRL(port, ln) \
- _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT1, \
- _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT2, \
- _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT1)
-#define CRI_TXDEEMPH_OVERRIDE_17_12(x) ((x) << 0)
-#define CRI_TXDEEMPH_OVERRIDE_17_12_MASK (0x3F << 0)
-
-#define _ICL_MG_TX_DRVCTRL_TX1LN0_PORT1 0x168144
-#define _ICL_MG_TX_DRVCTRL_TX1LN1_PORT1 0x168544
-#define _ICL_MG_TX_DRVCTRL_TX1LN0_PORT2 0x169144
-#define _ICL_MG_TX_DRVCTRL_TX1LN1_PORT2 0x169544
-#define _ICL_MG_TX_DRVCTRL_TX1LN0_PORT3 0x16A144
-#define _ICL_MG_TX_DRVCTRL_TX1LN1_PORT3 0x16A544
-#define _ICL_MG_TX_DRVCTRL_TX1LN0_PORT4 0x16B144
-#define _ICL_MG_TX_DRVCTRL_TX1LN1_PORT4 0x16B544
-#define ICL_PORT_MG_TX1_DRVCTRL(port, ln) \
- _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_DRVCTRL_TX1LN0_PORT1, \
- _ICL_MG_TX_DRVCTRL_TX1LN0_PORT2, \
- _ICL_MG_TX_DRVCTRL_TX1LN1_PORT1)
-
-#define _ICL_MG_TX_DRVCTRL_TX2LN0_PORT1 0x1680C4
-#define _ICL_MG_TX_DRVCTRL_TX2LN1_PORT1 0x1684C4
-#define _ICL_MG_TX_DRVCTRL_TX2LN0_PORT2 0x1690C4
-#define _ICL_MG_TX_DRVCTRL_TX2LN1_PORT2 0x1694C4
-#define _ICL_MG_TX_DRVCTRL_TX2LN0_PORT3 0x16A0C4
-#define _ICL_MG_TX_DRVCTRL_TX2LN1_PORT3 0x16A4C4
-#define _ICL_MG_TX_DRVCTRL_TX2LN0_PORT4 0x16B0C4
-#define _ICL_MG_TX_DRVCTRL_TX2LN1_PORT4 0x16B4C4
-#define ICL_PORT_MG_TX2_DRVCTRL(port, ln) \
- _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_DRVCTRL_TX2LN0_PORT1, \
- _ICL_MG_TX_DRVCTRL_TX2LN0_PORT2, \
- _ICL_MG_TX_DRVCTRL_TX2LN1_PORT1)
-#define CRI_TXDEEMPH_OVERRIDE_11_6(x) ((x) << 24)
-#define CRI_TXDEEMPH_OVERRIDE_11_6_MASK (0x3F << 24)
-#define CRI_TXDEEMPH_OVERRIDE_EN (1 << 22)
-#define CRI_TXDEEMPH_OVERRIDE_5_0(x) ((x) << 16)
-#define CRI_TXDEEMPH_OVERRIDE_5_0_MASK (0x3F << 16)
+#define MG_TX_SWINGCTRL_TX1LN0_PORT1 0x168148
+#define MG_TX_SWINGCTRL_TX1LN1_PORT1 0x168548
+#define MG_TX_SWINGCTRL_TX1LN0_PORT2 0x169148
+#define MG_TX_SWINGCTRL_TX1LN1_PORT2 0x169548
+#define MG_TX_SWINGCTRL_TX1LN0_PORT3 0x16A148
+#define MG_TX_SWINGCTRL_TX1LN1_PORT3 0x16A548
+#define MG_TX_SWINGCTRL_TX1LN0_PORT4 0x16B148
+#define MG_TX_SWINGCTRL_TX1LN1_PORT4 0x16B548
+#define MG_TX1_SWINGCTRL(port, ln) \
+ MG_PHY_PORT_LN(port, ln, MG_TX_SWINGCTRL_TX1LN0_PORT1, \
+ MG_TX_SWINGCTRL_TX1LN0_PORT2, \
+ MG_TX_SWINGCTRL_TX1LN1_PORT1)
+
+#define MG_TX_SWINGCTRL_TX2LN0_PORT1 0x1680C8
+#define MG_TX_SWINGCTRL_TX2LN1_PORT1 0x1684C8
+#define MG_TX_SWINGCTRL_TX2LN0_PORT2 0x1690C8
+#define MG_TX_SWINGCTRL_TX2LN1_PORT2 0x1694C8
+#define MG_TX_SWINGCTRL_TX2LN0_PORT3 0x16A0C8
+#define MG_TX_SWINGCTRL_TX2LN1_PORT3 0x16A4C8
+#define MG_TX_SWINGCTRL_TX2LN0_PORT4 0x16B0C8
+#define MG_TX_SWINGCTRL_TX2LN1_PORT4 0x16B4C8
+#define MG_TX2_SWINGCTRL(port, ln) \
+ MG_PHY_PORT_LN(port, ln, MG_TX_SWINGCTRL_TX2LN0_PORT1, \
+ MG_TX_SWINGCTRL_TX2LN0_PORT2, \
+ MG_TX_SWINGCTRL_TX2LN1_PORT1)
+#define CRI_TXDEEMPH_OVERRIDE_17_12(x) ((x) << 0)
+#define CRI_TXDEEMPH_OVERRIDE_17_12_MASK (0x3F << 0)
+
+#define MG_TX_DRVCTRL_TX1LN0_TXPORT1 0x168144
+#define MG_TX_DRVCTRL_TX1LN1_TXPORT1 0x168544
+#define MG_TX_DRVCTRL_TX1LN0_TXPORT2 0x169144
+#define MG_TX_DRVCTRL_TX1LN1_TXPORT2 0x169544
+#define MG_TX_DRVCTRL_TX1LN0_TXPORT3 0x16A144
+#define MG_TX_DRVCTRL_TX1LN1_TXPORT3 0x16A544
+#define MG_TX_DRVCTRL_TX1LN0_TXPORT4 0x16B144
+#define MG_TX_DRVCTRL_TX1LN1_TXPORT4 0x16B544
+#define MG_TX1_DRVCTRL(port, ln) \
+ MG_PHY_PORT_LN(port, ln, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \
+ MG_TX_DRVCTRL_TX1LN0_TXPORT2, \
+ MG_TX_DRVCTRL_TX1LN1_TXPORT1)
+
+#define MG_TX_DRVCTRL_TX2LN0_PORT1 0x1680C4
+#define MG_TX_DRVCTRL_TX2LN1_PORT1 0x1684C4
+#define MG_TX_DRVCTRL_TX2LN0_PORT2 0x1690C4
+#define MG_TX_DRVCTRL_TX2LN1_PORT2 0x1694C4
+#define MG_TX_DRVCTRL_TX2LN0_PORT3 0x16A0C4
+#define MG_TX_DRVCTRL_TX2LN1_PORT3 0x16A4C4
+#define MG_TX_DRVCTRL_TX2LN0_PORT4 0x16B0C4
+#define MG_TX_DRVCTRL_TX2LN1_PORT4 0x16B4C4
+#define MG_TX2_DRVCTRL(port, ln) \
+ MG_PHY_PORT_LN(port, ln, MG_TX_DRVCTRL_TX2LN0_PORT1, \
+ MG_TX_DRVCTRL_TX2LN0_PORT2, \
+ MG_TX_DRVCTRL_TX2LN1_PORT1)
+#define CRI_TXDEEMPH_OVERRIDE_11_6(x) ((x) << 24)
+#define CRI_TXDEEMPH_OVERRIDE_11_6_MASK (0x3F << 24)
+#define CRI_TXDEEMPH_OVERRIDE_EN (1 << 22)
+#define CRI_TXDEEMPH_OVERRIDE_5_0(x) ((x) << 16)
+#define CRI_TXDEEMPH_OVERRIDE_5_0_MASK (0x3F << 16)
+#define CRI_LOADGEN_SEL(x) ((x) << 12)
+#define CRI_LOADGEN_SEL_MASK (0x3 << 12)
+
+#define MG_CLKHUB_LN0_PORT1 0x16839C
+#define MG_CLKHUB_LN1_PORT1 0x16879C
+#define MG_CLKHUB_LN0_PORT2 0x16939C
+#define MG_CLKHUB_LN1_PORT2 0x16979C
+#define MG_CLKHUB_LN0_PORT3 0x16A39C
+#define MG_CLKHUB_LN1_PORT3 0x16A79C
+#define MG_CLKHUB_LN0_PORT4 0x16B39C
+#define MG_CLKHUB_LN1_PORT4 0x16B79C
+#define MG_CLKHUB(port, ln) \
+ MG_PHY_PORT_LN(port, ln, MG_CLKHUB_LN0_PORT1, \
+ MG_CLKHUB_LN0_PORT2, \
+ MG_CLKHUB_LN1_PORT1)
+#define CFG_LOW_RATE_LKREN_EN (1 << 11)
+
+#define MG_TX_DCC_TX1LN0_PORT1 0x168110
+#define MG_TX_DCC_TX1LN1_PORT1 0x168510
+#define MG_TX_DCC_TX1LN0_PORT2 0x169110
+#define MG_TX_DCC_TX1LN1_PORT2 0x169510
+#define MG_TX_DCC_TX1LN0_PORT3 0x16A110
+#define MG_TX_DCC_TX1LN1_PORT3 0x16A510
+#define MG_TX_DCC_TX1LN0_PORT4 0x16B110
+#define MG_TX_DCC_TX1LN1_PORT4 0x16B510
+#define MG_TX1_DCC(port, ln) \
+ MG_PHY_PORT_LN(port, ln, MG_TX_DCC_TX1LN0_PORT1, \
+ MG_TX_DCC_TX1LN0_PORT2, \
+ MG_TX_DCC_TX1LN1_PORT1)
+#define MG_TX_DCC_TX2LN0_PORT1 0x168090
+#define MG_TX_DCC_TX2LN1_PORT1 0x168490
+#define MG_TX_DCC_TX2LN0_PORT2 0x169090
+#define MG_TX_DCC_TX2LN1_PORT2 0x169490
+#define MG_TX_DCC_TX2LN0_PORT3 0x16A090
+#define MG_TX_DCC_TX2LN1_PORT3 0x16A490
+#define MG_TX_DCC_TX2LN0_PORT4 0x16B090
+#define MG_TX_DCC_TX2LN1_PORT4 0x16B490
+#define MG_TX2_DCC(port, ln) \
+ MG_PHY_PORT_LN(port, ln, MG_TX_DCC_TX2LN0_PORT1, \
+ MG_TX_DCC_TX2LN0_PORT2, \
+ MG_TX_DCC_TX2LN1_PORT1)
+#define CFG_AMI_CK_DIV_OVERRIDE_VAL(x) ((x) << 25)
+#define CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK (0x3 << 25)
+#define CFG_AMI_CK_DIV_OVERRIDE_EN (1 << 24)
/* The spec defines this only for BXT PHY0, but lets assume that this
* would exist for PHY1 too if it had a second channel.
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 15+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3] drm/i915/icl: Add remaining registers and bitfields for MG PHY DDI (rev3)
2018-06-28 22:35 [PATCH v2 1/2] drm/i915/icl: Add remaining registers and bitfields for MG PHY DDI Manasi Navare
` (8 preceding siblings ...)
2018-07-13 19:43 ` [PATCH v3] " Manasi Navare
@ 2018-07-13 19:50 ` Patchwork
2018-07-13 20:06 ` ✓ Fi.CI.BAT: success " Patchwork
10 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2018-07-13 19:50 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v3] drm/i915/icl: Add remaining registers and bitfields for MG PHY DDI (rev3)
URL : https://patchwork.freedesktop.org/series/45623/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ce48abb9636a drm/i915/icl: Add remaining registers and bitfields for MG PHY DDI
-:37: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'ln0p1' - possible side-effects?
#37: FILE: drivers/gpu/drm/i915/i915_reg.h:1935:
+#define MG_PHY_PORT_LN(port, ln, ln0p1, ln0p2, ln1p1) \
_MMIO(_PORT((port) - PORT_C, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
total: 0 errors, 0 warnings, 1 checks, 276 lines checked
01e5f1c68b2a drm/i915/icl: Implement voltage swing programming sequence for MG PHY DDI
-:79: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#79: FILE: drivers/gpu/drm/i915/intel_ddi.c:2501:
+ val |= CRI_TXDEEMPH_OVERRIDE_17_12(
-:85: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#85: FILE: drivers/gpu/drm/i915/intel_ddi.c:2507:
+ val |= CRI_TXDEEMPH_OVERRIDE_17_12(
-:95: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#95: FILE: drivers/gpu/drm/i915/intel_ddi.c:2517:
+ val |= CRI_TXDEEMPH_OVERRIDE_5_0(
-:97: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#97: FILE: drivers/gpu/drm/i915/intel_ddi.c:2519:
+ CRI_TXDEEMPH_OVERRIDE_11_6(
-:105: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#105: FILE: drivers/gpu/drm/i915/intel_ddi.c:2527:
+ val |= CRI_TXDEEMPH_OVERRIDE_5_0(
-:107: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#107: FILE: drivers/gpu/drm/i915/intel_ddi.c:2529:
+ CRI_TXDEEMPH_OVERRIDE_11_6(
total: 0 errors, 0 warnings, 6 checks, 165 lines checked
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [v3] drm/i915/icl: Add remaining registers and bitfields for MG PHY DDI (rev3)
2018-06-28 22:35 [PATCH v2 1/2] drm/i915/icl: Add remaining registers and bitfields for MG PHY DDI Manasi Navare
` (9 preceding siblings ...)
2018-07-13 19:50 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3] drm/i915/icl: Add remaining registers and bitfields for MG PHY DDI (rev3) Patchwork
@ 2018-07-13 20:06 ` Patchwork
10 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2018-07-13 20:06 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v3] drm/i915/icl: Add remaining registers and bitfields for MG PHY DDI (rev3)
URL : https://patchwork.freedesktop.org/series/45623/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4488 -> Patchwork_9652 =
== Summary - SUCCESS ==
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/45623/revisions/3/mbox/
== Known issues ==
Here are the changes found in Patchwork_9652 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@gem_exec_suspend@basic-s3:
{fi-cfl-8109u}: PASS -> INCOMPLETE (fdo#107187)
igt@kms_frontbuffer_tracking@basic:
fi-hsw-peppy: PASS -> DMESG-FAIL (fdo#106103, fdo#102614)
==== Possible fixes ====
igt@debugfs_test@read_all_entries:
fi-snb-2520m: INCOMPLETE (fdo#103713) -> PASS
igt@kms_chamelium@hdmi-hpd-fast:
fi-kbl-7500u: FAIL (fdo#103841, fdo#102672) -> SKIP
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
fdo#102672 https://bugs.freedesktop.org/show_bug.cgi?id=102672
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841
fdo#106103 https://bugs.freedesktop.org/show_bug.cgi?id=106103
fdo#107187 https://bugs.freedesktop.org/show_bug.cgi?id=107187
== Participating hosts (46 -> 41) ==
Missing (5): fi-skl-guc fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u
== Build changes ==
* Linux: CI_DRM_4488 -> Patchwork_9652
CI_DRM_4488: a3a527faf129e7901fdff5309a7e6df8abd72d13 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4557: 140a67c13aad2595ee6c72e41d14d35a793158b5 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9652: 01e5f1c68b2abb21df3f3a6449aedc064208ec12 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
01e5f1c68b2a drm/i915/icl: Implement voltage swing programming sequence for MG PHY DDI
ce48abb9636a drm/i915/icl: Add remaining registers and bitfields for MG PHY DDI
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9652/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3] drm/i915/icl: Add remaining registers and bitfields for MG PHY DDI
2018-07-13 19:43 ` [PATCH v3] " Manasi Navare
@ 2018-07-16 21:01 ` Paulo Zanoni
0 siblings, 0 replies; 15+ messages in thread
From: Paulo Zanoni @ 2018-07-16 21:01 UTC (permalink / raw)
To: Manasi Navare, intel-gfx
Em Sex, 2018-07-13 às 12:43 -0700, Manasi Navare escreveu:
> This patch adds the remaining register definitions and bit fields
> required for MG PHy DDI buffer initializations and voltage
> swing programming for MG PHy DDI ports.
>
> While at it this patch also fixes the naming for previously defined
> MG PHY registers in original commit id (c92f47b5ec977a "drm/i915/icl:
> Add register defs for voltage swing sequences for MG PHY DDI").
> Since the MG PHY registers are first defined in ICL platform, there
> is no need for _ICL prefix.
>
> v3:
> * Fix register names, add spaces for MASK defines, correct the order
> of #defines (Paulo)
>
> v2:
> * Change the MG_TX_DRVCTL registers names to match the spec (Anusha)
>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: James Ausmus <james.ausmus@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 266 +++++++++++++++++++++++-------
> ----------
> 1 file changed, 155 insertions(+), 111 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index c30cfcd..1e4ed68 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1872,121 +1872,165 @@ enum i915_power_well_id {
> #define N_SCALAR(x) ((x) << 24)
> #define N_SCALAR_MASK (0x7F << 24)
>
> -#define _ICL_MG_PHY_PORT_LN(port, ln, ln0p1, ln0p2, ln1p1) \
> +#define MG_PHY_PORT_LN(port, ln, ln0p1, ln0p2, ln1p1) \
> _MMIO(_PORT((port) - PORT_C, ln0p1, ln0p2) + (ln) * ((ln1p1)
> - (ln0p1)))
>
> -#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT1 0x16812C
> -#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT1 0x16852C
> -#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT2 0x16912C
> -#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT2 0x16952C
> -#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT3 0x16A12C
> -#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT3 0x16A52C
> -#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT4 0x16B12C
> -#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT4 0x16B52C
> -#define ICL_PORT_MG_TX1_LINK_PARAMS(port, ln) \
> - _ICL_MG_PHY_PORT_LN(port, ln,
> _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
> - _ICL_MG_TX_LINK_PARAMS_TX1LN0_
> PORT2, \
> - _ICL_MG_TX_LINK_PARAMS_TX1LN1_
> PORT1)
> -
> -#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT1 0x1680AC
> -#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT1 0x1684AC
> -#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT2 0x1690AC
> -#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT2 0x1694AC
> -#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT3 0x16A0AC
> -#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT3 0x16A4AC
> -#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT4 0x16B0AC
> -#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT4 0x16B4AC
> -#define ICL_PORT_MG_TX2_LINK_PARAMS(port, ln) \
> - _ICL_MG_PHY_PORT_LN(port, ln,
> _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
> - _ICL_MG_TX_LINK_PARAMS_TX2LN0_
> PORT2, \
> - _ICL_MG_TX_LINK_PARAMS_TX2LN1_
> PORT1)
> -#define CRI_USE_FS32 (1 << 5)
> -
> -#define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT1 0x16814
> C
> -#define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT1 0x16854
> C
> -#define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT2 0x16914
> C
> -#define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT2 0x16954
> C
> -#define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT3 0x16A14
> C
> -#define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT3 0x16A54
> C
> -#define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT4 0x16B14
> C
> -#define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT4 0x16B54
> C
> -#define ICL_PORT_MG_TX1_PISO_READLOAD(port, ln) \
> - _ICL_MG_PHY_PORT_LN(port, ln,
> _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
> - _ICL_MG_TX_PISO_READLOAD_TX1LN
> 0_PORT2, \
> - _ICL_MG_TX_PISO_READLOAD_TX1LN
> 1_PORT1)
> -
> -#define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT1 0x1680C
> C
> -#define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT1 0x1684C
> C
> -#define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT2 0x1690C
> C
> -#define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT2 0x1694C
> C
> -#define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT3 0x16A0C
> C
> -#define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT3 0x16A4C
> C
> -#define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT4 0x16B0C
> C
> -#define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT4 0x16B4C
> C
> -#define ICL_PORT_MG_TX2_PISO_READLOAD(port, ln) \
> - _ICL_MG_PHY_PORT_LN(port, ln,
> _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
> - _ICL_MG_TX_PISO_READLOAD_TX2LN
> 0_PORT2, \
> - _ICL_MG_TX_PISO_READLOAD_TX2LN
> 1_PORT1)
> +#define MG_TX_LINK_PARAMS_TX1LN0_PORT1 0x16812C
> +#define MG_TX_LINK_PARAMS_TX1LN1_PORT1 0x16852C
> +#define MG_TX_LINK_PARAMS_TX1LN0_PORT2 0x16912C
> +#define MG_TX_LINK_PARAMS_TX1LN1_PORT2 0x16952C
> +#define MG_TX_LINK_PARAMS_TX1LN0_PORT3 0x16A12C
> +#define MG_TX_LINK_PARAMS_TX1LN1_PORT3 0x16A52C
> +#define MG_TX_LINK_PARAMS_TX1LN0_PORT4 0x16B12C
> +#define MG_TX_LINK_PARAMS_TX1LN1_PORT4 0x16B52C
> +#define MG_TX1_LINK_PARAMS(port, ln) \
> + MG_PHY_PORT_LN(port, ln, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
> + MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
> + MG_TX_LINK_PARAMS_TX1LN1_PORT1)
> +
> +#define MG_TX_LINK_PARAMS_TX2LN0_PORT1 0x1680AC
> +#define MG_TX_LINK_PARAMS_TX2LN1_PORT1 0x1684AC
> +#define MG_TX_LINK_PARAMS_TX2LN0_PORT2 0x1690AC
> +#define MG_TX_LINK_PARAMS_TX2LN1_PORT2 0x1694AC
> +#define MG_TX_LINK_PARAMS_TX2LN0_PORT3 0x16A0AC
> +#define MG_TX_LINK_PARAMS_TX2LN1_PORT3 0x16A4AC
> +#define MG_TX_LINK_PARAMS_TX2LN0_PORT4 0x16B0AC
> +#define MG_TX_LINK_PARAMS_TX2LN1_PORT4 0x16B4AC
> +#define MG_TX2_LINK_PARAMS(port, ln) \
> + MG_PHY_PORT_LN(port, ln, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
> + MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
> + MG_TX_LINK_PARAMS_TX2LN1_PORT1)
> +#define CRI_USE_FS32 (1 << 5)
> +
> +#define MG_TX_PISO_READLOAD_TX1LN0_PORT1 0x16814C
> +#define MG_TX_PISO_READLOAD_TX1LN1_PORT1 0x16854C
> +#define MG_TX_PISO_READLOAD_TX1LN0_PORT2 0x16914C
> +#define MG_TX_PISO_READLOAD_TX1LN1_PORT2 0x16954C
> +#define MG_TX_PISO_READLOAD_TX1LN0_PORT3 0x16A14C
> +#define MG_TX_PISO_READLOAD_TX1LN1_PORT3 0x16A54C
> +#define MG_TX_PISO_READLOAD_TX1LN0_PORT4 0x16B14C
> +#define MG_TX_PISO_READLOAD_TX1LN1_PORT4 0x16B54C
> +#define MG_TX1_PISO_READLOAD(port, ln) \
> + MG_PHY_PORT_LN(port, ln, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
> + MG_TX_PISO_READLOAD_TX1LN0_PORT2, \
> + MG_TX_PISO_READLOAD_TX1LN1_PORT1)
> +
> +#define MG_TX_PISO_READLOAD_TX2LN0_PORT1 0x1680CC
> +#define MG_TX_PISO_READLOAD_TX2LN1_PORT1 0x1684CC
> +#define MG_TX_PISO_READLOAD_TX2LN0_PORT2 0x1690CC
> +#define MG_TX_PISO_READLOAD_TX2LN1_PORT2 0x1694CC
> +#define MG_TX_PISO_READLOAD_TX2LN0_PORT3 0x16A0CC
> +#define MG_TX_PISO_READLOAD_TX2LN1_PORT3 0x16A4CC
> +#define MG_TX_PISO_READLOAD_TX2LN0_PORT4 0x16B0CC
> +#define MG_TX_PISO_READLOAD_TX2LN1_PORT4 0x16B4CC
> +#define MG_TX2_PISO_READLOAD(port, ln) \
> + MG_PHY_PORT_LN(port, ln, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
> + MG_TX_PISO_READLOAD_TX2LN0_PORT2, \
> + MG_TX_PISO_READLOAD_TX2LN1_PORT1)
> #define CRI_CALCINIT (1 << 1)
You missed the extra spaces on this one.
With that:
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> -#define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT1 0x168148
> -#define _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT1 0x168548
> -#define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT2 0x169148
> -#define _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT2 0x169548
> -#define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT3 0x16A148
> -#define _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT3 0x16A548
> -#define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT4 0x16B148
> -#define _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT4 0x16B548
> -#define ICL_PORT_MG_TX1_SWINGCTRL(port, ln) \
> - _ICL_MG_PHY_PORT_LN(port, ln,
> _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT1, \
> - _ICL_MG_TX_SWINGCTRL_TX1LN0_PO
> RT2, \
> - _ICL_MG_TX_SWINGCTRL_TX1LN1_PO
> RT1)
> -
> -#define _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT1 0x1680C8
> -#define _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT1 0x1684C8
> -#define _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT2 0x1690C8
> -#define _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT2 0x1694C8
> -#define _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT3 0x16A0C8
> -#define _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT3 0x16A4C8
> -#define _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT4 0x16B0C8
> -#define _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT4 0x16B4C8
> -#define ICL_PORT_MG_TX2_SWINGCTRL(port, ln) \
> - _ICL_MG_PHY_PORT_LN(port, ln,
> _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT1, \
> - _ICL_MG_TX_SWINGCTRL_TX2LN0_PO
> RT2, \
> - _ICL_MG_TX_SWINGCTRL_TX2LN1_PO
> RT1)
> -#define CRI_TXDEEMPH_OVERRIDE_17_12(x) ((x)
> << 0)
> -#define CRI_TXDEEMPH_OVERRIDE_17_12_MASK (0x3F << 0)
> -
> -#define _ICL_MG_TX_DRVCTRL_TX1LN0_PORT1 0x168
> 144
> -#define _ICL_MG_TX_DRVCTRL_TX1LN1_PORT1 0x168
> 544
> -#define _ICL_MG_TX_DRVCTRL_TX1LN0_PORT2 0x169
> 144
> -#define _ICL_MG_TX_DRVCTRL_TX1LN1_PORT2 0x169
> 544
> -#define _ICL_MG_TX_DRVCTRL_TX1LN0_PORT3 0x16A
> 144
> -#define _ICL_MG_TX_DRVCTRL_TX1LN1_PORT3 0x16A
> 544
> -#define _ICL_MG_TX_DRVCTRL_TX1LN0_PORT4 0x16B
> 144
> -#define _ICL_MG_TX_DRVCTRL_TX1LN1_PORT4 0x16B
> 544
> -#define ICL_PORT_MG_TX1_DRVCTRL(port, ln) \
> - _ICL_MG_PHY_PORT_LN(port, ln,
> _ICL_MG_TX_DRVCTRL_TX1LN0_PORT1, \
> - _ICL_MG_TX_DRVCTRL_TX1LN0_PORT
> 2, \
> - _ICL_MG_TX_DRVCTRL_TX1LN1_PORT
> 1)
> -
> -#define _ICL_MG_TX_DRVCTRL_TX2LN0_PORT1 0x168
> 0C4
> -#define _ICL_MG_TX_DRVCTRL_TX2LN1_PORT1 0x168
> 4C4
> -#define _ICL_MG_TX_DRVCTRL_TX2LN0_PORT2 0x169
> 0C4
> -#define _ICL_MG_TX_DRVCTRL_TX2LN1_PORT2 0x169
> 4C4
> -#define _ICL_MG_TX_DRVCTRL_TX2LN0_PORT3 0x16A
> 0C4
> -#define _ICL_MG_TX_DRVCTRL_TX2LN1_PORT3 0x16A
> 4C4
> -#define _ICL_MG_TX_DRVCTRL_TX2LN0_PORT4 0x16B
> 0C4
> -#define _ICL_MG_TX_DRVCTRL_TX2LN1_PORT4 0x16B
> 4C4
> -#define ICL_PORT_MG_TX2_DRVCTRL(port, ln) \
> - _ICL_MG_PHY_PORT_LN(port, ln,
> _ICL_MG_TX_DRVCTRL_TX2LN0_PORT1, \
> - _ICL_MG_TX_DRVCTRL_TX2LN0_PORT
> 2, \
> - _ICL_MG_TX_DRVCTRL_TX2LN1_PORT
> 1)
> -#define CRI_TXDEEMPH_OVERRIDE_11_6(x) ((x) <<
> 24)
> -#define CRI_TXDEEMPH_OVERRIDE_11_6_MASK (0x3F
> << 24)
> -#define CRI_TXDEEMPH_OVERRIDE_EN (1 << 22)
> -#define CRI_TXDEEMPH_OVERRIDE_5_0(x) ((x) <<
> 16)
> -#define CRI_TXDEEMPH_OVERRIDE_5_0_MASK (0x3F
> << 16)
> +#define MG_TX_SWINGCTRL_TX1LN0_PORT1 0x168148
> +#define MG_TX_SWINGCTRL_TX1LN1_PORT1 0x168548
> +#define MG_TX_SWINGCTRL_TX1LN0_PORT2 0x169148
> +#define MG_TX_SWINGCTRL_TX1LN1_PORT2 0x169548
> +#define MG_TX_SWINGCTRL_TX1LN0_PORT3 0x16A148
> +#define MG_TX_SWINGCTRL_TX1LN1_PORT3 0x16A548
> +#define MG_TX_SWINGCTRL_TX1LN0_PORT4 0x16B148
> +#define MG_TX_SWINGCTRL_TX1LN1_PORT4 0x16B548
> +#define MG_TX1_SWINGCTRL(port, ln) \
> + MG_PHY_PORT_LN(port, ln, MG_TX_SWINGCTRL_TX1LN0_PORT1, \
> + MG_TX_SWINGCTRL_TX1LN0_PORT2, \
> + MG_TX_SWINGCTRL_TX1LN1_PORT1)
> +
> +#define MG_TX_SWINGCTRL_TX2LN0_PORT1 0x1680C8
> +#define MG_TX_SWINGCTRL_TX2LN1_PORT1 0x1684C8
> +#define MG_TX_SWINGCTRL_TX2LN0_PORT2 0x1690C8
> +#define MG_TX_SWINGCTRL_TX2LN1_PORT2 0x1694C8
> +#define MG_TX_SWINGCTRL_TX2LN0_PORT3 0x16A0C8
> +#define MG_TX_SWINGCTRL_TX2LN1_PORT3 0x16A4C8
> +#define MG_TX_SWINGCTRL_TX2LN0_PORT4 0x16B0C8
> +#define MG_TX_SWINGCTRL_TX2LN1_PORT4 0x16B4C8
> +#define MG_TX2_SWINGCTRL(port, ln) \
> + MG_PHY_PORT_LN(port, ln, MG_TX_SWINGCTRL_TX2LN0_PORT1, \
> + MG_TX_SWINGCTRL_TX2LN0_PORT2, \
> + MG_TX_SWINGCTRL_TX2LN1_PORT1)
> +#define CRI_TXDEEMPH_OVERRIDE_17_12(x) ((x) << 0)
> +#define CRI_TXDEEMPH_OVERRIDE_17_12_MASK (0x3F <<
> 0)
> +
> +#define MG_TX_DRVCTRL_TX1LN0_TXPORT1 0x168144
> +#define MG_TX_DRVCTRL_TX1LN1_TXPORT1 0x168544
> +#define MG_TX_DRVCTRL_TX1LN0_TXPORT2 0x169144
> +#define MG_TX_DRVCTRL_TX1LN1_TXPORT2 0x169544
> +#define MG_TX_DRVCTRL_TX1LN0_TXPORT3 0x16A144
> +#define MG_TX_DRVCTRL_TX1LN1_TXPORT3 0x16A544
> +#define MG_TX_DRVCTRL_TX1LN0_TXPORT4 0x16B144
> +#define MG_TX_DRVCTRL_TX1LN1_TXPORT4 0x16B544
> +#define MG_TX1_DRVCTRL(port, ln) \
> + MG_PHY_PORT_LN(port, ln, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \
> + MG_TX_DRVCTRL_TX1LN0_TXPORT2, \
> + MG_TX_DRVCTRL_TX1LN1_TXPORT1)
> +
> +#define MG_TX_DRVCTRL_TX2LN0_PORT1 0x1680C4
> +#define MG_TX_DRVCTRL_TX2LN1_PORT1 0x1684C4
> +#define MG_TX_DRVCTRL_TX2LN0_PORT2 0x1690C4
> +#define MG_TX_DRVCTRL_TX2LN1_PORT2 0x1694C4
> +#define MG_TX_DRVCTRL_TX2LN0_PORT3 0x16A0C4
> +#define MG_TX_DRVCTRL_TX2LN1_PORT3 0x16A4C4
> +#define MG_TX_DRVCTRL_TX2LN0_PORT4 0x16B0C4
> +#define MG_TX_DRVCTRL_TX2LN1_PORT4 0x16B4C4
> +#define MG_TX2_DRVCTRL(port, ln) \
> + MG_PHY_PORT_LN(port, ln, MG_TX_DRVCTRL_TX2LN0_PORT1, \
> + MG_TX_DRVCTRL_TX2LN0_PORT2, \
> + MG_TX_DRVCTRL_TX2LN1_PORT1)
> +#define CRI_TXDEEMPH_OVERRIDE_11_6(x) ((x)
> << 24)
> +#define CRI_TXDEEMPH_OVERRIDE_11_6_MASK (0x3F <<
> 24)
> +#define CRI_TXDEEMPH_OVERRIDE_EN (1 << 22)
> +#define CRI_TXDEEMPH_OVERRIDE_5_0(x) ((x)
> << 16)
> +#define CRI_TXDEEMPH_OVERRIDE_5_0_MASK (0x3F << 16)
> +#define CRI_LOADGEN_SEL(x) ((x) <<
> 12)
> +#define CRI_LOADGEN_SEL_MASK (0x3
> << 12)
> +
> +#define MG_CLKHUB_LN0_PORT1 0x16839C
> +#define MG_CLKHUB_LN1_PORT1 0x16879C
> +#define MG_CLKHUB_LN0_PORT2 0x16939C
> +#define MG_CLKHUB_LN1_PORT2 0x16979C
> +#define MG_CLKHUB_LN0_PORT3 0x16A39C
> +#define MG_CLKHUB_LN1_PORT3 0x16A79C
> +#define MG_CLKHUB_LN0_PORT4 0x16B39C
> +#define MG_CLKHUB_LN1_PORT4 0x16B79C
> +#define MG_CLKHUB(port, ln) \
> + MG_PHY_PORT_LN(port, ln, MG_CLKHUB_LN0_PORT1, \
> + MG_CLKHUB_LN0_PORT2, \
> + MG_CLKHUB_LN1_PORT1)
> +#define CFG_LOW_RATE_LKREN_EN (1 <<
> 11)
> +
> +#define MG_TX_DCC_TX1LN0_PORT1 0x168110
> +#define MG_TX_DCC_TX1LN1_PORT1 0x168510
> +#define MG_TX_DCC_TX1LN0_PORT2 0x169110
> +#define MG_TX_DCC_TX1LN1_PORT2 0x169510
> +#define MG_TX_DCC_TX1LN0_PORT3 0x16A110
> +#define MG_TX_DCC_TX1LN1_PORT3 0x16A510
> +#define MG_TX_DCC_TX1LN0_PORT4 0x16B110
> +#define MG_TX_DCC_TX1LN1_PORT4 0x16B510
> +#define MG_TX1_DCC(port, ln) \
> + MG_PHY_PORT_LN(port, ln, MG_TX_DCC_TX1LN0_PORT1, \
> + MG_TX_DCC_TX1LN0_PORT2, \
> + MG_TX_DCC_TX1LN1_PORT1)
> +#define MG_TX_DCC_TX2LN0_PORT1 0x168090
> +#define MG_TX_DCC_TX2LN1_PORT1 0x168490
> +#define MG_TX_DCC_TX2LN0_PORT2 0x169090
> +#define MG_TX_DCC_TX2LN1_PORT2 0x169490
> +#define MG_TX_DCC_TX2LN0_PORT3 0x16A090
> +#define MG_TX_DCC_TX2LN1_PORT3 0x16A490
> +#define MG_TX_DCC_TX2LN0_PORT4 0x16B090
> +#define MG_TX_DCC_TX2LN1_PORT4 0x16B490
> +#define MG_TX2_DCC(port, ln) \
> + MG_PHY_PORT_LN(port, ln, MG_TX_DCC_TX2LN0_PORT1, \
> + MG_TX_DCC_TX2LN0_PORT2, \
> + MG_TX_DCC_TX2LN1_PORT1)
> +#define CFG_AMI_CK_DIV_OVERRIDE_VAL(x) ((x) << 25)
> +#define CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK (0x3 << 25)
> +#define CFG_AMI_CK_DIV_OVERRIDE_EN (1 << 24)
>
> /* The spec defines this only for BXT PHY0, but lets assume that
> this
> * would exist for PHY1 too if it had a second channel.
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^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 2/2] drm/i915/icl: Implement voltage swing programming sequence for MG PHY DDI
2018-06-28 22:35 ` [PATCH v2 2/2] drm/i915/icl: Implement voltage swing programming sequence " Manasi Navare
@ 2018-07-16 23:48 ` Paulo Zanoni
0 siblings, 0 replies; 15+ messages in thread
From: Paulo Zanoni @ 2018-07-16 23:48 UTC (permalink / raw)
To: Manasi Navare, intel-gfx; +Cc: Rodrigo Vivi
Em Qui, 2018-06-28 às 15:35 -0700, Manasi Navare escreveu:
> This sequence is used to setup voltage swing before enabling MG PHY
> DDI
> as well as for changing the voltage during DisplayPort Link training.
>
> For ICL, there are two types of DDIs. This sequence needs to be used
> for MG PHY DDI which is ports C-F.
And our spec is still incomplete...
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> v6 (From Manasi):
> * Add programming for MG_CLKHUB and MG_TX_DCC as per the
> spec updates
>
> v5 (from Paulo):
> * Checkpatch.
> v4 (from Paulo):
> * Fix bogus error message
> * Fix copy+paste bugs (missing s/TX1/TX2/ after copy+paste)
> * Use the new mask names
> * Stay under 80 columns
> * Add some blank lines
> v3:
> * Clear the regs before writing (Paulo)
> v2:
> * Rename to MG PHY in the function def (Jani Nikula)
> * Rebase on top of new revision of other patches in series
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 135
> +++++++++++++++++++++++++++++++++++++--
> 1 file changed, 129 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 0319825..c91e96e 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2459,7 +2459,128 @@ static void
> icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
> I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
> }
>
> -static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
> u32 level,
> +static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder
> *encoder,
> + int link_clock,
> + u32 level)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder-
> >base.dev);
> + enum port port = encoder->port;
> + const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
> + u32 n_entries, val;
> + int ln;
> +
> + n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
> + ddi_translations = icl_mg_phy_ddi_translations;
> + /* The table does not have values for level 3 and level 9.
> */
> + if (level >= n_entries || level == 3 || level == 9) {
> + DRM_DEBUG_KMS("DDI translation not found for level
> %d. Using %d instead.",
> + level, n_entries - 2);
> + level = n_entries - 2;
> + }
> +
> + /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
> + for (ln = 0; ln < 2; ln++) {
> + val = I915_READ(MG_TX1_LINK_PARAMS(port, ln));
> + val &= ~CRI_USE_FS32;
> + I915_WRITE(MG_TX1_LINK_PARAMS(port, ln), val);
> +
> + val = I915_READ(MG_TX2_LINK_PARAMS(port, ln));
> + val &= ~CRI_USE_FS32;
> + I915_WRITE(MG_TX2_LINK_PARAMS(port, ln), val);
> + }
> +
> + /* Program MG_TX_SWINGCTRL with values from vswing table */
> + for (ln = 0; ln < 2; ln++) {
> + val = I915_READ(MG_TX1_SWINGCTRL(port, ln));
> + val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
> + val |= CRI_TXDEEMPH_OVERRIDE_17_12(
> + ddi_translations[level].cri_txdeemph_overrid
> e_17_12);
> + I915_WRITE(MG_TX1_SWINGCTRL(port, ln), val);
> +
> + val = I915_READ(MG_TX2_SWINGCTRL(port, ln));
> + val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
> + val |= CRI_TXDEEMPH_OVERRIDE_17_12(
> + ddi_translations[level].cri_txdeemph_overrid
> e_17_12);
> + I915_WRITE(MG_TX2_SWINGCTRL(port, ln), val);
> + }
> +
> + /* Program MG_TX_DRVCTRL with values from vswing table */
> + for (ln = 0; ln < 2; ln++) {
> + val = I915_READ(MG_TX1_DRVCTRL(port, ln));
> + val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
> + CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
> + val |= CRI_TXDEEMPH_OVERRIDE_5_0(
> + ddi_translations[level].cri_txdeemph_overrid
> e_5_0) |
> + CRI_TXDEEMPH_OVERRIDE_11_6(
> + ddi_translations[level].cri_txdeemph
> _override_11_6) |
> + CRI_TXDEEMPH_OVERRIDE_EN;
> + I915_WRITE(MG_TX1_DRVCTRL(port, ln), val);
> +
> + val = I915_READ(MG_TX2_DRVCTRL(port, ln));
> + val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
> + CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
> + val |= CRI_TXDEEMPH_OVERRIDE_5_0(
> + ddi_translations[level].cri_txdeemph_overrid
> e_5_0) |
> + CRI_TXDEEMPH_OVERRIDE_11_6(
> + ddi_translations[level].cri_txdeemph
> _override_11_6) |
> + CRI_TXDEEMPH_OVERRIDE_EN;
> + I915_WRITE(MG_TX2_DRVCTRL(port, ln), val);
> +
> + /* FIXME: Program CRI_LOADGEN_SEL after the spec is
> updated */
> + }
> +
> + /*
> + * Program MG_CLKHUB<LN, port being used> with value from
> frequency table
> + * In case of Legacy mode on MG PHY, both TX1 and TX2
> enabled so use the
> + * values from table for which TX1 and TX2 enabled.
> + */
> + for (ln = 0; ln < 2; ln++) {
> + val = I915_READ(MG_CLKHUB(port, ln));
> + if (link_clock < 300000)
> + val |= CFG_LOW_RATE_LKREN_EN;
> + else
> + val &= ~CFG_LOW_RATE_LKREN_EN;
> + I915_WRITE(MG_CLKHUB(port, ln), val);
> + }
> +
> + /* Program the MG_TX_DCC<LN, port being used> based on the
> link frequency */
> + for (ln = 0; ln < 2; ln++) {
> + val = I915_READ(MG_TX1_DCC(port, ln));
> + val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
> + if (link_clock <= 500000) {
> + val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
> + } else {
> + val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
> + CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
> + }
> + I915_WRITE(MG_TX1_DCC(port, ln), val);
> +
> + val = I915_READ(MG_TX2_DCC(port, ln));
> + val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
> + if (link_clock <= 500000) {
> + val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
> + } else {
> + val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
> + CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
> + }
> + I915_WRITE(MG_TX2_DCC(port, ln), val);
> + }
> +
> + /* Program MG_TX_PISO_READLOAD with values from vswing table
> */
> + for (ln = 0; ln < 2; ln++) {
> + val = I915_READ(MG_TX1_PISO_READLOAD(port, ln));
> + val |= CRI_CALCINIT;
> + I915_WRITE(MG_TX1_PISO_READLOAD(port, ln), val);
> +
> + val = I915_READ(MG_TX2_PISO_READLOAD(port, ln));
> + val |= CRI_CALCINIT;
> + I915_WRITE(MG_TX2_PISO_READLOAD(port, ln), val);
> + }
> +}
> +
> +static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
> + int link_clock,
> + u32 level,
> enum intel_output_type type)
> {
> enum port port = encoder->port;
> @@ -2467,8 +2588,7 @@ static void icl_ddi_vswing_sequence(struct
> intel_encoder *encoder, u32 level,
> if (port == PORT_A || port == PORT_B)
> icl_combo_phy_ddi_vswing_sequence(encoder, level,
> type);
> else
> - /* Not Implemented Yet */
> - WARN_ON(1);
> + icl_mg_phy_ddi_vswing_sequence(encoder, link_clock,
> level);
> }
>
> static uint32_t translate_signal_level(int signal_levels)
> @@ -2503,7 +2623,8 @@ u32 bxt_signal_levels(struct intel_dp
> *intel_dp)
> int level = intel_ddi_dp_level(intel_dp);
>
> if (IS_ICELAKE(dev_priv))
> - icl_ddi_vswing_sequence(encoder, level, encoder-
> >type);
> + icl_ddi_vswing_sequence(encoder, intel_dp-
> >link_rate,
> + level, encoder->type);
> else if (IS_CANNONLAKE(dev_priv))
> cnl_ddi_vswing_sequence(encoder, level, encoder-
> >type);
> else
> @@ -2684,7 +2805,8 @@ static void intel_ddi_pre_enable_dp(struct
> intel_encoder *encoder,
> intel_display_power_get(dev_priv, dig_port-
> >ddi_io_power_domain);
>
> if (IS_ICELAKE(dev_priv))
> - icl_ddi_vswing_sequence(encoder, level, encoder-
> >type);
> + icl_ddi_vswing_sequence(encoder, crtc_state-
> >port_clock,
> + level, encoder->type);
> else if (IS_CANNONLAKE(dev_priv))
> cnl_ddi_vswing_sequence(encoder, level, encoder-
> >type);
> else if (IS_GEN9_LP(dev_priv))
> @@ -2719,7 +2841,8 @@ static void intel_ddi_pre_enable_hdmi(struct
> intel_encoder *encoder,
> intel_display_power_get(dev_priv, dig_port-
> >ddi_io_power_domain);
>
> if (IS_ICELAKE(dev_priv))
> - icl_ddi_vswing_sequence(encoder, level,
> INTEL_OUTPUT_HDMI);
> + icl_ddi_vswing_sequence(encoder, crtc_state-
> >port_clock,
> + level, INTEL_OUTPUT_HDMI);
> else if (IS_CANNONLAKE(dev_priv))
> cnl_ddi_vswing_sequence(encoder, level,
> INTEL_OUTPUT_HDMI);
> else if (IS_GEN9_LP(dev_priv))
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^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2018-07-16 23:48 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-06-28 22:35 [PATCH v2 1/2] drm/i915/icl: Add remaining registers and bitfields for MG PHY DDI Manasi Navare
2018-06-28 22:35 ` [PATCH v2 2/2] drm/i915/icl: Implement voltage swing programming sequence " Manasi Navare
2018-07-16 23:48 ` Paulo Zanoni
2018-06-28 23:26 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/2] drm/i915/icl: Add remaining registers and bitfields " Patchwork
2018-06-28 23:42 ` ✓ Fi.CI.BAT: success " Patchwork
2018-06-29 5:46 ` ✓ Fi.CI.IGT: " Patchwork
2018-06-29 20:47 ` [PATCH v2 1/2] " Srivatsa, Anusha
2018-06-29 21:33 ` ✗ Fi.CI.BAT: failure for series starting with [v2,1/2] drm/i915/icl: Add remaining registers and bitfields for MG PHY DDI (rev2) Patchwork
2018-07-03 18:07 ` [PATCH v2 1/2] drm/i915/icl: Add remaining registers and bitfields for MG PHY DDI Srivatsa, Anusha
2018-07-13 0:00 ` Paulo Zanoni
2018-07-13 18:44 ` Manasi Navare
2018-07-13 19:43 ` [PATCH v3] " Manasi Navare
2018-07-16 21:01 ` Paulo Zanoni
2018-07-13 19:50 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3] drm/i915/icl: Add remaining registers and bitfields for MG PHY DDI (rev3) Patchwork
2018-07-13 20:06 ` ✓ Fi.CI.BAT: success " Patchwork
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