* [U-Boot] [PATCH 01/53] move data structure out of cpu.h
2018-10-03 10:44 [U-Boot] [PATCH 00/53] TF-A Boot support for NXP Chassis 2 platforms Rajesh Bhagat
@ 2018-10-03 10:44 ` Rajesh Bhagat
2018-10-03 10:44 ` [U-Boot] [PATCH 02/53] env: allow flash and nand env driver to compile together Rajesh Bhagat
` (28 subsequent siblings)
29 siblings, 0 replies; 32+ messages in thread
From: Rajesh Bhagat @ 2018-10-03 10:44 UTC (permalink / raw)
To: u-boot
From: York Sun <york.sun@nxp.com>
Move static definitions to cpu.c file, as it doesn't allow
the cpu.h file to be included in multiple c files.
Signed-off-by: York Sun <york.sun@nxp.com>
---
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 297 +++++++++++++++++
.../arm/include/asm/arch-fsl-layerscape/cpu.h | 300 ------------------
2 files changed, 297 insertions(+), 300 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 052e0708d4..bae50f68d8 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -33,6 +33,303 @@
DECLARE_GLOBAL_DATA_PTR;
+static struct cpu_type cpu_type_list[] = {
+ CPU_TYPE_ENTRY(LS2080A, LS2080A, 8),
+ CPU_TYPE_ENTRY(LS2085A, LS2085A, 8),
+ CPU_TYPE_ENTRY(LS2045A, LS2045A, 4),
+ CPU_TYPE_ENTRY(LS2088A, LS2088A, 8),
+ CPU_TYPE_ENTRY(LS2084A, LS2084A, 8),
+ CPU_TYPE_ENTRY(LS2048A, LS2048A, 4),
+ CPU_TYPE_ENTRY(LS2044A, LS2044A, 4),
+ CPU_TYPE_ENTRY(LS2081A, LS2081A, 8),
+ CPU_TYPE_ENTRY(LS2041A, LS2041A, 4),
+ CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
+ CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
+ CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
+ CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
+ CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
+ CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
+ CPU_TYPE_ENTRY(LS1088A, LS1088A, 8),
+ CPU_TYPE_ENTRY(LS1084A, LS1084A, 8),
+ CPU_TYPE_ENTRY(LS1048A, LS1048A, 4),
+ CPU_TYPE_ENTRY(LS1044A, LS1044A, 4),
+};
+
+#define EARLY_PGTABLE_SIZE 0x5000
+static struct mm_region early_map[] = {
+#ifdef CONFIG_FSL_LSCH3
+ { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
+ CONFIG_SYS_FSL_CCSR_SIZE,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
+ SYS_FSL_OCRAM_SPACE_SIZE,
+ PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
+ },
+ { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
+ CONFIG_SYS_FSL_QSPI_SIZE1,
+ PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE},
+#ifdef CONFIG_FSL_IFC
+ /* For IFC Region #1, only the first 4MB is cache-enabled */
+ { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
+ CONFIG_SYS_FSL_IFC_SIZE1_1,
+ PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
+ },
+ { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
+ CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
+ CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
+ },
+ { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
+ CONFIG_SYS_FSL_IFC_SIZE1,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
+ },
+#endif
+ { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
+ CONFIG_SYS_FSL_DRAM_SIZE1,
+#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+ PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+#else /* Start with nGnRnE and PXN and UXN to prevent speculative access */
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
+#endif
+ PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
+ },
+#ifdef CONFIG_FSL_IFC
+ /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
+ { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
+ CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
+ },
+#endif
+ { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
+ CONFIG_SYS_FSL_DCSR_SIZE,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
+ CONFIG_SYS_FSL_DRAM_SIZE2,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
+ PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
+ },
+#elif defined(CONFIG_FSL_LSCH2)
+ { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
+ CONFIG_SYS_FSL_CCSR_SIZE,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
+ SYS_FSL_OCRAM_SPACE_SIZE,
+ PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
+ },
+ { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
+ CONFIG_SYS_FSL_DCSR_SIZE,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
+ CONFIG_SYS_FSL_QSPI_SIZE,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
+ },
+#ifdef CONFIG_FSL_IFC
+ { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
+ CONFIG_SYS_FSL_IFC_SIZE,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
+ },
+#endif
+ { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
+ CONFIG_SYS_FSL_DRAM_SIZE1,
+#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+ PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+#else /* Start with nGnRnE and PXN and UXN to prevent speculative access */
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
+#endif
+ PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
+ },
+ { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
+ CONFIG_SYS_FSL_DRAM_SIZE2,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
+ PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
+ },
+#endif
+ {}, /* list terminator */
+};
+
+static struct mm_region final_map[] = {
+#ifdef CONFIG_FSL_LSCH3
+ { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
+ CONFIG_SYS_FSL_CCSR_SIZE,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
+ SYS_FSL_OCRAM_SPACE_SIZE,
+ PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
+ },
+ { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
+ CONFIG_SYS_FSL_DRAM_SIZE1,
+ PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
+ },
+ { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
+ CONFIG_SYS_FSL_QSPI_SIZE1,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
+ CONFIG_SYS_FSL_QSPI_SIZE2,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+#ifdef CONFIG_FSL_IFC
+ { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
+ CONFIG_SYS_FSL_IFC_SIZE2,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+#endif
+ { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
+ CONFIG_SYS_FSL_DCSR_SIZE,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
+ CONFIG_SYS_FSL_MC_SIZE,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
+ CONFIG_SYS_FSL_NI_SIZE,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ /* For QBMAN portal, only the first 64MB is cache-enabled */
+ { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
+ CONFIG_SYS_FSL_QBMAN_SIZE_1,
+ PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS
+ },
+ { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
+ CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
+ CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
+ CONFIG_SYS_PCIE1_PHYS_SIZE,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
+ CONFIG_SYS_PCIE2_PHYS_SIZE,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
+ CONFIG_SYS_PCIE3_PHYS_SIZE,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+#ifdef CONFIG_ARCH_LS2080A
+ { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
+ CONFIG_SYS_PCIE4_PHYS_SIZE,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+#endif
+ { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
+ CONFIG_SYS_FSL_WRIOP1_SIZE,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
+ CONFIG_SYS_FSL_AIOP1_SIZE,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
+ CONFIG_SYS_FSL_PEBUF_SIZE,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
+ CONFIG_SYS_FSL_DRAM_SIZE2,
+ PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
+ },
+#elif defined(CONFIG_FSL_LSCH2)
+ { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
+ CONFIG_SYS_FSL_BOOTROM_SIZE,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
+ CONFIG_SYS_FSL_CCSR_SIZE,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
+ SYS_FSL_OCRAM_SPACE_SIZE,
+ PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
+ },
+ { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
+ CONFIG_SYS_FSL_DCSR_SIZE,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
+ CONFIG_SYS_FSL_QSPI_SIZE,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+#ifdef CONFIG_FSL_IFC
+ { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
+ CONFIG_SYS_FSL_IFC_SIZE,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
+ },
+#endif
+ { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
+ CONFIG_SYS_FSL_DRAM_SIZE1,
+ PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
+ },
+ { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
+ CONFIG_SYS_FSL_QBMAN_SIZE,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
+ CONFIG_SYS_FSL_DRAM_SIZE2,
+ PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
+ },
+ { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
+ CONFIG_SYS_PCIE1_PHYS_SIZE,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
+ CONFIG_SYS_PCIE2_PHYS_SIZE,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
+ CONFIG_SYS_PCIE3_PHYS_SIZE,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
+ CONFIG_SYS_FSL_DRAM_SIZE3,
+ PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
+ },
+#endif
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+ {}, /* space holder for secure mem */
+#endif
+ {},
+};
+
struct mm_region *mem_map = early_map;
void cpu_name(char *name)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index 48d0ab163a..3926aa3039 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -7,30 +7,6 @@
#ifndef _FSL_LAYERSCAPE_CPU_H
#define _FSL_LAYERSCAPE_CPU_H
-static struct cpu_type cpu_type_list[] = {
- CPU_TYPE_ENTRY(LS2080A, LS2080A, 8),
- CPU_TYPE_ENTRY(LS2085A, LS2085A, 8),
- CPU_TYPE_ENTRY(LS2045A, LS2045A, 4),
- CPU_TYPE_ENTRY(LS2088A, LS2088A, 8),
- CPU_TYPE_ENTRY(LS2084A, LS2084A, 8),
- CPU_TYPE_ENTRY(LS2048A, LS2048A, 4),
- CPU_TYPE_ENTRY(LS2044A, LS2044A, 4),
- CPU_TYPE_ENTRY(LS2081A, LS2081A, 8),
- CPU_TYPE_ENTRY(LS2041A, LS2041A, 4),
- CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
- CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
- CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
- CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
- CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
- CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
- CPU_TYPE_ENTRY(LS1088A, LS1088A, 8),
- CPU_TYPE_ENTRY(LS1084A, LS1084A, 8),
- CPU_TYPE_ENTRY(LS1048A, LS1048A, 4),
- CPU_TYPE_ENTRY(LS1044A, LS1044A, 4),
-};
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-
#ifdef CONFIG_FSL_LSCH3
#define CONFIG_SYS_FSL_CCSR_BASE 0x00000000
#define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000
@@ -90,282 +66,6 @@ static struct cpu_type cpu_type_list[] = {
#define CONFIG_SYS_FSL_DRAM_SIZE3 0x7800000000 /* 480GB */
#endif
-#define EARLY_PGTABLE_SIZE 0x5000
-static struct mm_region early_map[] = {
-#ifdef CONFIG_FSL_LSCH3
- { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
- CONFIG_SYS_FSL_CCSR_SIZE,
- PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
- },
- { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
- SYS_FSL_OCRAM_SPACE_SIZE,
- PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
- },
- { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
- CONFIG_SYS_FSL_QSPI_SIZE1,
- PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE},
-#ifdef CONFIG_FSL_IFC
- /* For IFC Region #1, only the first 4MB is cache-enabled */
- { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
- CONFIG_SYS_FSL_IFC_SIZE1_1,
- PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
- },
- { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
- CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
- CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
- PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
- },
- { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
- CONFIG_SYS_FSL_IFC_SIZE1,
- PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
- },
-#endif
- { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
- CONFIG_SYS_FSL_DRAM_SIZE1,
-#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
- PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-#else /* Start with nGnRnE and PXN and UXN to prevent speculative access */
- PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
-#endif
- PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
- },
-#ifdef CONFIG_FSL_IFC
- /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
- { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
- CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
- PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
- },
-#endif
- { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
- CONFIG_SYS_FSL_DCSR_SIZE,
- PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
- },
- { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
- CONFIG_SYS_FSL_DRAM_SIZE2,
- PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
- PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
- },
-#elif defined(CONFIG_FSL_LSCH2)
- { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
- CONFIG_SYS_FSL_CCSR_SIZE,
- PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
- },
- { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
- SYS_FSL_OCRAM_SPACE_SIZE,
- PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
- },
- { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
- CONFIG_SYS_FSL_DCSR_SIZE,
- PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
- },
- { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
- CONFIG_SYS_FSL_QSPI_SIZE,
- PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
- },
-#ifdef CONFIG_FSL_IFC
- { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
- CONFIG_SYS_FSL_IFC_SIZE,
- PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
- },
-#endif
- { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
- CONFIG_SYS_FSL_DRAM_SIZE1,
-#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
- PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-#else /* Start with nGnRnE and PXN and UXN to prevent speculative access */
- PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
-#endif
- PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
- },
- { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
- CONFIG_SYS_FSL_DRAM_SIZE2,
- PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
- PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
- },
-#endif
- {}, /* list terminator */
-};
-
-static struct mm_region final_map[] = {
-#ifdef CONFIG_FSL_LSCH3
- { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
- CONFIG_SYS_FSL_CCSR_SIZE,
- PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
- },
- { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
- SYS_FSL_OCRAM_SPACE_SIZE,
- PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
- },
- { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
- CONFIG_SYS_FSL_DRAM_SIZE1,
- PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
- },
- { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
- CONFIG_SYS_FSL_QSPI_SIZE1,
- PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
- },
- { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
- CONFIG_SYS_FSL_QSPI_SIZE2,
- PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
- },
-#ifdef CONFIG_FSL_IFC
- { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
- CONFIG_SYS_FSL_IFC_SIZE2,
- PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
- },
-#endif
- { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
- CONFIG_SYS_FSL_DCSR_SIZE,
- PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
- },
- { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
- CONFIG_SYS_FSL_MC_SIZE,
- PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
- },
- { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
- CONFIG_SYS_FSL_NI_SIZE,
- PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
- },
- /* For QBMAN portal, only the first 64MB is cache-enabled */
- { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
- CONFIG_SYS_FSL_QBMAN_SIZE_1,
- PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS
- },
- { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
- CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
- CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
- PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
- },
- { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
- CONFIG_SYS_PCIE1_PHYS_SIZE,
- PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
- },
- { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
- CONFIG_SYS_PCIE2_PHYS_SIZE,
- PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
- },
- { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
- CONFIG_SYS_PCIE3_PHYS_SIZE,
- PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
- },
-#ifdef CONFIG_ARCH_LS2080A
- { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
- CONFIG_SYS_PCIE4_PHYS_SIZE,
- PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
- },
-#endif
- { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
- CONFIG_SYS_FSL_WRIOP1_SIZE,
- PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
- },
- { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
- CONFIG_SYS_FSL_AIOP1_SIZE,
- PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
- },
- { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
- CONFIG_SYS_FSL_PEBUF_SIZE,
- PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
- },
- { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
- CONFIG_SYS_FSL_DRAM_SIZE2,
- PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
- },
-#elif defined(CONFIG_FSL_LSCH2)
- { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
- CONFIG_SYS_FSL_BOOTROM_SIZE,
- PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
- },
- { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
- CONFIG_SYS_FSL_CCSR_SIZE,
- PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
- },
- { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
- SYS_FSL_OCRAM_SPACE_SIZE,
- PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
- },
- { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
- CONFIG_SYS_FSL_DCSR_SIZE,
- PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
- },
- { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
- CONFIG_SYS_FSL_QSPI_SIZE,
- PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
- },
-#ifdef CONFIG_FSL_IFC
- { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
- CONFIG_SYS_FSL_IFC_SIZE,
- PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
- },
-#endif
- { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
- CONFIG_SYS_FSL_DRAM_SIZE1,
- PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
- },
- { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
- CONFIG_SYS_FSL_QBMAN_SIZE,
- PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
- },
- { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
- CONFIG_SYS_FSL_DRAM_SIZE2,
- PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
- },
- { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
- CONFIG_SYS_PCIE1_PHYS_SIZE,
- PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
- },
- { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
- CONFIG_SYS_PCIE2_PHYS_SIZE,
- PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
- },
- { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
- CONFIG_SYS_PCIE3_PHYS_SIZE,
- PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
- },
- { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
- CONFIG_SYS_FSL_DRAM_SIZE3,
- PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
- },
-#endif
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
- {}, /* space holder for secure mem */
-#endif
- {},
-};
-#endif /* !CONFIG_SYS_DCACHE_OFF */
-
int fsl_qoriq_core_to_cluster(unsigned int core);
u32 cpu_mask(void);
--
2.17.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [U-Boot] [PATCH 02/53] env: allow flash and nand env driver to compile together
2018-10-03 10:44 [U-Boot] [PATCH 00/53] TF-A Boot support for NXP Chassis 2 platforms Rajesh Bhagat
2018-10-03 10:44 ` [U-Boot] [PATCH 01/53] move data structure out of cpu.h Rajesh Bhagat
@ 2018-10-03 10:44 ` Rajesh Bhagat
2018-10-03 10:44 ` [U-Boot] [PATCH 03/53] env: sf: define API to override sf environment address Rajesh Bhagat
` (27 subsequent siblings)
29 siblings, 0 replies; 32+ messages in thread
From: Rajesh Bhagat @ 2018-10-03 10:44 UTC (permalink / raw)
To: u-boot
Define env_ptr as static in flash and nand env driver to
allow these to compile together.
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
---
env/flash.c | 4 ++--
env/nand.c | 6 +++---
include/environment.h | 1 -
3 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/env/flash.c b/env/flash.c
index 32236c716e..33b199f05b 100644
--- a/env/flash.c
+++ b/env/flash.c
@@ -45,13 +45,13 @@ DECLARE_GLOBAL_DATA_PTR;
#endif
#ifdef ENV_IS_EMBEDDED
-env_t *env_ptr = &environment;
+static env_t *env_ptr = &environment;
static __maybe_unused env_t *flash_addr = (env_t *)CONFIG_ENV_ADDR;
#else /* ! ENV_IS_EMBEDDED */
-env_t *env_ptr = (env_t *)CONFIG_ENV_ADDR;
+static env_t *env_ptr = (env_t *)CONFIG_ENV_ADDR;
static __maybe_unused env_t *flash_addr = (env_t *)CONFIG_ENV_ADDR;
#endif /* ENV_IS_EMBEDDED */
diff --git a/env/nand.c b/env/nand.c
index 3698e68957..4d04bbb164 100644
--- a/env/nand.c
+++ b/env/nand.c
@@ -40,11 +40,11 @@
#endif
#if defined(ENV_IS_EMBEDDED)
-env_t *env_ptr = &environment;
+static env_t *env_ptr = &environment;
#elif defined(CONFIG_NAND_ENV_DST)
-env_t *env_ptr = (env_t *)CONFIG_NAND_ENV_DST;
+static env_t *env_ptr = (env_t *)CONFIG_NAND_ENV_DST;
#else /* ! ENV_IS_EMBEDDED */
-env_t *env_ptr;
+static env_t *env_ptr;
#endif /* ENV_IS_EMBEDDED */
DECLARE_GLOBAL_DATA_PTR;
diff --git a/include/environment.h b/include/environment.h
index 5e90f157e8..7da1291d5b 100644
--- a/include/environment.h
+++ b/include/environment.h
@@ -157,7 +157,6 @@ extern env_t environment;
#endif /* ENV_IS_EMBEDDED */
extern const unsigned char default_environment[];
-extern env_t *env_ptr;
#if defined(CONFIG_NEEDS_MANUAL_RELOC)
extern void env_reloc(void);
--
2.17.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [U-Boot] [PATCH 03/53] env: sf: define API to override sf environment address
2018-10-03 10:44 [U-Boot] [PATCH 00/53] TF-A Boot support for NXP Chassis 2 platforms Rajesh Bhagat
2018-10-03 10:44 ` [U-Boot] [PATCH 01/53] move data structure out of cpu.h Rajesh Bhagat
2018-10-03 10:44 ` [U-Boot] [PATCH 02/53] env: allow flash and nand env driver to compile together Rajesh Bhagat
@ 2018-10-03 10:44 ` Rajesh Bhagat
2018-10-03 10:44 ` [U-Boot] [PATCH 04/53] env: nand: remove unnecessary env_ptr definition Rajesh Bhagat
` (26 subsequent siblings)
29 siblings, 0 replies; 32+ messages in thread
From: Rajesh Bhagat @ 2018-10-03 10:44 UTC (permalink / raw)
To: u-boot
Defines env_sf_get_env_addr API to override sf environment address,
required to support multiple environment.
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
---
env/sf.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/env/sf.c b/env/sf.c
index 494510533a..df22fd520b 100644
--- a/env/sf.c
+++ b/env/sf.c
@@ -297,10 +297,17 @@ out:
}
#endif
+#ifdef CONFIG_ENV_ADDR
+__weak void *env_sf_get_env_addr(void)
+{
+ return (void *)CONFIG_ENV_ADDR;
+}
+#endif
+
#if defined(INITENV) && defined(CONFIG_ENV_ADDR)
static int env_sf_init(void)
{
- env_t *env_ptr = (env_t *)(CONFIG_ENV_ADDR);
+ env_t *env_ptr = (env_t *)env_sf_get_env_addr();
if (crc32(0, env_ptr->data, ENV_SIZE) == env_ptr->crc) {
gd->env_addr = (ulong)&(env_ptr->data);
--
2.17.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [U-Boot] [PATCH 04/53] env: nand: remove unnecessary env_ptr definition
2018-10-03 10:44 [U-Boot] [PATCH 00/53] TF-A Boot support for NXP Chassis 2 platforms Rajesh Bhagat
` (2 preceding siblings ...)
2018-10-03 10:44 ` [U-Boot] [PATCH 03/53] env: sf: define API to override sf environment address Rajesh Bhagat
@ 2018-10-03 10:44 ` Rajesh Bhagat
2018-10-03 10:44 ` [U-Boot] [PATCH 05/53] armv8: layerscape: add TFABOOT config option Rajesh Bhagat
` (25 subsequent siblings)
29 siblings, 0 replies; 32+ messages in thread
From: Rajesh Bhagat @ 2018-10-03 10:44 UTC (permalink / raw)
To: u-boot
env_ptr is not used when ENV_IS_EMBEDDED and CONFIG_NAND_ENV_DST
is not defined. Hence, remove it.
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
---
env/nand.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/env/nand.c b/env/nand.c
index 4d04bbb164..29eda66fad 100644
--- a/env/nand.c
+++ b/env/nand.c
@@ -43,8 +43,6 @@
static env_t *env_ptr = &environment;
#elif defined(CONFIG_NAND_ENV_DST)
static env_t *env_ptr = (env_t *)CONFIG_NAND_ENV_DST;
-#else /* ! ENV_IS_EMBEDDED */
-static env_t *env_ptr;
#endif /* ENV_IS_EMBEDDED */
DECLARE_GLOBAL_DATA_PTR;
--
2.17.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [U-Boot] [PATCH 05/53] armv8: layerscape: add TFABOOT config option
2018-10-03 10:44 [U-Boot] [PATCH 00/53] TF-A Boot support for NXP Chassis 2 platforms Rajesh Bhagat
` (3 preceding siblings ...)
2018-10-03 10:44 ` [U-Boot] [PATCH 04/53] env: nand: remove unnecessary env_ptr definition Rajesh Bhagat
@ 2018-10-03 10:44 ` Rajesh Bhagat
2018-10-03 10:44 ` [U-Boot] [PATCH 06/53] armv8: fsl-layerscape: identify boot source from PORSR register Rajesh Bhagat
` (24 subsequent siblings)
29 siblings, 0 replies; 32+ messages in thread
From: Rajesh Bhagat @ 2018-10-03 10:44 UTC (permalink / raw)
To: u-boot
Adds TFABOOT config option for u-boot to be loaded by trusted
firmware.
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
---
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index f2111fadc0..9092757d1f 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -514,3 +514,10 @@ config HAS_FSL_XHCI_USB
help
For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
pins, select it when the pins are assigned to USB.
+
+config TFABOOT
+ bool "Support for booting from TFA"
+ default n
+ help
+ Enabling this will make a U-Boot binary that is capable of being
+ booted via TFA.
--
2.17.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [U-Boot] [PATCH 06/53] armv8: fsl-layerscape: identify boot source from PORSR register
2018-10-03 10:44 [U-Boot] [PATCH 00/53] TF-A Boot support for NXP Chassis 2 platforms Rajesh Bhagat
` (4 preceding siblings ...)
2018-10-03 10:44 ` [U-Boot] [PATCH 05/53] armv8: layerscape: add TFABOOT config option Rajesh Bhagat
@ 2018-10-03 10:44 ` Rajesh Bhagat
2018-10-03 10:44 ` [U-Boot] [PATCH 07/53] armv8: ls1046ardb: Add TFABOOT defconfig Rajesh Bhagat
` (23 subsequent siblings)
29 siblings, 0 replies; 32+ messages in thread
From: Rajesh Bhagat @ 2018-10-03 10:44 UTC (permalink / raw)
To: u-boot
PORSR register holds the cfg_rcw_src field which can be used
to identify boot source.
Further, it can be used to select the environment location.
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
---
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 190 ++++++++++++++++++
.../asm/arch-fsl-layerscape/immap_lsch2.h | 20 ++
.../asm/arch-fsl-layerscape/immap_lsch3.h | 49 +++++
.../arm/include/asm/arch-fsl-layerscape/soc.h | 17 ++
4 files changed, 276 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index bae50f68d8..3b4f110027 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -31,6 +31,10 @@
#include <hwconfig.h>
#include <fsl_qbman.h>
+#ifdef CONFIG_TFABOOT
+#include <environment.h>
+#endif
+
DECLARE_GLOBAL_DATA_PTR;
static struct cpu_type cpu_type_list[] = {
@@ -576,7 +580,193 @@ void enable_caches(void)
icache_enable();
dcache_enable();
}
+#endif /* CONFIG_SYS_DCACHE_OFF */
+
+#ifdef CONFIG_TFABOOT
+enum boot_src __get_boot_src(u32 porsr1)
+{
+ enum boot_src src = BOOT_SOURCE_RESERVED;
+ uint32_t rcw_src = (porsr1 & RCW_SRC_MASK) >> RCW_SRC_BIT;
+#if !defined(CONFIG_FSL_LSCH3_2)
+ uint32_t val;
+#endif
+ debug("%s: rcw_src 0x%x\n", __func__, rcw_src);
+
+#if defined(CONFIG_FSL_LSCH3)
+#if defined(CONFIG_FSL_LSCH3_2)
+ switch (rcw_src) {
+ case RCW_SRC_SDHC1_VAL:
+ src = BOOT_SOURCE_SD_MMC;
+ break;
+ case RCW_SRC_SDHC2_VAL:
+ src = BOOT_SOURCE_SD_MMC2;
+ break;
+ case RCW_SRC_I2C1_VAL:
+ src = BOOT_SOURCE_I2C1_EXTENDED;
+ break;
+ case RCW_SRC_FLEXSPI_NAND2K_VAL:
+ src = BOOT_SOURCE_XSPI_NAND;
+ break;
+ case RCW_SRC_FLEXSPI_NAND4K_VAL:
+ src = BOOT_SOURCE_XSPI_NAND;
+ break;
+ case RCW_SRC_RESERVED_1_VAL:
+ src = BOOT_SOURCE_RESERVED;
+ break;
+ case RCW_SRC_FLEXSPI_NOR_24B:
+ src = BOOT_SOURCE_XSPI_NOR;
+ break;
+ default:
+ src = BOOT_SOURCE_RESERVED;
+ }
+#else
+ val = rcw_src & RCW_SRC_TYPE_MASK;
+ if (val == RCW_SRC_NOR_VAL) {
+ val = rcw_src & NOR_TYPE_MASK;
+
+ switch (val) {
+ case NOR_16B_VAL:
+ case NOR_32B_VAL:
+ src = BOOT_SOURCE_IFC_NOR;
+ break;
+ default:
+ src = BOOT_SOURCE_RESERVED;
+ }
+ } else {
+ /* RCW SRC Serial Flash */
+ val = rcw_src & RCW_SRC_SERIAL_MASK;
+ switch (val) {
+ case RCW_SRC_QSPI_VAL:
+ /* RCW SRC Serial NOR (QSPI) */
+ src = BOOT_SOURCE_QSPI_NOR;
+ break;
+ case RCW_SRC_SD_CARD_VAL:
+ /* RCW SRC SD Card */
+ src = BOOT_SOURCE_SD_MMC;
+ break;
+ case RCW_SRC_EMMC_VAL:
+ /* RCW SRC EMMC */
+ src = BOOT_SOURCE_SD_MMC2;
+ break;
+ case RCW_SRC_I2C1_VAL:
+ /* RCW SRC I2C1 Extended */
+ src = BOOT_SOURCE_I2C1_EXTENDED;
+ break;
+ default:
+ src = BOOT_SOURCE_RESERVED;
+ }
+ }
+#endif
+#elif defined(CONFIG_FSL_LSCH2)
+ /* RCW SRC NAND */
+ val = rcw_src & RCW_SRC_NAND_MASK;
+ if (val == RCW_SRC_NAND_VAL) {
+ val = rcw_src & NAND_RESERVED_MASK;
+ if ((val != NAND_RESERVED_1) && (val != NAND_RESERVED_2)) {
+ src = BOOT_SOURCE_IFC_NAND;
+ }
+ } else {
+ /* RCW SRC NOR */
+ val = rcw_src & RCW_SRC_NOR_MASK;
+ if (val == NOR_8B_VAL || val == NOR_16B_VAL) {
+ src = BOOT_SOURCE_IFC_NOR;
+ } else {
+ switch (rcw_src) {
+ case QSPI_VAL1:
+ case QSPI_VAL2:
+ src = BOOT_SOURCE_QSPI_NOR;
+ break;
+ case SD_VAL:
+ src = BOOT_SOURCE_SD_MMC;
+ break;
+ default:
+ src = BOOT_SOURCE_RESERVED;
+ }
+ }
+ }
#endif
+ debug("%s: src 0x%x\n", __func__, src);
+ return src;
+}
+
+enum boot_src get_boot_src(void)
+{
+ u32 porsr1;
+
+#if defined(CONFIG_FSL_LSCH3)
+ u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
+
+ porsr1 = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
+#elif defined(CONFIG_FSL_LSCH2)
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+
+ porsr1 = in_be32(&gur->porsr1);
+#endif
+ debug("%s: porsr1 0x%x\n", __func__, porsr1);
+
+ return __get_boot_src(porsr1);
+}
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+int mmc_get_env_dev(void)
+{
+ enum boot_src src = get_boot_src();
+ int dev = CONFIG_SYS_MMC_ENV_DEV;
+
+ switch (src) {
+ case BOOT_SOURCE_SD_MMC:
+ dev = 0;
+ break;
+ case BOOT_SOURCE_SD_MMC2:
+ dev = 1;
+ break;
+ default:
+ break;
+ }
+
+ return dev;
+}
+#endif
+
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+ enum boot_src src = get_boot_src();
+ enum env_location env_loc = ENVL_NOWHERE;
+
+ if (prio)
+ return ENVL_UNKNOWN;
+
+ switch (src) {
+ case BOOT_SOURCE_IFC_NOR:
+ env_loc = ENVL_FLASH;
+ break;
+ case BOOT_SOURCE_QSPI_NOR:
+ /* FALLTHROUGH */
+ case BOOT_SOURCE_XSPI_NOR:
+ env_loc = ENVL_SPI_FLASH;
+ break;
+ case BOOT_SOURCE_IFC_NAND:
+ /* FALLTHROUGH */
+ case BOOT_SOURCE_QSPI_NAND:
+ /* FALLTHROUGH */
+ case BOOT_SOURCE_XSPI_NAND:
+ env_loc = ENVL_NAND;
+ break;
+ case BOOT_SOURCE_SD_MMC:
+ /* FALLTHROUGH */
+ case BOOT_SOURCE_SD_MMC2:
+ env_loc = ENVL_MMC;
+ break;
+ case BOOT_SOURCE_I2C1_EXTENDED:
+ /* FALLTHROUGH */
+ default:
+ break;
+ }
+
+
+ return env_loc;
+}
+#endif /* CONFIG_TFABOOT */
u32 initiator_type(u32 cluster, int init_id)
{
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index be0a6ae363..16528911d7 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -675,6 +675,26 @@ struct ccsr_gpio {
#define SCR0_CLIENTPD_MASK 0x00000001
#define SCR0_USFCFG_MASK 0x00000400
+#ifdef CONFIG_TFABOOT
+#define RCW_SRC_MASK (0xFF800000)
+#define RCW_SRC_BIT 23
+
+/* RCW SRC NAND */
+#define RCW_SRC_NAND_MASK (0x100)
+#define RCW_SRC_NAND_VAL (0x100)
+#define NAND_RESERVED_MASK (0xFC)
+#define NAND_RESERVED_1 (0x0)
+#define NAND_RESERVED_2 (0x80)
+
+/* RCW SRC NOR */
+#define RCW_SRC_NOR_MASK (0x1F0)
+#define NOR_8B_VAL (0x10)
+#define NOR_16B_VAL (0x20)
+#define SD_VAL (0x40)
+#define QSPI_VAL1 (0x44)
+#define QSPI_VAL2 (0x45)
+#endif
+
uint get_svr(void);
#endif /* __ARCH_FSL_LSCH2_IMMAP_H__*/
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index b0cec74db0..816d960b2f 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -82,6 +82,55 @@
#define CONFIG_SYS_FSL_JR0_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
+#ifdef CONFIG_TFABOOT
+#ifdef CONFIG_FSL_LSCH3_2
+/* RCW_SRC field in Power-On Reset Control Register 1 */
+#define RCW_SRC_MASK 0x07800000
+#define RCW_SRC_BIT 23
+
+/* CFG_RCW_SRC[3:0] */
+#define RCW_SRC_TYPE_MASK 0x8
+#define RCW_SRC_ADDR_OFFSET_8MB 0x800000
+
+/* RCW SRC HARDCODED */
+#define RCW_SRC_HARDCODED_VAL 0x0 /* 0x00 - 0x07 */
+
+#define RCW_SRC_SDHC1_VAL 0x8 /* 0x8 */
+#define RCW_SRC_SDHC2_VAL 0x9 /* 0x9 */
+#define RCW_SRC_I2C1_VAL 0xa /* 0xa */
+#define RCW_SRC_RESERVED_UART_VAL 0xb /* 0xb */
+#define RCW_SRC_FLEXSPI_NAND2K_VAL 0xc /* 0xc */
+#define RCW_SRC_FLEXSPI_NAND4K_VAL 0xd /* 0xd */
+#define RCW_SRC_RESERVED_1_VAL 0xe /* 0xe */
+#define RCW_SRC_FLEXSPI_NOR_24B 0xf /* 0xf */
+#else
+#define RCW_SRC_MASK (0xFF800000)
+#define RCW_SRC_BIT 23
+/* CFG_RCW_SRC[6:0] */
+#define RCW_SRC_TYPE_MASK (0x70)
+
+/* RCW SRC HARDCODED */
+#define RCW_SRC_HARDCODED_VAL (0x10) /* 0x10 - 0x1f */
+/* Hardcoded will also have CFG_RCW_SRC[7] as 1. 0x90 - 0x9f */
+
+/* RCW SRC NOR */
+#define RCW_SRC_NOR_VAL (0x20)
+#define NOR_TYPE_MASK (0x10)
+#define NOR_16B_VAL (0x0) /* 0x20 - 0x2f */
+#define NOR_32B_VAL (0x10) /* 0x30 - 0x3f */
+
+/* RCW SRC Serial Flash
+ * 1. SERIAL NOR (QSPI)
+ * 2. OTHERS (SD/MMC, SPI, I2C1
+ */
+#define RCW_SRC_SERIAL_MASK (0x7F)
+#define RCW_SRC_QSPI_VAL (0x62) /* 0x62 */
+#define RCW_SRC_SD_CARD_VAL (0x40) /* 0x40 */
+#define RCW_SRC_EMMC_VAL (0x41) /* 0x41 */
+#define RCW_SRC_I2C1_VAL (0x49) /* 0x49 */
+#endif
+#endif
+
/* Security Monitor */
#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 61b6e4bf07..d327c7ba1f 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -53,6 +53,23 @@ struct cpu_type {
#define CPU_TYPE_ENTRY(n, v, nc) \
{ .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
+
+#ifdef CONFIG_TFABOOT
+enum boot_src {
+ BOOT_SOURCE_RESERVED = 0,
+ BOOT_SOURCE_IFC_NOR,
+ BOOT_SOURCE_IFC_NAND,
+ BOOT_SOURCE_QSPI_NOR,
+ BOOT_SOURCE_QSPI_NAND,
+ BOOT_SOURCE_XSPI_NOR,
+ BOOT_SOURCE_XSPI_NAND,
+ BOOT_SOURCE_SD_MMC,
+ BOOT_SOURCE_SD_MMC2,
+ BOOT_SOURCE_I2C1_EXTENDED,
+};
+
+enum boot_src get_boot_src(void);
+#endif
#endif
#define SVR_WO_E 0xFFFFFE
#define SVR_LS1012A 0x870400
--
2.17.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [U-Boot] [PATCH 07/53] armv8: ls1046ardb: Add TFABOOT defconfig
2018-10-03 10:44 [U-Boot] [PATCH 00/53] TF-A Boot support for NXP Chassis 2 platforms Rajesh Bhagat
` (5 preceding siblings ...)
2018-10-03 10:44 ` [U-Boot] [PATCH 06/53] armv8: fsl-layerscape: identify boot source from PORSR register Rajesh Bhagat
@ 2018-10-03 10:44 ` Rajesh Bhagat
2018-10-03 10:44 ` [U-Boot] [PATCH 08/53] armv8: ls1046aqds: " Rajesh Bhagat
` (22 subsequent siblings)
29 siblings, 0 replies; 32+ messages in thread
From: Rajesh Bhagat @ 2018-10-03 10:44 UTC (permalink / raw)
To: u-boot
This defconfig is for TFABOOT, to be loaded by trusted firmware.
Signed-off-by: York Sun <york.sun@nxp.com>
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
---
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 9 +++--
board/freescale/ls1046ardb/ddr.c | 3 +-
configs/ls1046ardb_ram_defconfig | 49 +++++++++++++++++++++++++
include/configs/ls1046a_common.h | 4 ++
4 files changed, 61 insertions(+), 4 deletions(-)
create mode 100644 configs/ls1046ardb_ram_defconfig
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 3b4f110027..1ab4d93638 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -92,7 +92,8 @@ static struct mm_region early_map[] = {
#endif
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
CONFIG_SYS_FSL_DRAM_SIZE1,
-#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_TFABOOT) || \
+ (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
#else /* Start with nGnRnE and PXN and UXN to prevent speculative access */
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
@@ -143,7 +144,8 @@ static struct mm_region early_map[] = {
#endif
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
CONFIG_SYS_FSL_DRAM_SIZE1,
-#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_TFABOOT) || \
+ (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
#else /* Start with nGnRnE and PXN and UXN to prevent speculative access */
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
@@ -1423,7 +1425,8 @@ void update_early_mmu_table(void)
__weak int dram_init(void)
{
fsl_initdram();
-#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+#if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
+ defined(CONFIG_SPL_BUILD)
/* This will break-before-make MMU for DDR */
update_early_mmu_table();
#endif
diff --git a/board/freescale/ls1046ardb/ddr.c b/board/freescale/ls1046ardb/ddr.c
index 82b1b1d9ea..8fe0794198 100644
--- a/board/freescale/ls1046ardb/ddr.c
+++ b/board/freescale/ls1046ardb/ddr.c
@@ -101,7 +101,8 @@ int fsl_initdram(void)
{
phys_size_t dram_size;
-#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_TFABOOT) || \
+ (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
gd->ram_size = fsl_ddr_sdram_size();
return 0;
diff --git a/configs/ls1046ardb_ram_defconfig b/configs/ls1046ardb_ram_defconfig
new file mode 100644
index 0000000000..5bc80ed24e
--- /dev/null
+++ b/configs/ls1046ardb_ram_defconfig
@@ -0,0 +1,49 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1046ARDB=y
+CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_QSPI_AHB_INIT=y
+CONFIG_TFABOOT=y
+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
+CONFIG_MISC_INIT_R=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_CACHE=y
+CONFIG_MP=y
+CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_DM=y
+CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
+CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_PHY_GIGE=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_STORAGE=y
diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h
index cdb73f644a..b6ec5bdf66 100644
--- a/include/configs/ls1046a_common.h
+++ b/include/configs/ls1046a_common.h
@@ -33,7 +33,11 @@
#include <asm/arch/stream_id_lsch2.h>
/* Link Definitions */
+#ifdef CONFIG_TFABOOT
+#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
+#else
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
+#endif
#define CONFIG_SKIP_LOWLEVEL_INIT
--
2.17.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [U-Boot] [PATCH 08/53] armv8: ls1046aqds: Add TFABOOT defconfig
2018-10-03 10:44 [U-Boot] [PATCH 00/53] TF-A Boot support for NXP Chassis 2 platforms Rajesh Bhagat
` (6 preceding siblings ...)
2018-10-03 10:44 ` [U-Boot] [PATCH 07/53] armv8: ls1046ardb: Add TFABOOT defconfig Rajesh Bhagat
@ 2018-10-03 10:44 ` Rajesh Bhagat
2018-10-03 10:44 ` [U-Boot] [PATCH 09/53] armv8: ls1046a: make environment address and size common Rajesh Bhagat
` (21 subsequent siblings)
29 siblings, 0 replies; 32+ messages in thread
From: Rajesh Bhagat @ 2018-10-03 10:44 UTC (permalink / raw)
To: u-boot
This defconfig is for TFABOOT, to be loaded by trusted firmware.
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
---
board/freescale/ls1046aqds/ddr.c | 3 +-
board/freescale/ls1046aqds/ls1046aqds.c | 15 ++++++-
configs/ls1046aqds_ram_defconfig | 57 +++++++++++++++++++++++++
include/configs/ls1046aqds.h | 3 +-
4 files changed, 75 insertions(+), 3 deletions(-)
create mode 100644 configs/ls1046aqds_ram_defconfig
diff --git a/board/freescale/ls1046aqds/ddr.c b/board/freescale/ls1046aqds/ddr.c
index 08f7610e69..d2afe62cfc 100644
--- a/board/freescale/ls1046aqds/ddr.c
+++ b/board/freescale/ls1046aqds/ddr.c
@@ -96,7 +96,8 @@ int fsl_initdram(void)
{
phys_size_t dram_size;
-#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_TFABOOT) || \
+ (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
gd->ram_size = fsl_ddr_sdram_size();
return 0;
diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c
index 0da82381af..77b21ac52a 100644
--- a/board/freescale/ls1046aqds/ls1046aqds.c
+++ b/board/freescale/ls1046aqds/ls1046aqds.c
@@ -38,6 +38,9 @@ enum {
int checkboard(void)
{
+#ifdef CONFIG_TFABOOT
+ enum boot_src src = get_boot_src();
+#endif
char buf[64];
#ifndef CONFIG_SD_BOOT
u8 sw;
@@ -45,6 +48,12 @@ int checkboard(void)
puts("Board: LS1046AQDS, boot from ");
+#ifdef CONFIG_TFABOOT
+ if (src == BOOT_SOURCE_SD_MMC)
+ puts("SD\n");
+ else {
+#endif
+
#ifdef CONFIG_SD_BOOT
puts("SD\n");
#else
@@ -63,6 +72,9 @@ int checkboard(void)
printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
#endif
+#ifdef CONFIG_TFABOOT
+ }
+#endif
printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
QIXIS_READ(id), QIXIS_READ(arch));
@@ -153,7 +165,8 @@ int dram_init(void)
*/
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
fsl_initdram();
-#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+#if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
+ defined(CONFIG_SPL_BUILD)
/* This will break-before-make MMU for DDR */
update_early_mmu_table();
#endif
diff --git a/configs/ls1046aqds_ram_defconfig b/configs/ls1046aqds_ram_defconfig
new file mode 100644
index 0000000000..c91bb76edf
--- /dev/null
+++ b/configs/ls1046aqds_ram_defconfig
@@ -0,0 +1,57 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1046AQDS=y
+CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_TFABOOT=y
+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m at 0x100000(nor_bank0_uboot),40m at 0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m at 0x4100000(nor_bank4_uboot),40m at 0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)"
+# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_MISC_INIT_R=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_CACHE=y
+CONFIG_MP=y
+CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m at 0x100000(nor_bank0_uboot),40m at 0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m at 0x4100000(nor_bank4_uboot),40m at 0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)"
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
+CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_DM=y
+CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_STORAGE=y
diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h
index 8edaf190d0..07e21469c8 100644
--- a/include/configs/ls1046aqds.h
+++ b/include/configs/ls1046aqds.h
@@ -50,7 +50,8 @@ unsigned long get_board_ddr_clk(void);
#endif
/* QSPI */
-#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#if defined(CONFIG_TFABOOT) || \
+ defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#ifdef CONFIG_FSL_QSPI
#define CONFIG_SPI_FLASH_SPANSION
#define FSL_QSPI_FLASH_SIZE (1 << 24)
--
2.17.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [U-Boot] [PATCH 09/53] armv8: ls1046a: make environment address and size common
2018-10-03 10:44 [U-Boot] [PATCH 00/53] TF-A Boot support for NXP Chassis 2 platforms Rajesh Bhagat
` (7 preceding siblings ...)
2018-10-03 10:44 ` [U-Boot] [PATCH 08/53] armv8: ls1046aqds: " Rajesh Bhagat
@ 2018-10-03 10:44 ` Rajesh Bhagat
2018-10-03 10:44 ` [U-Boot] [PATCH 10/53] armv8: ls1043ardb: Add TFABOOT defconfig Rajesh Bhagat
` (20 subsequent siblings)
29 siblings, 0 replies; 32+ messages in thread
From: Rajesh Bhagat @ 2018-10-03 10:44 UTC (permalink / raw)
To: u-boot
CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE and CONFIG_ENV_SECT_SIZE made common
to support all boot sources.
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
---
include/configs/ls1046aqds.h | 9 +++++++++
include/configs/ls1046ardb.h | 8 ++++++++
2 files changed, 17 insertions(+)
diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h
index 07e21469c8..765a21e00f 100644
--- a/include/configs/ls1046aqds.h
+++ b/include/configs/ls1046aqds.h
@@ -403,6 +403,14 @@ unsigned long get_board_ddr_clk(void);
*/
#define CONFIG_ENV_OVERWRITE
+#ifdef CONFIG_TFABOOT
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_OFFSET 0x500000 /* 5MB */
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x500000)
+#define CONFIG_ENV_SECT_SIZE 0x20000
+#else
#ifdef CONFIG_NAND_BOOT
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_OFFSET (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
@@ -419,6 +427,7 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_SIZE 0x20000
#endif
+#endif
#define CONFIG_CMDLINE_TAG
diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h
index ffca410b1a..b8d9419b48 100644
--- a/include/configs/ls1046ardb.h
+++ b/include/configs/ls1046ardb.h
@@ -160,6 +160,13 @@
#define CONFIG_ENV_OVERWRITE
#endif
+#ifdef CONFIG_TFABOOT
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
+#define CONFIG_ENV_OFFSET 0x500000 /* 5MB */
+#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */
+#else
#if defined(CONFIG_SD_BOOT)
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_OFFSET (3 * 1024 * 1024)
@@ -169,6 +176,7 @@
#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */
#endif
+#endif
#define AQR105_IRQ_MASK 0x80000000
/* FMan */
--
2.17.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [U-Boot] [PATCH 10/53] armv8: ls1043ardb: Add TFABOOT defconfig
2018-10-03 10:44 [U-Boot] [PATCH 00/53] TF-A Boot support for NXP Chassis 2 platforms Rajesh Bhagat
` (8 preceding siblings ...)
2018-10-03 10:44 ` [U-Boot] [PATCH 09/53] armv8: ls1046a: make environment address and size common Rajesh Bhagat
@ 2018-10-03 10:44 ` Rajesh Bhagat
2018-10-03 10:44 ` [U-Boot] [PATCH 11/53] armv8: ls1043aqds: " Rajesh Bhagat
` (19 subsequent siblings)
29 siblings, 0 replies; 32+ messages in thread
From: Rajesh Bhagat @ 2018-10-03 10:44 UTC (permalink / raw)
To: u-boot
This defconfig is for TFABOOT, to be loaded by trusted firmware.
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
---
board/freescale/ls1043ardb/ddr.c | 6 ++-
board/freescale/ls1043ardb/ls1043ardb.c | 12 ++++++
configs/ls1043ardb_ram_defconfig | 49 +++++++++++++++++++++++++
include/configs/ls1043a_common.h | 7 +++-
4 files changed, 71 insertions(+), 3 deletions(-)
create mode 100644 configs/ls1043ardb_ram_defconfig
diff --git a/board/freescale/ls1043ardb/ddr.c b/board/freescale/ls1043ardb/ddr.c
index 7bc0f568ff..1fb1635dfb 100644
--- a/board/freescale/ls1043ardb/ddr.c
+++ b/board/freescale/ls1043ardb/ddr.c
@@ -210,14 +210,16 @@ int fsl_initdram(void)
phys_size_t dram_size;
#ifdef CONFIG_SYS_DDR_RAW_TIMING
-#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL)
+#if !defined(CONFIG_TFABOOT) && \
+ (defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL))
puts("Initializing DDR....\n");
dram_size = fsl_ddr_sdram();
#else
dram_size = fsl_ddr_sdram_size();
#endif
#else
-#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL)
+#if !defined(CONFIG_TFABOOT) && \
+ (defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL))
puts("Initialzing DDR using fixed setting\n");
dram_size = fixed_sdram();
#else
diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c
index e7d8650d27..aa266557ba 100644
--- a/board/freescale/ls1043ardb/ls1043ardb.c
+++ b/board/freescale/ls1043ardb/ls1043ardb.c
@@ -37,6 +37,9 @@ int board_early_init_f(void)
int checkboard(void)
{
+#ifdef CONFIG_TFABOOT
+ enum boot_src src = get_boot_src();
+#endif
static const char *freq[2] = {"100.00MHZ", "156.25MHZ"};
#ifndef CONFIG_SD_BOOT
u8 cfg_rcw_src1, cfg_rcw_src2;
@@ -46,6 +49,12 @@ int checkboard(void)
printf("Board: LS1043ARDB, boot from ");
+#ifdef CONFIG_TFABOOT
+ if (src == BOOT_SOURCE_SD_MMC)
+ puts("SD\n");
+ else {
+#endif
+
#ifdef CONFIG_SD_BOOT
puts("SD\n");
#else
@@ -63,6 +72,9 @@ int checkboard(void)
printf("Invalid setting of SW4\n");
#endif
+#ifdef CONFIG_TFABOOT
+ }
+#endif
printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver),
CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver));
diff --git a/configs/ls1043ardb_ram_defconfig b/configs/ls1043ardb_ram_defconfig
new file mode 100644
index 0000000000..a15cb524d3
--- /dev/null
+++ b/configs/ls1043ardb_ram_defconfig
@@ -0,0 +1,49 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1043ARDB=y
+CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_TFABOOT=y
+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m at 0x100000(nor_bank0_uboot),40m at 0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m at 0x4100000(nor_bank4_uboot),40m at 0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
+CONFIG_MISC_INIT_R=y
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_CACHE=y
+CONFIG_MP=y
+CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m at 0x100000(nor_bank0_uboot),40m at 0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m at 0x4100000(nor_bank4_uboot),40m at 0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
+CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_DM=y
+CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_PHY_GIGE=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_STORAGE=y
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index 656d10dffb..80676487ae 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -33,7 +33,11 @@
#include <asm/arch/config.h>
/* Link Definitions */
+#ifdef CONFIG_TFABOOT
+#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
+#else
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
+#endif
#define CONFIG_SKIP_LOWLEVEL_INIT
@@ -119,7 +123,8 @@
/* IFC */
#ifndef SPL_NO_IFC
-#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
+#if defined(CONFIG_TFABOOT) || \
+ (!defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI))
#define CONFIG_FSL_IFC
/*
* CONFIG_SYS_FLASH_BASE has the final address (core view)
--
2.17.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [U-Boot] [PATCH 11/53] armv8: ls1043aqds: Add TFABOOT defconfig
2018-10-03 10:44 [U-Boot] [PATCH 00/53] TF-A Boot support for NXP Chassis 2 platforms Rajesh Bhagat
` (9 preceding siblings ...)
2018-10-03 10:44 ` [U-Boot] [PATCH 10/53] armv8: ls1043ardb: Add TFABOOT defconfig Rajesh Bhagat
@ 2018-10-03 10:44 ` Rajesh Bhagat
2018-10-03 10:44 ` [U-Boot] [PATCH 12/53] armv8: ls1043a: make environment address and size common Rajesh Bhagat
` (18 subsequent siblings)
29 siblings, 0 replies; 32+ messages in thread
From: Rajesh Bhagat @ 2018-10-03 10:44 UTC (permalink / raw)
To: u-boot
This defconfig is for TFABOOT, to be loaded by trusted firmware.
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
---
board/freescale/ls1043aqds/ddr.c | 3 +-
board/freescale/ls1043aqds/ls1043aqds.c | 15 ++++++-
configs/ls1043aqds_ram_defconfig | 54 +++++++++++++++++++++++++
include/configs/ls1043aqds.h | 3 +-
4 files changed, 72 insertions(+), 3 deletions(-)
create mode 100644 configs/ls1043aqds_ram_defconfig
diff --git a/board/freescale/ls1043aqds/ddr.c b/board/freescale/ls1043aqds/ddr.c
index efc441a917..a79d8e2120 100644
--- a/board/freescale/ls1043aqds/ddr.c
+++ b/board/freescale/ls1043aqds/ddr.c
@@ -112,7 +112,8 @@ int fsl_initdram(void)
{
phys_size_t dram_size;
-#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_TFABOOT) || \
+ (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
gd->ram_size = fsl_ddr_sdram_size();
return 0;
diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c
index 4fba57242b..5247d9ac14 100644
--- a/board/freescale/ls1043aqds/ls1043aqds.c
+++ b/board/freescale/ls1043aqds/ls1043aqds.c
@@ -47,6 +47,9 @@ enum {
int checkboard(void)
{
+#ifdef CONFIG_TFABOOT
+ enum boot_src src = get_boot_src();
+#endif
char buf[64];
#ifndef CONFIG_SD_BOOT
u8 sw;
@@ -54,6 +57,12 @@ int checkboard(void)
puts("Board: LS1043AQDS, boot from ");
+#ifdef CONFIG_TFABOOT
+ if (src == BOOT_SOURCE_SD_MMC)
+ puts("SD\n");
+ else {
+#endif
+
#ifdef CONFIG_SD_BOOT
puts("SD\n");
#else
@@ -72,6 +81,9 @@ int checkboard(void)
printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
#endif
+#ifdef CONFIG_TFABOOT
+ }
+#endif
printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
QIXIS_READ(id), QIXIS_READ(arch));
@@ -155,7 +167,8 @@ int dram_init(void)
*/
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
fsl_initdram();
-#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+#if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
+ defined(CONFIG_SPL_BUILD)
/* This will break-before-make MMU for DDR */
update_early_mmu_table();
#endif
diff --git a/configs/ls1043aqds_ram_defconfig b/configs/ls1043aqds_ram_defconfig
new file mode 100644
index 0000000000..149a26ef33
--- /dev/null
+++ b/configs/ls1043aqds_ram_defconfig
@@ -0,0 +1,54 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1043AQDS=y
+CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_TFABOOT=y
+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m at 0x100000(nor_bank0_uboot),40m at 0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m at 0x4100000(nor_bank4_uboot),40m at 0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
+# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_MISC_INIT_R=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_CACHE=y
+CONFIG_MP=y
+CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m at 0x100000(nor_bank0_uboot),40m at 0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m at 0x4100000(nor_bank4_uboot),40m at 0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
+CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_DM=y
+CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_STORAGE=y
diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h
index 68f202f97a..31ef9941b6 100644
--- a/include/configs/ls1043aqds.h
+++ b/include/configs/ls1043aqds.h
@@ -349,7 +349,8 @@ unsigned long get_board_ddr_clk(void);
#define VDD_MV_MAX 1212
/* QSPI device */
-#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#if defined(CONFIG_TFABOOT) || \
+ (defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI))
#define CONFIG_FSL_QSPI
#ifdef CONFIG_FSL_QSPI
#define CONFIG_SPI_FLASH_SPANSION
--
2.17.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [U-Boot] [PATCH 12/53] armv8: ls1043a: make environment address and size common
2018-10-03 10:44 [U-Boot] [PATCH 00/53] TF-A Boot support for NXP Chassis 2 platforms Rajesh Bhagat
` (10 preceding siblings ...)
2018-10-03 10:44 ` [U-Boot] [PATCH 11/53] armv8: ls1043aqds: " Rajesh Bhagat
@ 2018-10-03 10:44 ` Rajesh Bhagat
2018-10-03 10:44 ` [U-Boot] [PATCH 13/53] armv8: ls1043aqds: define environment address for QSPI boot Rajesh Bhagat
` (17 subsequent siblings)
29 siblings, 0 replies; 32+ messages in thread
From: Rajesh Bhagat @ 2018-10-03 10:44 UTC (permalink / raw)
To: u-boot
CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE and CONFIG_ENV_SECT_SIZE made common
to support all boot sources.
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
---
include/configs/ls1043aqds.h | 9 +++++++++
include/configs/ls1043ardb.h | 9 +++++++++
2 files changed, 18 insertions(+)
diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h
index 31ef9941b6..88736d0e89 100644
--- a/include/configs/ls1043aqds.h
+++ b/include/configs/ls1043aqds.h
@@ -382,6 +382,14 @@ unsigned long get_board_ddr_clk(void);
*/
#define CONFIG_ENV_OVERWRITE
+#ifdef CONFIG_TFABOOT
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_OFFSET 0x500000 /* 5MB */
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x500000)
+#define CONFIG_ENV_SECT_SIZE 0x20000
+#else
#ifdef CONFIG_NAND_BOOT
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_OFFSET (24 * CONFIG_SYS_NAND_BLOCK_SIZE)
@@ -398,6 +406,7 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_SIZE 0x20000
#endif
+#endif
#define CONFIG_CMDLINE_TAG
diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
index bc639e586f..bd56cbd8aa 100644
--- a/include/configs/ls1043ardb.h
+++ b/include/configs/ls1043ardb.h
@@ -227,6 +227,14 @@
#define CONFIG_ENV_OVERWRITE
#endif
+#ifdef CONFIG_TFABOOT
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_OFFSET 0x500000
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x500000)
+#define CONFIG_ENV_SECT_SIZE 0x20000
+#else
#if defined(CONFIG_NAND_BOOT)
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_OFFSET (24 * CONFIG_SYS_NAND_BLOCK_SIZE)
@@ -239,6 +247,7 @@
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_SIZE 0x20000
#endif
+#endif
/* FMan */
#ifndef SPL_NO_FMAN
--
2.17.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [U-Boot] [PATCH 13/53] armv8: ls1043aqds: define environment address for QSPI boot
2018-10-03 10:44 [U-Boot] [PATCH 00/53] TF-A Boot support for NXP Chassis 2 platforms Rajesh Bhagat
` (11 preceding siblings ...)
2018-10-03 10:44 ` [U-Boot] [PATCH 12/53] armv8: ls1043a: make environment address and size common Rajesh Bhagat
@ 2018-10-03 10:44 ` Rajesh Bhagat
2018-10-03 10:44 ` [U-Boot] [PATCH 14/53] armv8: ls1046aqds: " Rajesh Bhagat
` (16 subsequent siblings)
29 siblings, 0 replies; 32+ messages in thread
From: Rajesh Bhagat @ 2018-10-03 10:44 UTC (permalink / raw)
To: u-boot
Defines environment address for QSPI boot
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
---
board/freescale/ls1043aqds/ls1043aqds.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c
index 5247d9ac14..1f317a4574 100644
--- a/board/freescale/ls1043aqds/ls1043aqds.c
+++ b/board/freescale/ls1043aqds/ls1043aqds.c
@@ -13,6 +13,9 @@
#include <asm/arch/ppa.h>
#include <asm/arch/fdt.h>
#include <asm/arch/mmu.h>
+#ifdef CONFIG_TFABOOT
+#include <asm/arch/cpu.h>
+#endif
#include <asm/arch/soc.h>
#include <ahci.h>
#include <hwconfig.h>
@@ -396,3 +399,10 @@ u16 flash_read16(void *addr)
return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
}
+
+#ifdef CONFIG_TFABOOT
+void *env_sf_get_env_addr(void)
+{
+ return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
+}
+#endif
--
2.17.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [U-Boot] [PATCH 14/53] armv8: ls1046aqds: define environment address for QSPI boot.
2018-10-03 10:44 [U-Boot] [PATCH 00/53] TF-A Boot support for NXP Chassis 2 platforms Rajesh Bhagat
` (12 preceding siblings ...)
2018-10-03 10:44 ` [U-Boot] [PATCH 13/53] armv8: ls1043aqds: define environment address for QSPI boot Rajesh Bhagat
@ 2018-10-03 10:44 ` Rajesh Bhagat
2018-10-03 10:44 ` [U-Boot] [PATCH 15/53] net: fm: add TFABOOT support Rajesh Bhagat
` (15 subsequent siblings)
29 siblings, 0 replies; 32+ messages in thread
From: Rajesh Bhagat @ 2018-10-03 10:44 UTC (permalink / raw)
To: u-boot
From: Pankit Garg <pankit.garg@nxp.com>
Define environment address for QSPI Boot.
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
---
board/freescale/ls1046aqds/ls1046aqds.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c
index 77b21ac52a..ae401a38eb 100644
--- a/board/freescale/ls1046aqds/ls1046aqds.c
+++ b/board/freescale/ls1046aqds/ls1046aqds.c
@@ -13,6 +13,9 @@
#include <asm/arch/ppa.h>
#include <asm/arch/fdt.h>
#include <asm/arch/mmu.h>
+#ifdef CONFIG_TFABOOT
+#include <asm/arch/cpu.h>
+#endif
#include <asm/arch/soc.h>
#include <asm/arch-fsl-layerscape/fsl_icid.h>
#include <ahci.h>
@@ -355,3 +358,10 @@ u16 flash_read16(void *addr)
return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
}
+
+#ifdef CONFIG_TFABOOT
+void *env_sf_get_env_addr(void)
+{
+ return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
+}
+#endif
--
2.17.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [U-Boot] [PATCH 15/53] net: fm: add TFABOOT support
2018-10-03 10:44 [U-Boot] [PATCH 00/53] TF-A Boot support for NXP Chassis 2 platforms Rajesh Bhagat
` (13 preceding siblings ...)
2018-10-03 10:44 ` [U-Boot] [PATCH 14/53] armv8: ls1046aqds: " Rajesh Bhagat
@ 2018-10-03 10:44 ` Rajesh Bhagat
2018-10-03 10:44 ` [U-Boot] [PATCH 16/53] drivers: qe: " Rajesh Bhagat
` (14 subsequent siblings)
29 siblings, 0 replies; 32+ messages in thread
From: Rajesh Bhagat @ 2018-10-03 10:44 UTC (permalink / raw)
To: u-boot
Adds TFABOOT support and allows to pick FMAN firmware
on basis of boot source.
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
---
drivers/net/fm/fm.c | 104 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 104 insertions(+)
diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c
index 3327073bf1..427ea1a627 100644
--- a/drivers/net/fm/fm.c
+++ b/drivers/net/fm/fm.c
@@ -11,6 +11,15 @@
#include "fm.h"
#include <fsl_qe.h> /* For struct qe_firmware */
+#ifdef CONFIG_TFABOOT
+#include <nand.h>
+#include <spi_flash.h>
+#include <mmc.h>
+/* required to include IFC and QSPI base address */
+#include <asm/armv8/mmu.h>
+#include <asm/arch/cpu.h>
+#include <environment.h>
+#else
#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
#include <nand.h>
#elif defined(CONFIG_SYS_QE_FW_IN_SPIFLASH)
@@ -18,6 +27,7 @@
#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_MMC)
#include <mmc.h>
#endif
+#endif
struct fm_muram muram[CONFIG_SYS_NUM_FMAN];
@@ -347,6 +357,99 @@ static void fm_init_qmi(struct fm_qmi_common *qmi)
}
/* Init common part of FM, index is fm num# like fm as above */
+#ifdef CONFIG_TFABOOT
+int fm_init_common(int index, struct ccsr_fman *reg)
+{
+ int rc;
+ void *addr = NULL;
+ enum boot_src src = get_boot_src();
+
+ if (src == BOOT_SOURCE_IFC_NOR) {
+ addr = (void *)(CONFIG_SYS_FMAN_FW_ADDR +
+ CONFIG_SYS_FSL_IFC_BASE);
+ } else if (src == BOOT_SOURCE_IFC_NAND) {
+ size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
+
+ addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
+
+ rc = nand_read(get_nand_dev_by_index(0),
+ (loff_t)CONFIG_SYS_FMAN_FW_ADDR,
+ &fw_length, (u_char *)addr);
+ if (rc == -EUCLEAN) {
+ printf("NAND read of FMAN firmware at offset 0x%x\
+ failed %d\n", CONFIG_SYS_FMAN_FW_ADDR, rc);
+ }
+ } else if (src == BOOT_SOURCE_QSPI_NOR) {
+ struct spi_flash *ucode_flash;
+
+ addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
+ int ret = 0;
+
+#ifdef CONFIG_DM_SPI_FLASH
+ struct udevice *new;
+
+ /* speed and mode will be read from DT */
+ ret = spi_flash_probe_bus_cs(CONFIG_ENV_SPI_BUS,
+ CONFIG_ENV_SPI_CS, 0, 0, &new);
+
+ ucode_flash = dev_get_uclass_priv(new);
+#else
+ ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS,
+ CONFIG_ENV_SPI_CS,
+ CONFIG_ENV_SPI_MAX_HZ,
+ CONFIG_ENV_SPI_MODE);
+#endif
+ if (!ucode_flash)
+ printf("SF: probe for ucode failed\n");
+ else {
+ ret = spi_flash_read(ucode_flash,
+ CONFIG_SYS_FMAN_FW_ADDR +
+ CONFIG_SYS_FSL_QSPI_BASE,
+ CONFIG_SYS_QE_FMAN_FW_LENGTH,
+ addr);
+ if (ret)
+ printf("SF: read for ucode failed\n");
+ spi_flash_free(ucode_flash);
+ }
+ } else if (src == BOOT_SOURCE_SD_MMC) {
+ int dev = CONFIG_SYS_MMC_ENV_DEV;
+
+ addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
+ u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512;
+ u32 blk = CONFIG_SYS_FMAN_FW_ADDR / 512;
+ struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
+
+ if (!mmc)
+ printf("\nMMC cannot find device for ucode\n");
+ else {
+ printf("\nMMC read: dev # %u, block # %u, count %u \
+ ...\n", dev, blk, cnt);
+ mmc_init(mmc);
+ (void)mmc->block_dev.block_read(&mmc->block_dev, blk,
+ cnt, addr);
+ }
+ } else
+ addr = NULL;
+
+ /* Upload the Fman microcode if it's present */
+ rc = fman_upload_firmware(index, ®->fm_imem, addr);
+ if (rc)
+ return rc;
+ env_set_addr("fman_ucode", addr);
+
+ fm_init_muram(index, ®->muram);
+ fm_init_qmi(®->fm_qmi_common);
+ fm_init_fpm(®->fm_fpm);
+
+ /* clear DMA status */
+ setbits_be32(®->fm_dma.fmdmsr, FMDMSR_CLEAR_ALL);
+
+ /* set DMA mode */
+ setbits_be32(®->fm_dma.fmdmmr, FMDMMR_SBER);
+
+ return fm_init_bmi(index, ®->fm_bmi_common);
+}
+#else
int fm_init_common(int index, struct ccsr_fman *reg)
{
int rc;
@@ -429,3 +532,4 @@ int fm_init_common(int index, struct ccsr_fman *reg)
return fm_init_bmi(index, ®->fm_bmi_common);
}
+#endif
--
2.17.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [U-Boot] [PATCH 16/53] drivers: qe: add TFABOOT support
2018-10-03 10:44 [U-Boot] [PATCH 00/53] TF-A Boot support for NXP Chassis 2 platforms Rajesh Bhagat
` (14 preceding siblings ...)
2018-10-03 10:44 ` [U-Boot] [PATCH 15/53] net: fm: add TFABOOT support Rajesh Bhagat
@ 2018-10-03 10:44 ` Rajesh Bhagat
2018-10-03 10:44 ` [U-Boot] [PATCH 17/53] armv8: ls1046a: make FMAN address common Rajesh Bhagat
` (13 subsequent siblings)
29 siblings, 0 replies; 32+ messages in thread
From: Rajesh Bhagat @ 2018-10-03 10:44 UTC (permalink / raw)
To: u-boot
Adds TFABOOT support and allows to pick QE firmware
on basis of boot source.
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
---
drivers/qe/qe.c | 81 +++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 81 insertions(+)
diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index 7654df8008..d7e3a1b923 100644
--- a/drivers/qe/qe.c
+++ b/drivers/qe/qe.c
@@ -17,9 +17,17 @@
#include <asm/arch/immap_ls102xa.h>
#endif
+#ifdef CONFIG_TFABOOT
+#include <mmc.h>
+/* required to include IFC and QSPI base address */
+#include <asm/armv8/mmu.h>
+#include <asm/arch/cpu.h>
+#include <environment.h>
+#else
#ifdef CONFIG_SYS_QE_FMAN_FW_IN_MMC
#include <mmc.h>
#endif
+#endif
#define MPC85xx_DEVDISR_QE_DISABLE 0x1
@@ -170,6 +178,33 @@ void qe_put_snum(u8 snum)
}
}
+#ifdef CONFIG_TFABOOT
+void qe_init(uint qe_base)
+{
+ enum boot_src src = get_boot_src();
+
+ /* Init the QE IMMR base */
+ qe_immr = (qe_map_t *)qe_base;
+
+ if (src == BOOT_SOURCE_IFC_NOR) {
+ /*
+ * Upload microcode to IRAM for those SOCs
+ * which do not have ROM in QE.
+ */
+ qe_upload_firmware((const void *)(CONFIG_SYS_QE_FW_ADDR +
+ CONFIG_SYS_FSL_IFC_BASE));
+
+ /* enable the microcode in IRAM */
+ out_be32(&qe_immr->iram.iready, QE_IRAM_READY);
+ }
+
+ gd->arch.mp_alloc_base = QE_DATAONLY_BASE;
+ gd->arch.mp_alloc_top = gd->arch.mp_alloc_base + QE_DATAONLY_SIZE;
+
+ qe_sdma_init();
+ qe_snums_init();
+}
+#else
void qe_init(uint qe_base)
{
/* Init the QE IMMR base */
@@ -192,8 +227,53 @@ void qe_init(uint qe_base)
qe_snums_init();
}
#endif
+#endif
#ifdef CONFIG_U_QE
+#ifdef CONFIG_TFABOOT
+void u_qe_init(void)
+{
+ enum boot_src src = get_boot_src();
+
+ qe_immr = (qe_map_t *)(CONFIG_SYS_IMMR + QE_IMMR_OFFSET);
+
+ void *addr = (void *)CONFIG_SYS_QE_FW_ADDR;
+
+ if (src == BOOT_SOURCE_IFC_NOR) {
+ addr = (void *)(CONFIG_SYS_QE_FW_ADDR + CONFIG_SYS_FSL_IFC_BASE);
+ }
+ if (src == BOOT_SOURCE_QSPI_NOR) {
+ addr = (void *)(CONFIG_SYS_QE_FW_ADDR + CONFIG_SYS_FSL_QSPI_BASE);
+ }
+ if (src == BOOT_SOURCE_SD_MMC) {
+ int dev = CONFIG_SYS_MMC_ENV_DEV;
+ u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512;
+ u32 blk = CONFIG_SYS_QE_FW_ADDR / 512;
+
+ if (mmc_initialize(gd->bd)) {
+ printf("%s: mmc_initialize() failed\n", __func__);
+ return;
+ }
+ addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
+ struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
+
+ if (!mmc) {
+ free(addr);
+ printf("\nMMC cannot find device for ucode\n");
+ } else {
+ printf("\nMMC read: dev # %u, block # %u,\
+ count %u ...\n", dev, blk, cnt);
+ mmc_init(mmc);
+ (void)mmc->block_dev.block_read(&mmc->block_dev, blk,
+ cnt, addr);
+ }
+ }
+ if (!u_qe_upload_firmware(addr))
+ out_be32(&qe_immr->iram.iready, QE_IRAM_READY);
+ if (src == BOOT_SOURCE_SD_MMC)
+ free(addr);
+}
+#else
void u_qe_init(void)
{
qe_immr = (qe_map_t *)(CONFIG_SYS_IMMR + QE_IMMR_OFFSET);
@@ -229,6 +309,7 @@ void u_qe_init(void)
#endif
}
#endif
+#endif
#ifdef CONFIG_U_QE
void u_qe_resume(void)
--
2.17.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [U-Boot] [PATCH 17/53] armv8: ls1046a: make FMAN address common
2018-10-03 10:44 [U-Boot] [PATCH 00/53] TF-A Boot support for NXP Chassis 2 platforms Rajesh Bhagat
` (15 preceding siblings ...)
2018-10-03 10:44 ` [U-Boot] [PATCH 16/53] drivers: qe: " Rajesh Bhagat
@ 2018-10-03 10:44 ` Rajesh Bhagat
2018-10-03 10:44 ` [U-Boot] [PATCH 18/53] armv8: ls1043a: make FMAN and QE " Rajesh Bhagat
` (12 subsequent siblings)
29 siblings, 0 replies; 32+ messages in thread
From: Rajesh Bhagat @ 2018-10-03 10:44 UTC (permalink / raw)
To: u-boot
CONFIG_SYS_FMAN_FW_ADDR made common to support all boot sources.
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
---
include/configs/ls1046a_common.h | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h
index b6ec5bdf66..6e36c9339b 100644
--- a/include/configs/ls1046a_common.h
+++ b/include/configs/ls1046a_common.h
@@ -169,6 +169,13 @@
#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
#endif
+#ifdef CONFIG_TFABOOT
+#define CONFIG_SYS_FMAN_FW_ADDR 0x900000
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_CS 0
+#define CONFIG_ENV_SPI_MAX_HZ 1000000
+#define CONFIG_ENV_SPI_MODE 0x03
+#else
#ifdef CONFIG_SD_BOOT
/*
* PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
@@ -191,6 +198,7 @@
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
#define CONFIG_SYS_FMAN_FW_ADDR 0x60900000
#endif
+#endif
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#endif
--
2.17.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [U-Boot] [PATCH 18/53] armv8: ls1043a: make FMAN and QE address common
2018-10-03 10:44 [U-Boot] [PATCH 00/53] TF-A Boot support for NXP Chassis 2 platforms Rajesh Bhagat
` (16 preceding siblings ...)
2018-10-03 10:44 ` [U-Boot] [PATCH 17/53] armv8: ls1046a: make FMAN address common Rajesh Bhagat
@ 2018-10-03 10:44 ` Rajesh Bhagat
2018-10-03 10:44 ` [U-Boot] [PATCH 19/53] armv8: fsl-layerscape: bootcmd identification for TFABOOT Rajesh Bhagat
` (11 subsequent siblings)
29 siblings, 0 replies; 32+ messages in thread
From: Rajesh Bhagat @ 2018-10-03 10:44 UTC (permalink / raw)
To: u-boot
CONFIG_SYS_FMAN_FW_ADDR and CONFIG_SYS_QE_FW_ADDR made common
to support all boot sources.
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
---
include/configs/ls1043a_common.h | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index 80676487ae..e8b6657b83 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -190,6 +190,16 @@
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
+#ifdef CONFIG_TFABOOT
+#define CONFIG_SYS_FMAN_FW_ADDR 0x900000
+#define CONFIG_SYS_QE_FW_ADDR 0x940000
+
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_CS 0
+#define CONFIG_ENV_SPI_MAX_HZ 1000000
+#define CONFIG_ENV_SPI_MODE 0x03
+
+#else
#ifdef CONFIG_NAND_BOOT
/* Store Fman ucode at offeset 0x900000(72 blocks). */
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
@@ -216,6 +226,7 @@
#define CONFIG_SYS_FMAN_FW_ADDR 0x60900000
#define CONFIG_SYS_QE_FW_ADDR 0x60940000
#endif
+#endif
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#endif
--
2.17.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [U-Boot] [PATCH 19/53] armv8: fsl-layerscape: bootcmd identification for TFABOOT.
2018-10-03 10:44 [U-Boot] [PATCH 00/53] TF-A Boot support for NXP Chassis 2 platforms Rajesh Bhagat
` (17 preceding siblings ...)
2018-10-03 10:44 ` [U-Boot] [PATCH 18/53] armv8: ls1043a: make FMAN and QE " Rajesh Bhagat
@ 2018-10-03 10:44 ` Rajesh Bhagat
2018-10-03 10:44 ` [U-Boot] [PATCH 20/53] armv8: ls1046a: define BOOTCOMMAND " Rajesh Bhagat
` (10 subsequent siblings)
29 siblings, 0 replies; 32+ messages in thread
From: Rajesh Bhagat @ 2018-10-03 10:44 UTC (permalink / raw)
To: u-boot
From: Pankit Garg <pankit.garg@nxp.com>
Adds bootcmd identificaton on basis on boot source, valid
in TFABOOT configuration.
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
---
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 69 +++++++++++++++++++++++++
1 file changed, 69 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 3f15cb08ff..1e701c58df 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -679,12 +679,81 @@ int qspi_ahb_init(void)
}
#endif
+#ifdef CONFIG_TFABOOT
+#define MAX_BOOTCMD_SIZE 256
+
+int fsl_setenv_bootcmd(void)
+{
+ int ret;
+ enum boot_src src = get_boot_src();
+ char bootcmd_str[MAX_BOOTCMD_SIZE];
+
+ switch (src) {
+#ifdef IFC_NOR_BOOTCOMMAND
+ case BOOT_SOURCE_IFC_NOR:
+ sprintf(bootcmd_str, IFC_NOR_BOOTCOMMAND);
+ break;
+#endif
+#ifdef QSPI_NOR_BOOTCOMMAND
+ case BOOT_SOURCE_QSPI_NOR:
+ sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND);
+ break;
+#endif
+#ifdef XSPI_NOR_BOOTCOMMAND
+ case BOOT_SOURCE_XSPI_NOR:
+ sprintf(bootcmd_str, XSPI_NOR_BOOTCOMMAND);
+ break;
+#endif
+#ifdef IFC_NAND_BOOTCOMMAND
+ case BOOT_SOURCE_IFC_NAND:
+ sprintf(bootcmd_str, IFC_NAND_BOOTCOMMAND);
+ break;
+#endif
+#ifdef QSPI_NAND_BOOTCOMMAND
+ case BOOT_SOURCE_QSPI_NAND:
+ sprintf(bootcmd_str, QSPI_NAND_BOOTCOMMAND);
+ break;
+#endif
+#ifdef XSPI_NAND_BOOTCOMMAND
+ case BOOT_SOURCE_XSPI_NAND:
+ sprintf(bootcmd_str, XSPI_NAND_BOOTCOMMAND);
+ break;
+#endif
+#ifdef SD_BOOTCOMMAND
+ case BOOT_SOURCE_SD_MMC:
+ sprintf(bootcmd_str, SD_BOOTCOMMAND);
+ break;
+#endif
+#ifdef SD2_BOOTCOMMAND
+ case BOOT_SOURCE_SD_MMC2:
+ sprintf(bootcmd_str, SD2_BOOTCOMMAND);
+ break;
+#endif
+ default:
+#ifdef QSPI_NOR_BOOTCOMMAND
+ sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND);
+#endif
+ break;
+ }
+
+ ret = env_set("bootcmd", bootcmd_str);
+ if (ret) {
+ printf("Failed to set bootcmd: ret = %d\n", ret);
+ return ret;
+ }
+ return 0;
+}
+#endif
+
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
#ifdef CONFIG_CHAIN_OF_TRUST
fsl_setenv_chain_of_trust();
#endif
+#ifdef CONFIG_TFABOOT
+ fsl_setenv_bootcmd();
+#endif
#ifdef CONFIG_QSPI_AHB_INIT
qspi_ahb_init();
#endif
--
2.17.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [U-Boot] [PATCH 20/53] armv8: ls1046a: define BOOTCOMMAND for TFABOOT
2018-10-03 10:44 [U-Boot] [PATCH 00/53] TF-A Boot support for NXP Chassis 2 platforms Rajesh Bhagat
` (18 preceding siblings ...)
2018-10-03 10:44 ` [U-Boot] [PATCH 19/53] armv8: fsl-layerscape: bootcmd identification for TFABOOT Rajesh Bhagat
@ 2018-10-03 10:44 ` Rajesh Bhagat
2018-10-03 10:44 ` [U-Boot] [PATCH 21/53] armv8: ls1043a: " Rajesh Bhagat
` (9 subsequent siblings)
29 siblings, 0 replies; 32+ messages in thread
From: Rajesh Bhagat @ 2018-10-03 10:44 UTC (permalink / raw)
To: u-boot
Defines BOOTCOMMAND for TFABOOT configuration for
supported boot sources.
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
---
include/configs/ls1046aqds.h | 9 +++++++++
include/configs/ls1046ardb.h | 7 +++++++
2 files changed, 16 insertions(+)
diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h
index 765a21e00f..2a30cef0e4 100644
--- a/include/configs/ls1046aqds.h
+++ b/include/configs/ls1046aqds.h
@@ -432,6 +432,14 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_CMDLINE_TAG
#undef CONFIG_BOOTCOMMAND
+#ifdef CONFIG_TFABOOT
+#define QSPI_NOR_BOOTCOMMAND "sf probe && sf read $kernel_load " \
+ "e0000 f00000 && bootm $kernel_load"
+#define IFC_NOR_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \
+ "$kernel_size && bootm $kernel_load"
+#define SD_BOOTCOMMAND "mmc info; mmc read $kernel_load" \
+ "$kernel_addr_sd $kernel_size_sd && bootm $kernel_load"
+#else
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_BOOTCOMMAND "sf probe && sf read $kernel_load " \
"e0000 f00000 && bootm $kernel_load"
@@ -439,6 +447,7 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \
"$kernel_size && bootm $kernel_load"
#endif
+#endif
#include <asm/fsl_secure_boot.h>
diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h
index b8d9419b48..cc1f5f5f55 100644
--- a/include/configs/ls1046ardb.h
+++ b/include/configs/ls1046ardb.h
@@ -216,6 +216,12 @@
#ifndef SPL_NO_MISC
#undef CONFIG_BOOTCOMMAND
+#ifdef CONFIG_TFABOOT
+#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
+ "env exists secureboot && esbc_halt;;"
+#define SD_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; " \
+ "env exists secureboot && esbc_halt;"
+#else
#if defined(CONFIG_QSPI_BOOT)
#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
"env exists secureboot && esbc_halt;;"
@@ -224,6 +230,7 @@
"env exists secureboot && esbc_halt;"
#endif
#endif
+#endif
#include <asm/fsl_secure_boot.h>
--
2.17.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [U-Boot] [PATCH 21/53] armv8: ls1043a: define BOOTCOMMAND for TFABOOT
2018-10-03 10:44 [U-Boot] [PATCH 00/53] TF-A Boot support for NXP Chassis 2 platforms Rajesh Bhagat
` (19 preceding siblings ...)
2018-10-03 10:44 ` [U-Boot] [PATCH 20/53] armv8: ls1046a: define BOOTCOMMAND " Rajesh Bhagat
@ 2018-10-03 10:44 ` Rajesh Bhagat
2018-10-03 10:44 ` [U-Boot] [PATCH 22/53] armv8: ls1012ardb: Add TFABOOT defconfig Rajesh Bhagat
` (8 subsequent siblings)
29 siblings, 0 replies; 32+ messages in thread
From: Rajesh Bhagat @ 2018-10-03 10:44 UTC (permalink / raw)
To: u-boot
Defines BOOTCOMMAND for TFABOOT configuration for
supported boot sources.
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
---
include/configs/ls1043a_common.h | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index e8b6657b83..7875bf4bba 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -319,6 +319,14 @@
#undef CONFIG_BOOTCOMMAND
+#ifdef CONFIG_TFABOOT
+#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
+ "env exists secureboot && esbc_halt;"
+#define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
+ "env exists secureboot && esbc_halt;"
+#define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
+ "env exists secureboot && esbc_halt;"
+#else
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
"env exists secureboot && esbc_halt;"
@@ -330,6 +338,7 @@
"env exists secureboot && esbc_halt;"
#endif
#endif
+#endif
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
--
2.17.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [U-Boot] [PATCH 22/53] armv8: ls1012ardb: Add TFABOOT defconfig
2018-10-03 10:44 [U-Boot] [PATCH 00/53] TF-A Boot support for NXP Chassis 2 platforms Rajesh Bhagat
` (20 preceding siblings ...)
2018-10-03 10:44 ` [U-Boot] [PATCH 21/53] armv8: ls1043a: " Rajesh Bhagat
@ 2018-10-03 10:44 ` Rajesh Bhagat
2018-10-03 10:44 ` [U-Boot] [PATCH 23/53] armv8: ls1012aqds: " Rajesh Bhagat
` (7 subsequent siblings)
29 siblings, 0 replies; 32+ messages in thread
From: Rajesh Bhagat @ 2018-10-03 10:44 UTC (permalink / raw)
To: u-boot
This defconfig is for TFABOOT, to be loaded by trusted firmware.
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
---
board/freescale/ls1012ardb/ls1012ardb.c | 11 +++++
configs/ls1012ardb_ram_defconfig | 56 +++++++++++++++++++++++++
include/configs/ls1012a_common.h | 6 ++-
3 files changed, 72 insertions(+), 1 deletion(-)
create mode 100644 configs/ls1012ardb_ram_defconfig
diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
index 888f8500d4..f59749b87c 100644
--- a/board/freescale/ls1012ardb/ls1012ardb.c
+++ b/board/freescale/ls1012ardb/ls1012ardb.c
@@ -87,8 +87,17 @@ int checkboard(void)
return 0;
}
+#ifdef CONFIG_TFABOOT
int dram_init(void)
{
+ gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+ return 0;
+}
+#else
+int dram_init(void)
+{
+#ifndef CONFIG_TFABOOT
static const struct fsl_mmdc_info mparam = {
0x05180000, /* mdctl */
0x00030035, /* mdpdc */
@@ -106,6 +115,7 @@ int dram_init(void)
};
mmdc_init(&mparam);
+#endif
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
@@ -115,6 +125,7 @@ int dram_init(void)
return 0;
}
+#endif
int board_early_init_f(void)
diff --git a/configs/ls1012ardb_ram_defconfig b/configs/ls1012ardb_ram_defconfig
new file mode 100644
index 0000000000..e594bd6b21
--- /dev/null
+++ b/configs/ls1012ardb_ram_defconfig
@@ -0,0 +1,56 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1012ARDB=y
+CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_QSPI_AHB_INIT=y
+CONFIG_TFABOOT=y
+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_NR_DRAM_BANKS=2
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000"
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+# CONFIG_BLK is not set
+CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_FSL_PFE=y
+CONFIG_DM_ETH=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_STORAGE=y
diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
index 787adbc382..07998f7eee 100644
--- a/include/configs/ls1012a_common.h
+++ b/include/configs/ls1012a_common.h
@@ -16,7 +16,11 @@
#define CONFIG_SKIP_LOWLEVEL_INIT
+#ifdef CONFIG_TFABOOT
+#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
+#else
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
+#endif
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
@@ -34,7 +38,7 @@
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
/*SPI device */
-#ifdef CONFIG_QSPI_BOOT
+#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_TFABOOT)
#define CONFIG_SYS_QE_FW_IN_SPIFLASH
#define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000
#define CONFIG_ENV_SPI_BUS 0
--
2.17.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [U-Boot] [PATCH 23/53] armv8: ls1012aqds: Add TFABOOT defconfig
2018-10-03 10:44 [U-Boot] [PATCH 00/53] TF-A Boot support for NXP Chassis 2 platforms Rajesh Bhagat
` (21 preceding siblings ...)
2018-10-03 10:44 ` [U-Boot] [PATCH 22/53] armv8: ls1012ardb: Add TFABOOT defconfig Rajesh Bhagat
@ 2018-10-03 10:44 ` Rajesh Bhagat
2018-10-03 10:44 ` [U-Boot] [PATCH 24/53] armv8: ls1012a: update environment address for TFABOOT Rajesh Bhagat
` (6 subsequent siblings)
29 siblings, 0 replies; 32+ messages in thread
From: Rajesh Bhagat @ 2018-10-03 10:44 UTC (permalink / raw)
To: u-boot
This defconfig is for TFABOOT, to be loaded by trusted firmware.
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
---
board/freescale/ls1012aqds/ls1012aqds.c | 10 +++-
configs/ls1012aqds_ram_defconfig | 62 +++++++++++++++++++++++++
2 files changed, 71 insertions(+), 1 deletion(-)
create mode 100644 configs/ls1012aqds_ram_defconfig
diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
index 7102237756..f312200433 100644
--- a/board/freescale/ls1012aqds/ls1012aqds.c
+++ b/board/freescale/ls1012aqds/ls1012aqds.c
@@ -55,6 +55,14 @@ int checkboard(void)
return 0;
}
+#ifdef CONFIG_TFABOOT
+int dram_init(void)
+{
+ gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+ return 0;
+}
+#else
int dram_init(void)
{
static const struct fsl_mmdc_info mparam = {
@@ -74,7 +82,6 @@ int dram_init(void)
};
mmdc_init(&mparam);
-
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
/* This will break-before-make MMU for DDR */
@@ -83,6 +90,7 @@ int dram_init(void)
return 0;
}
+#endif
int board_early_init_f(void)
{
diff --git a/configs/ls1012aqds_ram_defconfig b/configs/ls1012aqds_ram_defconfig
new file mode 100644
index 0000000000..39805ccf9e
--- /dev/null
+++ b/configs/ls1012aqds_ram_defconfig
@@ -0,0 +1,62 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1012AQDS=y
+CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_QSPI_AHB_INIT=y
+CONFIG_TFABOOT=y
+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_NR_DRAM_BANKS=2
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000"
+# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_MISC_INIT_R=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_DATE=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_SCSI_AHCI=y
+# CONFIG_BLK is not set
+CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_FSL_PFE=y
+CONFIG_DM_ETH=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SCSI=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_STORAGE=y
--
2.17.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [U-Boot] [PATCH 24/53] armv8: ls1012a: update environment address for TFABOOT
2018-10-03 10:44 [U-Boot] [PATCH 00/53] TF-A Boot support for NXP Chassis 2 platforms Rajesh Bhagat
` (22 preceding siblings ...)
2018-10-03 10:44 ` [U-Boot] [PATCH 23/53] armv8: ls1012aqds: " Rajesh Bhagat
@ 2018-10-03 10:44 ` Rajesh Bhagat
2018-10-03 10:44 ` [U-Boot] [PATCH 25/53] armv8: ls1012a: define BOOTCOMMAND " Rajesh Bhagat
` (5 subsequent siblings)
29 siblings, 0 replies; 32+ messages in thread
From: Rajesh Bhagat @ 2018-10-03 10:44 UTC (permalink / raw)
To: u-boot
Update environment address for TFABOOT from 3MB to 5MB
offset. Required to support new flash layout used by
TFA.
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
---
include/configs/ls1012a_common.h | 4 ++++
include/configs/ls1012afrwy.h | 4 ++++
2 files changed, 8 insertions(+)
diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
index 07998f7eee..8f1f63920e 100644
--- a/include/configs/ls1012a_common.h
+++ b/include/configs/ls1012a_common.h
@@ -62,7 +62,11 @@
#define CONFIG_ENV_OVERWRITE
#define CONFIG_ENV_SIZE 0x40000 /* 256KB */
+#ifdef CONFIG_TFABOOT
+#define CONFIG_ENV_OFFSET 0x500000 /* 5MB */
+#else
#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
+#endif
#define CONFIG_ENV_SECT_SIZE 0x40000
#endif
diff --git a/include/configs/ls1012afrwy.h b/include/configs/ls1012afrwy.h
index 8129595d51..ae85ec1e72 100644
--- a/include/configs/ls1012afrwy.h
+++ b/include/configs/ls1012afrwy.h
@@ -31,7 +31,11 @@
#endif
#undef CONFIG_ENV_OFFSET
+#ifdef CONFIG_TFABOOT
+#define CONFIG_ENV_OFFSET 0x500000
+#else
#define CONFIG_ENV_OFFSET 0x1D0000
+#endif
#undef FSL_QSPI_FLASH_SIZE
#define FSL_QSPI_FLASH_SIZE SZ_16M
#undef CONFIG_ENV_SECT_SIZE
--
2.17.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [U-Boot] [PATCH 25/53] armv8: ls1012a: define BOOTCOMMAND for TFABOOT
2018-10-03 10:44 [U-Boot] [PATCH 00/53] TF-A Boot support for NXP Chassis 2 platforms Rajesh Bhagat
` (23 preceding siblings ...)
2018-10-03 10:44 ` [U-Boot] [PATCH 24/53] armv8: ls1012a: update environment address for TFABOOT Rajesh Bhagat
@ 2018-10-03 10:44 ` Rajesh Bhagat
2018-10-03 10:44 ` [U-Boot] [PATCH 26/53] armv8: layerscape: remove EL3 specific erratas " Rajesh Bhagat
` (4 subsequent siblings)
29 siblings, 0 replies; 32+ messages in thread
From: Rajesh Bhagat @ 2018-10-03 10:44 UTC (permalink / raw)
To: u-boot
From: Pankit Garg <pankit.garg@nxp.com>
Defines BOOTCOMMAND for TFABOOT configuration for
supported boot sources
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
---
include/configs/ls1012a2g5rdb.h | 6 ++++++
include/configs/ls1012a_common.h | 6 ++++++
include/configs/ls1012afrdm.h | 5 +++++
include/configs/ls1012afrwy.h | 6 ++++++
include/configs/ls1012ardb.h | 6 ++++++
5 files changed, 29 insertions(+)
diff --git a/include/configs/ls1012a2g5rdb.h b/include/configs/ls1012a2g5rdb.h
index 71e4a8b427..cb329385d9 100644
--- a/include/configs/ls1012a2g5rdb.h
+++ b/include/configs/ls1012a2g5rdb.h
@@ -93,10 +93,16 @@
"bootm $load_addr#$board\0"
#undef CONFIG_BOOTCOMMAND
+#ifdef CONFIG_TFABOOT
+#undef QSPI_NOR_BOOTCOMMAND
+#define QSPI_NOR_BOOTCOMMAND "pfe stop;run distro_bootcmd; run qspi_bootcmd; " \
+ "env exists secureboot && esbc_halt;"
+#else
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_BOOTCOMMAND "pfe stop;run distro_bootcmd; run qspi_bootcmd; " \
"env exists secureboot && esbc_halt;"
#endif
+#endif
#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
#define DEFAULT_PFE_MDIO1_NAME "PFE_MDIO1"
diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
index 8f1f63920e..324dba2b7e 100644
--- a/include/configs/ls1012a_common.h
+++ b/include/configs/ls1012a_common.h
@@ -114,9 +114,15 @@
"kernel_size=0x2800000\0" \
#undef CONFIG_BOOTCOMMAND
+#ifdef CONFIG_TFABOOT
+#define QSPI_NOR_BOOTCOMMAND "pfe stop; sf probe 0:0; sf read $kernel_load "\
+ "$kernel_start $kernel_size && "\
+ "bootm $kernel_load"
+#else
#define CONFIG_BOOTCOMMAND "pfe stop; sf probe 0:0; sf read $kernel_load "\
"$kernel_start $kernel_size && "\
"bootm $kernel_load"
+#endif
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h
index 7affabfdba..8c7d4e558d 100644
--- a/include/configs/ls1012afrdm.h
+++ b/include/configs/ls1012afrdm.h
@@ -65,7 +65,12 @@
"$kernel_addr $kernel_size && bootm $load_addr#$board\0"
#undef CONFIG_BOOTCOMMAND
+#ifdef CONFIG_TFABOOT
+#undef QSPI_NOR_BOOTCOMMAND
+#define QSPI_NOR_BOOTCOMMAND "pfe stop;run distro_bootcmd;run qspi_bootcmd"
+#else
#define CONFIG_BOOTCOMMAND "pfe stop;run distro_bootcmd;run qspi_bootcmd"
+#endif
#define CONFIG_CMD_MEMINFO
#define CONFIG_SYS_MEMTEST_START 0x80000000
diff --git a/include/configs/ls1012afrwy.h b/include/configs/ls1012afrwy.h
index ae85ec1e72..75ae329e11 100644
--- a/include/configs/ls1012afrwy.h
+++ b/include/configs/ls1012afrwy.h
@@ -123,8 +123,14 @@
"bootm $load_addr#$board\0"
#undef CONFIG_BOOTCOMMAND
+#ifdef CONFIG_TFABOOT
+#undef QSPI_NOR_BOOTCOMMAND
+#define QSPI_NOR_BOOTCOMMAND "pfe stop; run distro_bootcmd; run sd_bootcmd; "\
+ "env exists secureboot && esbc_halt;"
+#else
#define CONFIG_BOOTCOMMAND "pfe stop; run distro_bootcmd; run sd_bootcmd; "\
"env exists secureboot && esbc_halt;"
+#endif
#define CONFIG_CMD_MEMINFO
#define CONFIG_CMD_MEMTEST
#define CONFIG_SYS_MEMTEST_START 0x80000000
diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
index 17554ea955..f149a604cf 100644
--- a/include/configs/ls1012ardb.h
+++ b/include/configs/ls1012ardb.h
@@ -112,8 +112,14 @@
"bootm $load_addr#$board\0"
#undef CONFIG_BOOTCOMMAND
+#ifdef CONFIG_TFABOOT
+#undef QSPI_NOR_BOOTCOMMAND
+#define QSPI_NOR_BOOTCOMMAND "pfe stop; run distro_bootcmd; run qspi_bootcmd; "\
+ "env exists secureboot && esbc_halt;"
+#else
#define CONFIG_BOOTCOMMAND "pfe stop; run distro_bootcmd; run qspi_bootcmd; "\
"env exists secureboot && esbc_halt;"
+#endif
#include <asm/fsl_secure_boot.h>
--
2.17.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [U-Boot] [PATCH 26/53] armv8: layerscape: remove EL3 specific erratas for TFABOOT
2018-10-03 10:44 [U-Boot] [PATCH 00/53] TF-A Boot support for NXP Chassis 2 platforms Rajesh Bhagat
` (24 preceding siblings ...)
2018-10-03 10:44 ` [U-Boot] [PATCH 25/53] armv8: ls1012a: define BOOTCOMMAND " Rajesh Bhagat
@ 2018-10-03 10:44 ` Rajesh Bhagat
2018-10-03 10:44 ` [U-Boot] [PATCH 27/53] armv8: sec_firmware: return job ring status as true in TFABOOT Rajesh Bhagat
` (3 subsequent siblings)
29 siblings, 0 replies; 32+ messages in thread
From: Rajesh Bhagat @ 2018-10-03 10:44 UTC (permalink / raw)
To: u-boot
Removes EL3 specific erratas for TFABOOT, And now taken care in TFA.
ARM_ERRATA_855873, SYS_FSL_ERRATUM_A008850, SYS_FSL_ERRATUM_A008511,
SYS_FSL_ERRATUM_A008336, SYS_FSL_ERRATUM_A009663, SYS_FSL_ERRATUM_A009803
SYS_FSL_ERRATUM_A009942, SYS_FSL_ERRATUM_A010165
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
---
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 24 +++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 9092757d1f..1872c66dcd 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -1,7 +1,7 @@
config ARCH_LS1012A
bool
select ARMV8_SET_SMPEN
- select ARM_ERRATA_855873
+ select ARM_ERRATA_855873 if !TFABOOT
select FSL_LSCH2
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
@@ -22,22 +22,22 @@ config ARCH_LS1012A
config ARCH_LS1043A
bool
select ARMV8_SET_SMPEN
- select ARM_ERRATA_855873
+ select ARM_ERRATA_855873 if !TFABOOT
select FSL_LSCH2
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR
select SYS_FSL_DDR_BE
select SYS_FSL_DDR_VER_50
- select SYS_FSL_ERRATUM_A008850
+ select SYS_FSL_ERRATUM_A008850 if !TFABOOT
select SYS_FSL_ERRATUM_A008997
select SYS_FSL_ERRATUM_A009007
select SYS_FSL_ERRATUM_A009008
- select SYS_FSL_ERRATUM_A009660
- select SYS_FSL_ERRATUM_A009663
+ select SYS_FSL_ERRATUM_A009660 if !TFABOOT
+ select SYS_FSL_ERRATUM_A009663 if !TFABOOT
select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A009929
- select SYS_FSL_ERRATUM_A009942
+ select SYS_FSL_ERRATUM_A009942 if !TFABOOT
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_ERRATUM_A010539
select SYS_FSL_HAS_DDR3
@@ -62,17 +62,17 @@ config ARCH_LS1046A
select SYS_FSL_DDR
select SYS_FSL_DDR_BE
select SYS_FSL_DDR_VER_50
- select SYS_FSL_ERRATUM_A008336
- select SYS_FSL_ERRATUM_A008511
- select SYS_FSL_ERRATUM_A008850
+ select SYS_FSL_ERRATUM_A008336 if !TFABOOT
+ select SYS_FSL_ERRATUM_A008511 if !TFABOOT
+ select SYS_FSL_ERRATUM_A008850 if !TFABOOT
select SYS_FSL_ERRATUM_A008997
select SYS_FSL_ERRATUM_A009007
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A009801
- select SYS_FSL_ERRATUM_A009803
- select SYS_FSL_ERRATUM_A009942
- select SYS_FSL_ERRATUM_A010165
+ select SYS_FSL_ERRATUM_A009803 if !TFABOOT
+ select SYS_FSL_ERRATUM_A009942 if !TFABOOT
+ select SYS_FSL_ERRATUM_A010165 if !TFABOOT
select SYS_FSL_ERRATUM_A010539
select SYS_FSL_HAS_DDR4
select SYS_FSL_SRDS_2
--
2.17.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [U-Boot] [PATCH 27/53] armv8: sec_firmware: return job ring status as true in TFABOOT
2018-10-03 10:44 [U-Boot] [PATCH 00/53] TF-A Boot support for NXP Chassis 2 platforms Rajesh Bhagat
` (25 preceding siblings ...)
2018-10-03 10:44 ` [U-Boot] [PATCH 26/53] armv8: layerscape: remove EL3 specific erratas " Rajesh Bhagat
@ 2018-10-03 10:44 ` Rajesh Bhagat
2018-10-03 10:44 ` [U-Boot] [PATCH 28/53] armv8: layerscape: secure boot support for environment selection Rajesh Bhagat
` (2 subsequent siblings)
29 siblings, 0 replies; 32+ messages in thread
From: Rajesh Bhagat @ 2018-10-03 10:44 UTC (permalink / raw)
To: u-boot
From: Pankit Garg <pankit.garg@nxp.com>
Returns job ring status as true in TFABOOT, as one job ring is always
reserved.
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
---
arch/arm/cpu/armv8/sec_firmware.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/cpu/armv8/sec_firmware.c b/arch/arm/cpu/armv8/sec_firmware.c
index a13c92e246..8dc0ac9266 100644
--- a/arch/arm/cpu/armv8/sec_firmware.c
+++ b/arch/arm/cpu/armv8/sec_firmware.c
@@ -348,6 +348,10 @@ unsigned int sec_firmware_support_psci_version(void)
*/
bool sec_firmware_support_hwrng(void)
{
+#ifdef CONFIG_TFABOOT
+ /* return true as TFA has one job ring reserved */
+ return true;
+#endif
if (sec_firmware_addr & SEC_FIRMWARE_RUNNING) {
return true;
}
--
2.17.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [U-Boot] [PATCH 28/53] armv8: layerscape: secure boot support for environment selection
2018-10-03 10:44 [U-Boot] [PATCH 00/53] TF-A Boot support for NXP Chassis 2 platforms Rajesh Bhagat
` (26 preceding siblings ...)
2018-10-03 10:44 ` [U-Boot] [PATCH 27/53] armv8: sec_firmware: return job ring status as true in TFABOOT Rajesh Bhagat
@ 2018-10-03 10:44 ` Rajesh Bhagat
2018-10-03 10:44 ` [U-Boot] [PATCH 29/53] armv8: layerscape: add SMC calls for DDR size and bank info Rajesh Bhagat
2018-10-03 10:44 ` [U-Boot] [PATCH 30/53] armv8: layerscape: skip OCRAM init for TFABOOT Rajesh Bhagat
29 siblings, 0 replies; 32+ messages in thread
From: Rajesh Bhagat @ 2018-10-03 10:44 UTC (permalink / raw)
To: u-boot
Add secure boot support for environment selection.
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
---
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 1ab4d93638..063a8fea55 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -33,6 +33,9 @@
#ifdef CONFIG_TFABOOT
#include <environment.h>
+#ifdef CONFIG_CHAIN_OF_TRUST
+#include <fsl_validate.h>
+#endif
#endif
DECLARE_GLOBAL_DATA_PTR;
@@ -738,6 +741,14 @@ enum env_location env_get_location(enum env_operation op, int prio)
if (prio)
return ENVL_UNKNOWN;
+#ifdef CONFIG_CHAIN_OF_TRUST
+ /* Check Boot Mode
+ * If Boot Mode is Secure, return ENVL_NOWHERE
+ */
+ if (fsl_check_boot_mode_secure() == 1)
+ goto done;
+#endif
+
switch (src) {
case BOOT_SOURCE_IFC_NOR:
env_loc = ENVL_FLASH;
@@ -765,6 +776,9 @@ enum env_location env_get_location(enum env_operation op, int prio)
break;
}
+#ifdef CONFIG_CHAIN_OF_TRUST
+done:
+#endif
return env_loc;
}
--
2.17.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [U-Boot] [PATCH 29/53] armv8: layerscape: add SMC calls for DDR size and bank info.
2018-10-03 10:44 [U-Boot] [PATCH 00/53] TF-A Boot support for NXP Chassis 2 platforms Rajesh Bhagat
` (27 preceding siblings ...)
2018-10-03 10:44 ` [U-Boot] [PATCH 28/53] armv8: layerscape: secure boot support for environment selection Rajesh Bhagat
@ 2018-10-03 10:44 ` Rajesh Bhagat
2018-10-03 10:44 ` [U-Boot] [PATCH 30/53] armv8: layerscape: skip OCRAM init for TFABOOT Rajesh Bhagat
29 siblings, 0 replies; 32+ messages in thread
From: Rajesh Bhagat @ 2018-10-03 10:44 UTC (permalink / raw)
To: u-boot
From: Pankit Garg <pankit.garg@nxp.com>
Adds SMC calls for getting DDR size and bank info for TFABOOT.
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
---
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 84 +++++++++++++++++++
.../arm/include/asm/arch-fsl-layerscape/soc.h | 4 +
board/freescale/ls1012aqds/ls1012aqds.c | 4 +-
board/freescale/ls1012ardb/ls1012ardb.c | 4 +-
board/freescale/ls1043aqds/ddr.c | 14 +++-
board/freescale/ls1043ardb/ddr.c | 20 ++++-
board/freescale/ls1046aqds/ddr.c | 14 +++-
board/freescale/ls1046ardb/ddr.c | 15 +++-
8 files changed, 147 insertions(+), 12 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 063a8fea55..024600c694 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -1227,12 +1227,96 @@ phys_size_t get_effective_memsize(void)
return ea_size;
}
+#ifdef CONFIG_TFABOOT
+phys_size_t tfa_get_dram_size(void)
+{
+ struct pt_regs regs;
+ phys_size_t dram_size = 0;
+
+ regs.regs[0] = SMC_DRAM_BANK_INFO;
+ regs.regs[1] = -1;
+
+ smc_call(®s);
+ if (regs.regs[0])
+ return 0;
+
+ dram_size = regs.regs[1];
+ return dram_size;
+}
+
+static int tfa_dram_init_banksize(void)
+{
+ int i = 0, ret = 0;
+ struct pt_regs regs;
+ phys_size_t dram_size = tfa_get_dram_size();
+
+ debug("dram_size %llx\n", dram_size);
+
+ if (!dram_size)
+ return -EINVAL;
+
+ do {
+ regs.regs[0] = SMC_DRAM_BANK_INFO;
+ regs.regs[1] = i;
+
+ smc_call(®s);
+ if (regs.regs[0]) {
+ ret = -EINVAL;
+ break;
+ }
+
+ debug("bank[%d]: start %lx, size %lx\n", i, regs.regs[1],
+ regs.regs[2]);
+ gd->bd->bi_dram[i].start = regs.regs[1];
+ gd->bd->bi_dram[i].size = regs.regs[2];
+
+ dram_size -= gd->bd->bi_dram[i].size;
+
+ i++;
+ } while (dram_size);
+
+ if (i > 0)
+ ret = 0;
+
+#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
+ /* Assign memory for MC */
+#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
+ if (gd->bd->bi_dram[2].size >=
+ board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
+ gd->arch.resv_ram = gd->bd->bi_dram[2].start +
+ gd->bd->bi_dram[2].size -
+ board_reserve_ram_top(gd->bd->bi_dram[2].size);
+ } else
+#endif
+ {
+ if (gd->bd->bi_dram[1].size >=
+ board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
+ gd->arch.resv_ram = gd->bd->bi_dram[1].start +
+ gd->bd->bi_dram[1].size -
+ board_reserve_ram_top(gd->bd->bi_dram[1].size);
+ } else if (gd->bd->bi_dram[0].size >
+ board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
+ gd->arch.resv_ram = gd->bd->bi_dram[0].start +
+ gd->bd->bi_dram[0].size -
+ board_reserve_ram_top(gd->bd->bi_dram[0].size);
+ }
+ }
+#endif /* CONFIG_FSL_MC_ENET */
+
+ return ret;
+}
+#endif
+
int dram_init_banksize(void)
{
#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
phys_size_t dp_ddr_size;
#endif
+#ifdef CONFIG_TFABOOT
+ if (!tfa_dram_init_banksize())
+ return 0;
+#endif
/*
* gd->ram_size has the total size of DDR memory, less reserved secure
* memory. The DDR extends from low region to high region(s) presuming
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index d327c7ba1f..ef228b6443 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -55,6 +55,10 @@ struct cpu_type {
{ .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
#ifdef CONFIG_TFABOOT
+#define SMC_DRAM_BANK_INFO (0xC200FF12)
+
+phys_size_t tfa_get_dram_size(void);
+
enum boot_src {
BOOT_SOURCE_RESERVED = 0,
BOOT_SOURCE_IFC_NOR,
diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
index f312200433..7582f5e430 100644
--- a/board/freescale/ls1012aqds/ls1012aqds.c
+++ b/board/freescale/ls1012aqds/ls1012aqds.c
@@ -58,7 +58,9 @@ int checkboard(void)
#ifdef CONFIG_TFABOOT
int dram_init(void)
{
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ gd->ram_size = tfa_get_dram_size();
+ if (!gd->ram_size)
+ gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
return 0;
}
diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
index f59749b87c..66554bcf6e 100644
--- a/board/freescale/ls1012ardb/ls1012ardb.c
+++ b/board/freescale/ls1012ardb/ls1012ardb.c
@@ -90,7 +90,9 @@ int checkboard(void)
#ifdef CONFIG_TFABOOT
int dram_init(void)
{
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ gd->ram_size = tfa_get_dram_size();
+ if (!gd->ram_size)
+ gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
return 0;
}
diff --git a/board/freescale/ls1043aqds/ddr.c b/board/freescale/ls1043aqds/ddr.c
index a79d8e2120..d29a3ad797 100644
--- a/board/freescale/ls1043aqds/ddr.c
+++ b/board/freescale/ls1043aqds/ddr.c
@@ -108,12 +108,21 @@ found:
#endif
}
+#ifdef CONFIG_TFABOOT
+int fsl_initdram(void)
+{
+ gd->ram_size = tfa_get_dram_size();
+ if (!gd->ram_size)
+ gd->ram_size = fsl_ddr_sdram_size();
+
+ return 0;
+}
+#else
int fsl_initdram(void)
{
phys_size_t dram_size;
-#if defined(CONFIG_TFABOOT) || \
- (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
+#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
gd->ram_size = fsl_ddr_sdram_size();
return 0;
@@ -132,3 +141,4 @@ int fsl_initdram(void)
return 0;
}
+#endif
diff --git a/board/freescale/ls1043ardb/ddr.c b/board/freescale/ls1043ardb/ddr.c
index 1fb1635dfb..784e482f32 100644
--- a/board/freescale/ls1043ardb/ddr.c
+++ b/board/freescale/ls1043ardb/ddr.c
@@ -205,21 +205,32 @@ phys_size_t fixed_sdram(void)
}
#endif
+#ifdef CONFIG_TFABOOT
+int fsl_initdram(void)
+{
+ gd->ram_size = tfa_get_dram_size();
+ if (!gd->ram_size)
+#ifdef CONFIG_SYS_DDR_RAW_TIMING
+ gd->ram_size = fsl_ddr_sdram_size();
+#else
+ gd->ram_size = 0x80000000;
+#endif
+ return 0;
+}
+#else
int fsl_initdram(void)
{
phys_size_t dram_size;
#ifdef CONFIG_SYS_DDR_RAW_TIMING
-#if !defined(CONFIG_TFABOOT) && \
- (defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL))
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL)
puts("Initializing DDR....\n");
dram_size = fsl_ddr_sdram();
#else
dram_size = fsl_ddr_sdram_size();
#endif
#else
-#if !defined(CONFIG_TFABOOT) && \
- (defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL))
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL)
puts("Initialzing DDR using fixed setting\n");
dram_size = fixed_sdram();
#else
@@ -238,3 +249,4 @@ int fsl_initdram(void)
return 0;
}
+#endif
diff --git a/board/freescale/ls1046aqds/ddr.c b/board/freescale/ls1046aqds/ddr.c
index d2afe62cfc..45b1f373a7 100644
--- a/board/freescale/ls1046aqds/ddr.c
+++ b/board/freescale/ls1046aqds/ddr.c
@@ -92,12 +92,21 @@ found:
popts->cpo_sample = 0x70;
}
+#ifdef CONFIG_TFABOOT
+int fsl_initdram(void)
+{
+ gd->ram_size = tfa_get_dram_size();
+ if (!gd->ram_size)
+ gd->ram_size = fsl_ddr_sdram_size();
+
+ return 0;
+}
+#else
int fsl_initdram(void)
{
phys_size_t dram_size;
-#if defined(CONFIG_TFABOOT) || \
- (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
+#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
gd->ram_size = fsl_ddr_sdram_size();
return 0;
@@ -117,3 +126,4 @@ int fsl_initdram(void)
return 0;
}
+#endif
diff --git a/board/freescale/ls1046ardb/ddr.c b/board/freescale/ls1046ardb/ddr.c
index 8fe0794198..321222d68d 100644
--- a/board/freescale/ls1046ardb/ddr.c
+++ b/board/freescale/ls1046ardb/ddr.c
@@ -97,12 +97,22 @@ found:
popts->cpo_sample = 0x61;
}
+#ifdef CONFIG_TFABOOT
+int fsl_initdram(void)
+{
+ gd->ram_size = tfa_get_dram_size();
+
+ if (!gd->ram_size)
+ gd->ram_size = fsl_ddr_sdram_size();
+
+ return 0;
+}
+#else
int fsl_initdram(void)
{
phys_size_t dram_size;
-#if defined(CONFIG_TFABOOT) || \
- (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
+#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
gd->ram_size = fsl_ddr_sdram_size();
return 0;
@@ -118,3 +128,4 @@ int fsl_initdram(void)
return 0;
}
+#endif
--
2.17.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [U-Boot] [PATCH 30/53] armv8: layerscape: skip OCRAM init for TFABOOT
2018-10-03 10:44 [U-Boot] [PATCH 00/53] TF-A Boot support for NXP Chassis 2 platforms Rajesh Bhagat
` (28 preceding siblings ...)
2018-10-03 10:44 ` [U-Boot] [PATCH 29/53] armv8: layerscape: add SMC calls for DDR size and bank info Rajesh Bhagat
@ 2018-10-03 10:44 ` Rajesh Bhagat
29 siblings, 0 replies; 32+ messages in thread
From: Rajesh Bhagat @ 2018-10-03 10:44 UTC (permalink / raw)
To: u-boot
OCRAM initialization is performed by TFA, Hence
skipped from u-boot.
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
---
arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index ef3987ea84..acaa6d6e37 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -295,7 +295,8 @@ ENTRY(lowlevel_init)
100:
#endif
-#if defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_TFABOOT) && \
+ (defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD))
bl fsl_ocram_init
#endif
--
2.17.1
^ permalink raw reply related [flat|nested] 32+ messages in thread