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* [PATCH 1/3] drm/i915/execlists: Force write serialisation into context image vs execution
@ 2018-11-08  8:17 Chris Wilson
  2018-11-08  8:17 ` [PATCH 2/3] drm/i915: Return immediately if trylock fails for direct-reclaim Chris Wilson
                   ` (5 more replies)
  0 siblings, 6 replies; 19+ messages in thread
From: Chris Wilson @ 2018-11-08  8:17 UTC (permalink / raw)
  To: intel-gfx

Ensure that the writes into the context image are completed prior to the
register mmio to trigger execution. Although previously we were assured
by the SDM that all writes are flushed before an uncached memory
transaction (our mmio write to submit the context to HW for execution),
we have empirical evidence to believe that this is not actually the
case.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108656
References: https://bugs.freedesktop.org/show_bug.cgi?id=108315
References: https://bugs.freedesktop.org/show_bug.cgi?id=106887
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/intel_lrc.c | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 22b57b8926fc..f7892ddb3f13 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -380,7 +380,8 @@ static u64 execlists_update_context(struct i915_request *rq)
 
 	reg_state[CTX_RING_TAIL+1] = intel_ring_set_tail(rq->ring, rq->tail);
 
-	/* True 32b PPGTT with dynamic page allocation: update PDP
+	/*
+	 * True 32b PPGTT with dynamic page allocation: update PDP
 	 * registers and point the unallocated PDPs to scratch page.
 	 * PML4 is allocated during ppgtt init, so this is not needed
 	 * in 48-bit mode.
@@ -388,6 +389,17 @@ static u64 execlists_update_context(struct i915_request *rq)
 	if (!i915_vm_is_48bit(&ppgtt->vm))
 		execlists_update_context_pdps(ppgtt, reg_state);
 
+	/*
+	 * Make sure the context image is complete before we submit it to HW.
+	 *
+	 * Ostensibly, writes (including the WCB) should be flushed prior to
+	 * an uncached write such as our mmio register access, the empirical
+	 * evidence (esp. on Braswell) suggests that the WC write into memory
+	 * may not be visible to the HW prior to the completion of the UC
+	 * register write and that we may begin execution from the context
+	 * before its image is complete leading to invalid PD chasing.
+	 */
+	wmb();
 	return ce->lrc_desc;
 }
 
-- 
2.19.1

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^ permalink raw reply related	[flat|nested] 19+ messages in thread

end of thread, other threads:[~2018-11-15 11:39 UTC | newest]

Thread overview: 19+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-11-08  8:17 [PATCH 1/3] drm/i915/execlists: Force write serialisation into context image vs execution Chris Wilson
2018-11-08  8:17 ` [PATCH 2/3] drm/i915: Return immediately if trylock fails for direct-reclaim Chris Wilson
2018-11-08 16:23   ` Tvrtko Ursulin
2018-11-08 16:48     ` Chris Wilson
2018-11-09  7:30       ` Tvrtko Ursulin
2018-11-09 11:44         ` Chris Wilson
2018-11-13 10:24           ` Tvrtko Ursulin
2018-11-13 17:10             ` Chris Wilson
2018-11-15 11:39               ` Tvrtko Ursulin
2018-11-08  8:17 ` [PATCH 3/3] drm/i915/userptr: Avoid struct_mutex recursion for mmu_invalidate_range_start Chris Wilson
2018-11-08 16:45   ` Tvrtko Ursulin
2018-11-08  8:33 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/execlists: Force write serialisation into context image vs execution Patchwork
2018-11-08  9:07 ` ✓ Fi.CI.BAT: success " Patchwork
2018-11-08 12:00 ` [PATCH 1/3] " Mika Kuoppala
2018-11-08 12:11   ` Chris Wilson
2018-11-08 12:13     ` Mika Kuoppala
2018-11-08 12:26       ` Chris Wilson
2018-11-08 13:38     ` Chris Wilson
2018-11-08 19:51 ` ✓ Fi.CI.IGT: success for series starting with [1/3] " Patchwork

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