From: Maxime Ripard <maxime.ripard-LDxbnhwyfcJBDgjK7y7TUQ@public.gmane.org>
To: "Uwe Kleine-König"
<u.kleine-koenig-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
Cc: Hao Zhang <hao5781286-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
mark.rutland-5wv7dgnIgG8@public.gmane.org,
wens-jdAy2FN1RRM@public.gmane.org,
mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org,
sboyd-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-pwm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org
Subject: Re: [PATCH v3 1/6] Documentation: ARM: sunxi: pwm: add Allwinner sun8i.
Date: Tue, 27 Nov 2018 11:32:53 +0100 [thread overview]
Message-ID: <20181127103253.ubbjjy2ji6sxc7xs@flea> (raw)
In-Reply-To: <20181127083523.pciie2gyaplrwiey-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
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On Tue, Nov 27, 2018 at 09:35:23AM +0100, Uwe Kleine-König wrote:
> Hello,
>
> On Tue, Nov 27, 2018 at 08:52:26AM +0100, Maxime Ripard wrote:
> > On Mon, Nov 26, 2018 at 12:18:59AM +0800, Hao Zhang wrote:
> > > + - clocks: From common clock binding, handle to the parent clock.
> > > + - clock-names: Must contain the clock names described just above.
> >
> > [...]
> >
> > You seem to have used mux-0 and mux-1 for the clock names. I guess we
> > don't have to use a name there, we can simply use the position to find
> > out (as long as it's documented in the binding)
>
> I also wondered if the driver relies on the fact that the second clock
> is the faster running one. Is this sensible?
Not really, I'm not sure we can make those expectations in the DT
binding, especially since clock rate can change at runtime.
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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From: Maxime Ripard <maxime.ripard@bootlin.com>
To: "Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>
Cc: Hao Zhang <hao5781286@gmail.com>,
robh+dt@kernel.org, mark.rutland@arm.com, wens@csie.org,
mturquette@baylibre.com, sboyd@kernel.org,
thierry.reding@gmail.com, linux-gpio@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, linux-pwm@vger.kernel.org,
linux-sunxi@googlegroups.com
Subject: Re: [PATCH v3 1/6] Documentation: ARM: sunxi: pwm: add Allwinner sun8i.
Date: Tue, 27 Nov 2018 11:32:53 +0100 [thread overview]
Message-ID: <20181127103253.ubbjjy2ji6sxc7xs@flea> (raw)
In-Reply-To: <20181127083523.pciie2gyaplrwiey@pengutronix.de>
[-- Attachment #1: Type: text/plain, Size: 946 bytes --]
On Tue, Nov 27, 2018 at 09:35:23AM +0100, Uwe Kleine-König wrote:
> Hello,
>
> On Tue, Nov 27, 2018 at 08:52:26AM +0100, Maxime Ripard wrote:
> > On Mon, Nov 26, 2018 at 12:18:59AM +0800, Hao Zhang wrote:
> > > + - clocks: From common clock binding, handle to the parent clock.
> > > + - clock-names: Must contain the clock names described just above.
> >
> > [...]
> >
> > You seem to have used mux-0 and mux-1 for the clock names. I guess we
> > don't have to use a name there, we can simply use the position to find
> > out (as long as it's documented in the binding)
>
> I also wondered if the driver relies on the fact that the second clock
> is the faster running one. Is this sensible?
Not really, I'm not sure we can make those expectations in the DT
binding, especially since clock rate can change at runtime.
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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WARNING: multiple messages have this Message-ID (diff)
From: maxime.ripard@bootlin.com (Maxime Ripard)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 1/6] Documentation: ARM: sunxi: pwm: add Allwinner sun8i.
Date: Tue, 27 Nov 2018 11:32:53 +0100 [thread overview]
Message-ID: <20181127103253.ubbjjy2ji6sxc7xs@flea> (raw)
In-Reply-To: <20181127083523.pciie2gyaplrwiey@pengutronix.de>
On Tue, Nov 27, 2018 at 09:35:23AM +0100, Uwe Kleine-K?nig wrote:
> Hello,
>
> On Tue, Nov 27, 2018 at 08:52:26AM +0100, Maxime Ripard wrote:
> > On Mon, Nov 26, 2018 at 12:18:59AM +0800, Hao Zhang wrote:
> > > + - clocks: From common clock binding, handle to the parent clock.
> > > + - clock-names: Must contain the clock names described just above.
> >
> > [...]
> >
> > You seem to have used mux-0 and mux-1 for the clock names. I guess we
> > don't have to use a name there, we can simply use the position to find
> > out (as long as it's documented in the binding)
>
> I also wondered if the driver relies on the fact that the second clock
> is the faster running one. Is this sensible?
Not really, I'm not sure we can make those expectations in the DT
binding, especially since clock rate can change at runtime.
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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next prev parent reply other threads:[~2018-11-27 10:32 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-25 16:18 [PATCH v3 1/6] Documentation: ARM: sunxi: pwm: add Allwinner sun8i Hao Zhang
2018-11-25 16:18 ` Hao Zhang
2018-11-25 16:18 ` Hao Zhang
2018-11-27 1:57 ` Rob Herring
2018-11-27 1:57 ` Rob Herring
2018-11-27 1:57 ` Rob Herring
2018-11-27 7:04 ` Uwe Kleine-König
2018-11-27 7:04 ` Uwe Kleine-König
2018-11-27 7:52 ` Maxime Ripard
2018-11-27 7:52 ` Maxime Ripard
2018-11-27 7:52 ` Maxime Ripard
2018-11-27 8:35 ` Uwe Kleine-König
2018-11-27 8:35 ` Uwe Kleine-König
[not found] ` <20181127083523.pciie2gyaplrwiey-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
2018-11-27 10:32 ` Maxime Ripard [this message]
2018-11-27 10:32 ` Maxime Ripard
2018-11-27 10:32 ` Maxime Ripard
[not found] ` <CAJeuY79RRzTqLpaXSe5d8TuNKGeQeYLbXraRVrZk9HBMYBf1+A@mail.gmail.com>
[not found] ` <CAJeuY79RRzTqLpaXSe5d8TuNKGeQeYLbXraRVrZk9HBMYBf1+A-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-12-03 9:28 ` Maxime Ripard
2018-12-03 9:28 ` Maxime Ripard
2018-12-03 9:28 ` Maxime Ripard
2018-12-20 17:50 ` Thierry Reding
2018-12-20 17:50 ` Thierry Reding
2018-12-20 17:50 ` Thierry Reding
[not found] ` <CAJeuY7-StNNDpBPyw1JH5Jmc-NhDw67F6Veh0S2tBTmENCTY8Q@mail.gmail.com>
[not found] ` <CAJeuY7-StNNDpBPyw1JH5Jmc-NhDw67F6Veh0S2tBTmENCTY8Q-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2019-03-12 5:03 ` Fwd: " Hao Zhang
2019-03-12 5:03 ` Hao Zhang
2019-03-12 5:03 ` Hao Zhang
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