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From: Hao Zhang <hao5781286-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
To: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>,
	Maxime Ripard
	<maxime.ripard-LDxbnhwyfcJBDgjK7y7TUQ@public.gmane.org>,
	Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>,
	Michael Turquette
	<mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>,
	sboyd-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
	linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	open list <linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
	"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
	<devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
	"moderated list:ARM/Allwinner sunXi SoC support"
	<linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>,
	linux-pwm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org,
	Hao Zhang <hao5781286-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Subject: Fwd: [PATCH v3 1/6] Documentation: ARM: sunxi: pwm: add Allwinner sun8i.
Date: Tue, 12 Mar 2019 13:03:19 +0800	[thread overview]
Message-ID: <CAJeuY7_gx=PBhF4t40nCCWia-aq1G3t9D9nKS7ejOh56t2RkHQ@mail.gmail.com> (raw)
In-Reply-To: <CAJeuY7-StNNDpBPyw1JH5Jmc-NhDw67F6Veh0S2tBTmENCTY8Q-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>

---------- Forwarded message ---------
From: Hao Zhang <hao5781286-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Date: 2019年3月12日周二 下午12:59
Subject: Re: [PATCH v3 1/6] Documentation: ARM: sunxi: pwm: add Allwinner sun8i.
To: Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>


Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 于2018年12月21日周五 上午1:50写道:
>
> On Mon, Nov 26, 2018 at 12:18:59AM +0800, Hao Zhang wrote:
> > This patch adds Allwinner sun8i pwm binding document.
> >
> > Signed-off-by: Hao Zhang <hao5781286-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> > ---
> >  .../devicetree/bindings/pwm/pwm-sun8i.txt          | 24 ++++++++++++++++++++++
> >  1 file changed, 24 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/pwm/pwm-sun8i.txt
> >
> > diff --git a/Documentation/devicetree/bindings/pwm/pwm-sun8i.txt b/Documentation/devicetree/bindings/pwm/pwm-sun8i.txt
> > new file mode 100644
> > index 0000000..7531d85
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pwm/pwm-sun8i.txt
> > @@ -0,0 +1,24 @@
> > +Allwinner sun8i R40/V40/T3 SoC PWM controller
> > +
> > +Required properties:
> > +  - compatible: Should be one of:
> > +    - "allwinner,sun8i-r40-pwm"
> > +  - reg: Physical base address and length of the controller's registers
> > +  - interrupts: Should contain interrupt.
> > +  - clocks: From common clock binding, handle to the parent clock.
> > +  - clock-names: Must contain the clock names described just above.
> > +  - pwm-channels: PWM channels of the controller.
>
> Why do you need this? In the cover letter you say:
>
>         "The sun8i R40/T3/V40 PWM has 8 PWM channals ..."
>
> Why does this need to be specified in the DT?

T3 PWM has 8 channals, i think it is necessary to tell user how to
specify it Instead of
hardcode the channal myself :)

Thanks for review :)

>
> Thierry
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WARNING: multiple messages have this Message-ID (diff)
From: Hao Zhang <hao5781286@gmail.com>
To: Mark Rutland <mark.rutland@arm.com>,
	Maxime Ripard <maxime.ripard@bootlin.com>,
	Chen-Yu Tsai <wens@csie.org>,
	Michael Turquette <mturquette@baylibre.com>,
	sboyd@kernel.org, linux-gpio@vger.kernel.org,
	open list <linux-kernel@vger.kernel.org>,
	"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
	<devicetree@vger.kernel.org>,
	"moderated list:ARM/Allwinner sunXi SoC support" 
	<linux-arm-kernel@lists.infradead.org>,
	linux-pwm@vger.kernel.org, linux-sunxi@googlegroups.com,
	Hao Zhang <hao5781286@gmail.com>
Subject: Fwd: [PATCH v3 1/6] Documentation: ARM: sunxi: pwm: add Allwinner sun8i.
Date: Tue, 12 Mar 2019 13:03:19 +0800	[thread overview]
Message-ID: <CAJeuY7_gx=PBhF4t40nCCWia-aq1G3t9D9nKS7ejOh56t2RkHQ@mail.gmail.com> (raw)
In-Reply-To: <CAJeuY7-StNNDpBPyw1JH5Jmc-NhDw67F6Veh0S2tBTmENCTY8Q@mail.gmail.com>

---------- Forwarded message ---------
From: Hao Zhang <hao5781286@gmail.com>
Date: 2019年3月12日周二 下午12:59
Subject: Re: [PATCH v3 1/6] Documentation: ARM: sunxi: pwm: add Allwinner sun8i.
To: Thierry Reding <thierry.reding@gmail.com>


Thierry Reding <thierry.reding@gmail.com> 于2018年12月21日周五 上午1:50写道:
>
> On Mon, Nov 26, 2018 at 12:18:59AM +0800, Hao Zhang wrote:
> > This patch adds Allwinner sun8i pwm binding document.
> >
> > Signed-off-by: Hao Zhang <hao5781286@gmail.com>
> > ---
> >  .../devicetree/bindings/pwm/pwm-sun8i.txt          | 24 ++++++++++++++++++++++
> >  1 file changed, 24 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/pwm/pwm-sun8i.txt
> >
> > diff --git a/Documentation/devicetree/bindings/pwm/pwm-sun8i.txt b/Documentation/devicetree/bindings/pwm/pwm-sun8i.txt
> > new file mode 100644
> > index 0000000..7531d85
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pwm/pwm-sun8i.txt
> > @@ -0,0 +1,24 @@
> > +Allwinner sun8i R40/V40/T3 SoC PWM controller
> > +
> > +Required properties:
> > +  - compatible: Should be one of:
> > +    - "allwinner,sun8i-r40-pwm"
> > +  - reg: Physical base address and length of the controller's registers
> > +  - interrupts: Should contain interrupt.
> > +  - clocks: From common clock binding, handle to the parent clock.
> > +  - clock-names: Must contain the clock names described just above.
> > +  - pwm-channels: PWM channels of the controller.
>
> Why do you need this? In the cover letter you say:
>
>         "The sun8i R40/T3/V40 PWM has 8 PWM channals ..."
>
> Why does this need to be specified in the DT?

T3 PWM has 8 channals, i think it is necessary to tell user how to
specify it Instead of
hardcode the channal myself :)

Thanks for review :)

>
> Thierry
> -----BEGIN PGP SIGNATURE-----
>
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> =9v1O
> -----END PGP SIGNATURE-----

WARNING: multiple messages have this Message-ID (diff)
From: Hao Zhang <hao5781286@gmail.com>
To: Mark Rutland <mark.rutland@arm.com>,
	Maxime Ripard <maxime.ripard@bootlin.com>,
	 Chen-Yu Tsai <wens@csie.org>,
	Michael Turquette <mturquette@baylibre.com>,
	sboyd@kernel.org,  linux-gpio@vger.kernel.org,
	open list <linux-kernel@vger.kernel.org>,
	 "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
	<devicetree@vger.kernel.org>,
	 "moderated list:ARM/Allwinner sunXi SoC support"
	<linux-arm-kernel@lists.infradead.org>,
	linux-pwm@vger.kernel.org,  linux-sunxi@googlegroups.com,
	Hao Zhang <hao5781286@gmail.com>
Subject: Fwd: [PATCH v3 1/6] Documentation: ARM: sunxi: pwm: add Allwinner sun8i.
Date: Tue, 12 Mar 2019 13:03:19 +0800	[thread overview]
Message-ID: <CAJeuY7_gx=PBhF4t40nCCWia-aq1G3t9D9nKS7ejOh56t2RkHQ@mail.gmail.com> (raw)
In-Reply-To: <CAJeuY7-StNNDpBPyw1JH5Jmc-NhDw67F6Veh0S2tBTmENCTY8Q@mail.gmail.com>

---------- Forwarded message ---------
From: Hao Zhang <hao5781286@gmail.com>
Date: 2019年3月12日周二 下午12:59
Subject: Re: [PATCH v3 1/6] Documentation: ARM: sunxi: pwm: add Allwinner sun8i.
To: Thierry Reding <thierry.reding@gmail.com>


Thierry Reding <thierry.reding@gmail.com> 于2018年12月21日周五 上午1:50写道:
>
> On Mon, Nov 26, 2018 at 12:18:59AM +0800, Hao Zhang wrote:
> > This patch adds Allwinner sun8i pwm binding document.
> >
> > Signed-off-by: Hao Zhang <hao5781286@gmail.com>
> > ---
> >  .../devicetree/bindings/pwm/pwm-sun8i.txt          | 24 ++++++++++++++++++++++
> >  1 file changed, 24 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/pwm/pwm-sun8i.txt
> >
> > diff --git a/Documentation/devicetree/bindings/pwm/pwm-sun8i.txt b/Documentation/devicetree/bindings/pwm/pwm-sun8i.txt
> > new file mode 100644
> > index 0000000..7531d85
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pwm/pwm-sun8i.txt
> > @@ -0,0 +1,24 @@
> > +Allwinner sun8i R40/V40/T3 SoC PWM controller
> > +
> > +Required properties:
> > +  - compatible: Should be one of:
> > +    - "allwinner,sun8i-r40-pwm"
> > +  - reg: Physical base address and length of the controller's registers
> > +  - interrupts: Should contain interrupt.
> > +  - clocks: From common clock binding, handle to the parent clock.
> > +  - clock-names: Must contain the clock names described just above.
> > +  - pwm-channels: PWM channels of the controller.
>
> Why do you need this? In the cover letter you say:
>
>         "The sun8i R40/T3/V40 PWM has 8 PWM channals ..."
>
> Why does this need to be specified in the DT?

T3 PWM has 8 channals, i think it is necessary to tell user how to
specify it Instead of
hardcode the channal myself :)

Thanks for review :)

>
> Thierry
> -----BEGIN PGP SIGNATURE-----
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> -----END PGP SIGNATURE-----

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  parent reply	other threads:[~2019-03-12  5:03 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-25 16:18 [PATCH v3 1/6] Documentation: ARM: sunxi: pwm: add Allwinner sun8i Hao Zhang
2018-11-25 16:18 ` Hao Zhang
2018-11-25 16:18 ` Hao Zhang
2018-11-27  1:57 ` Rob Herring
2018-11-27  1:57   ` Rob Herring
2018-11-27  1:57   ` Rob Herring
2018-11-27  7:04 ` Uwe Kleine-König
2018-11-27  7:04   ` Uwe Kleine-König
2018-11-27  7:52 ` Maxime Ripard
2018-11-27  7:52   ` Maxime Ripard
2018-11-27  7:52   ` Maxime Ripard
2018-11-27  8:35   ` Uwe Kleine-König
2018-11-27  8:35     ` Uwe Kleine-König
     [not found]     ` <20181127083523.pciie2gyaplrwiey-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
2018-11-27 10:32       ` Maxime Ripard
2018-11-27 10:32         ` Maxime Ripard
2018-11-27 10:32         ` Maxime Ripard
     [not found]         ` <CAJeuY79RRzTqLpaXSe5d8TuNKGeQeYLbXraRVrZk9HBMYBf1+A@mail.gmail.com>
     [not found]           ` <CAJeuY79RRzTqLpaXSe5d8TuNKGeQeYLbXraRVrZk9HBMYBf1+A-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-12-03  9:28             ` Maxime Ripard
2018-12-03  9:28               ` Maxime Ripard
2018-12-03  9:28               ` Maxime Ripard
2018-12-20 17:50 ` Thierry Reding
2018-12-20 17:50   ` Thierry Reding
2018-12-20 17:50   ` Thierry Reding
     [not found]   ` <CAJeuY7-StNNDpBPyw1JH5Jmc-NhDw67F6Veh0S2tBTmENCTY8Q@mail.gmail.com>
     [not found]     ` <CAJeuY7-StNNDpBPyw1JH5Jmc-NhDw67F6Veh0S2tBTmENCTY8Q-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2019-03-12  5:03       ` Hao Zhang [this message]
2019-03-12  5:03         ` Fwd: " Hao Zhang
2019-03-12  5:03         ` Hao Zhang

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