* [PATCH 1/3] ARM: dts: cyclone5: Add stmmac ptp_ref clock
@ 2018-12-13 23:03 dwesterg
2018-12-13 23:03 ` [PATCH 2/3] ARM: dts: arria10: " dwesterg
2018-12-13 23:03 ` [PATCH 3/3] ARM64: dts: stratix10: " dwesterg
0 siblings, 2 replies; 8+ messages in thread
From: dwesterg @ 2018-12-13 23:03 UTC (permalink / raw)
To: dinguyen, robh+dt, mark.rutland, devicetree, linux-kernel, thor.thayer
Cc: Dalon Westergreen
From: Dalon Westergreen <dalon.westergreen@linux.intel.com>
Add the ptp_ref clock to gmac0 / gmac1 specifying the default clk
of osc1. The stmmac driver defaults the ptp_ref clock to the main
stmmac clock if ptp_ref is not provided. This is inappropriate for
the Cyclone5 or Arria5 devices.
Signed-off-by: Dalon Westergreen <dalon.westergreen@linux.intel.com>
---
arch/arm/boot/dts/socfpga.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 28ecb4bdf5aa..c1c9d6a2bb91 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -557,8 +557,8 @@
interrupts = <0 115 4>;
interrupt-names = "macirq";
mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
- clocks = <&emac_0_clk>;
- clock-names = "stmmaceth";
+ clocks = <&emac_0_clk>, <&osc1>;
+ clock-names = "stmmaceth", "ptp_ref";
resets = <&rst EMAC0_RESET>;
reset-names = "stmmaceth";
snps,multicast-filter-bins = <256>;
@@ -575,8 +575,8 @@
interrupts = <0 120 4>;
interrupt-names = "macirq";
mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
- clocks = <&emac_1_clk>;
- clock-names = "stmmaceth";
+ clocks = <&emac_1_clk>, <&osc1>;
+ clock-names = "stmmaceth", "ptp_ref";
resets = <&rst EMAC1_RESET>;
reset-names = "stmmaceth";
snps,multicast-filter-bins = <256>;
--
2.19.2
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 2/3] ARM: dts: arria10: Add stmmac ptp_ref clock
2018-12-13 23:03 [PATCH 1/3] ARM: dts: cyclone5: Add stmmac ptp_ref clock dwesterg
@ 2018-12-13 23:03 ` dwesterg
2018-12-13 23:03 ` [PATCH 3/3] ARM64: dts: stratix10: " dwesterg
1 sibling, 0 replies; 8+ messages in thread
From: dwesterg @ 2018-12-13 23:03 UTC (permalink / raw)
To: dinguyen, robh+dt, mark.rutland, devicetree, linux-kernel, thor.thayer
Cc: Dalon Westergreen
From: Dalon Westergreen <dalon.westergreen@linux.intel.com>
Add the default stmmac ptp_ref clock for arria10. The stmmac
driver defaults the ptp_ref clock to the main stmmac clock
if the ptp_ref clock is not set in the devicetree. This is inappropriate
for the arria10 device. The default ptp_ref clock is peri_emac_ptp_clk.
Signed-off-by: Dalon Westergreen <dalon.westergreen@linux.intel.com>
---
arch/arm/boot/dts/socfpga_arria10.dtsi | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index 0017bac7f96c..6591def7b225 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -426,8 +426,8 @@
snps,perfect-filter-entries = <128>;
tx-fifo-depth = <4096>;
rx-fifo-depth = <16384>;
- clocks = <&l4_mp_clk>;
- clock-names = "stmmaceth";
+ clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>;
+ clock-names = "stmmaceth", "ptp_ref";
resets = <&rst EMAC0_RESET>;
reset-names = "stmmaceth";
snps,axi-config = <&socfpga_axi_setup>;
@@ -446,8 +446,8 @@
snps,perfect-filter-entries = <128>;
tx-fifo-depth = <4096>;
rx-fifo-depth = <16384>;
- clocks = <&l4_mp_clk>;
- clock-names = "stmmaceth";
+ clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>;
+ clock-names = "stmmaceth", "ptp_ref";
resets = <&rst EMAC1_RESET>;
reset-names = "stmmaceth";
snps,axi-config = <&socfpga_axi_setup>;
@@ -466,8 +466,8 @@
snps,perfect-filter-entries = <128>;
tx-fifo-depth = <4096>;
rx-fifo-depth = <16384>;
- clocks = <&l4_mp_clk>;
- clock-names = "stmmaceth";
+ clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>;
+ clock-names = "stmmaceth", "ptp_ref";
snps,axi-config = <&socfpga_axi_setup>;
status = "disabled";
};
--
2.19.2
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 3/3] ARM64: dts: stratix10: Add stmmac ptp_ref clock
2018-12-13 23:03 [PATCH 1/3] ARM: dts: cyclone5: Add stmmac ptp_ref clock dwesterg
2018-12-13 23:03 ` [PATCH 2/3] ARM: dts: arria10: " dwesterg
@ 2018-12-13 23:03 ` dwesterg
1 sibling, 0 replies; 8+ messages in thread
From: dwesterg @ 2018-12-13 23:03 UTC (permalink / raw)
To: dinguyen, robh+dt, mark.rutland, devicetree, linux-kernel, thor.thayer
Cc: Dalon Westergreen
From: Dalon Westergreen <dalon.westergreen@linux.intel.com>
Add the default stmmac ptp_ref clock for stratix10. The stmmac
driver defaults the ptp_ref clock to the main stmmac clock
if the ptp_ref clock is not set in the devicetree. This is
inappropriate for the stratix10. The default ptp_ref clock is
STRATIX10_PERI_EMAC_PTP_CLK in the clock manager.
Signed-off-by: Dalon Westergreen <dalon.westergreen@linux.intel.com>
---
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
index adedd563125a..f464e7ba3402 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
@@ -160,8 +160,8 @@
mac-address = [00 00 00 00 00 00];
resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
reset-names = "stmmaceth", "stmmaceth-ocp";
- clocks = <&clkmgr STRATIX10_EMAC0_CLK>;
- clock-names = "stmmaceth";
+ clocks = <&clkmgr STRATIX10_EMAC0_CLK>, <&clkmgr STRATIX10_PERI_EMAC_PTP_CLK>;
+ clock-names = "stmmaceth", "ptp_ref";
tx-fifo-depth = <16384>;
rx-fifo-depth = <16384>;
snps,multicast-filter-bins = <256>;
@@ -176,8 +176,8 @@
mac-address = [00 00 00 00 00 00];
resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
reset-names = "stmmaceth", "stmmaceth-ocp";
- clocks = <&clkmgr STRATIX10_EMAC1_CLK>;
- clock-names = "stmmaceth";
+ clocks = <&clkmgr STRATIX10_EMAC1_CLK>, <&clkmgr STRATIX10_PERI_EMAC_PTP_CLK>;
+ clock-names = "stmmaceth", "ptp_ref";
tx-fifo-depth = <16384>;
rx-fifo-depth = <16384>;
snps,multicast-filter-bins = <256>;
@@ -192,8 +192,8 @@
mac-address = [00 00 00 00 00 00];
resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
reset-names = "stmmaceth", "stmmaceth-ocp";
- clocks = <&clkmgr STRATIX10_EMAC2_CLK>;
- clock-names = "stmmaceth";
+ clocks = <&clkmgr STRATIX10_EMAC2_CLK>, <&clkmgr STRATIX10_PERI_EMAC_PTP_CLK>;
+ clock-names = "stmmaceth", "ptp_ref";
tx-fifo-depth = <16384>;
rx-fifo-depth = <16384>;
snps,multicast-filter-bins = <256>;
--
2.19.2
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 1/3] ARM: dts: cyclone5: Add stmmac ptp_ref clock
@ 2019-05-15 16:20 Dalon Westergreen
2019-05-15 16:20 ` [PATCH 3/3] ARM64: dts: stratix10: " Dalon Westergreen
0 siblings, 1 reply; 8+ messages in thread
From: Dalon Westergreen @ 2019-05-15 16:20 UTC (permalink / raw)
To: dinguyen, thor.thayer, devicetree
Add the ptp_ref clock to gmac0 / gmac1 specifying the default clk
of osc1. The stmmac driver defaults the ptp_ref clock to the main
stmmac clock if ptp_ref is not provided. This is inappropriate for
the Cyclone5 or Arria5 devices.
Signed-off-by: Dalon Westergreen <dalon.westergreen@linux.intel.com>
---
arch/arm/boot/dts/socfpga.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 28ecb4bdf5aa..c1c9d6a2bb91 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -557,8 +557,8 @@
interrupts = <0 115 4>;
interrupt-names = "macirq";
mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
- clocks = <&emac_0_clk>;
- clock-names = "stmmaceth";
+ clocks = <&emac_0_clk>, <&osc1>;
+ clock-names = "stmmaceth", "ptp_ref";
resets = <&rst EMAC0_RESET>;
reset-names = "stmmaceth";
snps,multicast-filter-bins = <256>;
@@ -575,8 +575,8 @@
interrupts = <0 120 4>;
interrupt-names = "macirq";
mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
- clocks = <&emac_1_clk>;
- clock-names = "stmmaceth";
+ clocks = <&emac_1_clk>, <&osc1>;
+ clock-names = "stmmaceth", "ptp_ref";
resets = <&rst EMAC1_RESET>;
reset-names = "stmmaceth";
snps,multicast-filter-bins = <256>;
--
2.19.2
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 3/3] ARM64: dts: stratix10: Add stmmac ptp_ref clock
2019-05-15 16:20 [PATCH 1/3] ARM: dts: cyclone5: " Dalon Westergreen
@ 2019-05-15 16:20 ` Dalon Westergreen
2019-05-20 16:39 ` Thor Thayer
0 siblings, 1 reply; 8+ messages in thread
From: Dalon Westergreen @ 2019-05-15 16:20 UTC (permalink / raw)
To: dinguyen, thor.thayer, devicetree
Add the default stmmac ptp_ref clock for stratix10. The stmmac
driver defaults the ptp_ref clock to the main stmmac clock
if the ptp_ref clock is not set in the devicetree. This is
inappropriate for the stratix10. The default ptp_ref clock is
STRATIX10_PERI_EMAC_PTP_CLK in the clock manager.
Signed-off-by: Dalon Westergreen <dalon.westergreen@linux.intel.com>
---
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
index adedd563125a..f464e7ba3402 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
@@ -160,8 +160,8 @@
mac-address = [00 00 00 00 00 00];
resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
reset-names = "stmmaceth", "stmmaceth-ocp";
- clocks = <&clkmgr STRATIX10_EMAC0_CLK>;
- clock-names = "stmmaceth";
+ clocks = <&clkmgr STRATIX10_EMAC0_CLK>, <&clkmgr STRATIX10_PERI_EMAC_PTP_CLK>;
+ clock-names = "stmmaceth", "ptp_ref";
tx-fifo-depth = <16384>;
rx-fifo-depth = <16384>;
snps,multicast-filter-bins = <256>;
@@ -176,8 +176,8 @@
mac-address = [00 00 00 00 00 00];
resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
reset-names = "stmmaceth", "stmmaceth-ocp";
- clocks = <&clkmgr STRATIX10_EMAC1_CLK>;
- clock-names = "stmmaceth";
+ clocks = <&clkmgr STRATIX10_EMAC1_CLK>, <&clkmgr STRATIX10_PERI_EMAC_PTP_CLK>;
+ clock-names = "stmmaceth", "ptp_ref";
tx-fifo-depth = <16384>;
rx-fifo-depth = <16384>;
snps,multicast-filter-bins = <256>;
@@ -192,8 +192,8 @@
mac-address = [00 00 00 00 00 00];
resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
reset-names = "stmmaceth", "stmmaceth-ocp";
- clocks = <&clkmgr STRATIX10_EMAC2_CLK>;
- clock-names = "stmmaceth";
+ clocks = <&clkmgr STRATIX10_EMAC2_CLK>, <&clkmgr STRATIX10_PERI_EMAC_PTP_CLK>;
+ clock-names = "stmmaceth", "ptp_ref";
tx-fifo-depth = <16384>;
rx-fifo-depth = <16384>;
snps,multicast-filter-bins = <256>;
--
2.19.2
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 3/3] ARM64: dts: stratix10: Add stmmac ptp_ref clock
2019-05-15 16:20 ` [PATCH 3/3] ARM64: dts: stratix10: " Dalon Westergreen
@ 2019-05-20 16:39 ` Thor Thayer
2019-05-21 13:09 ` Dalon L Westergreen
0 siblings, 1 reply; 8+ messages in thread
From: Thor Thayer @ 2019-05-20 16:39 UTC (permalink / raw)
To: Dalon Westergreen, dinguyen, devicetree
On 5/15/19 11:20 AM, Dalon Westergreen wrote:
> Add the default stmmac ptp_ref clock for stratix10. The stmmac
> driver defaults the ptp_ref clock to the main stmmac clock
> if the ptp_ref clock is not set in the devicetree. This is
> inappropriate for the stratix10. The default ptp_ref clock is
> STRATIX10_PERI_EMAC_PTP_CLK in the clock manager.
>
> Signed-off-by: Dalon Westergreen <dalon.westergreen@linux.intel.com>
> ---
> arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 12 ++++++------
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> index adedd563125a..f464e7ba3402 100644
> --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> @@ -160,8 +160,8 @@
> mac-address = [00 00 00 00 00 00];
> resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
> reset-names = "stmmaceth", "stmmaceth-ocp";
> - clocks = <&clkmgr STRATIX10_EMAC0_CLK>;
> - clock-names = "stmmaceth";
> + clocks = <&clkmgr STRATIX10_EMAC0_CLK>, <&clkmgr STRATIX10_PERI_EMAC_PTP_CLK>;
> + clock-names = "stmmaceth", "ptp_ref";
> tx-fifo-depth = <16384>;
> rx-fifo-depth = <16384>;
> snps,multicast-filter-bins = <256>;
> @@ -176,8 +176,8 @@
> mac-address = [00 00 00 00 00 00];
> resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
> reset-names = "stmmaceth", "stmmaceth-ocp";
> - clocks = <&clkmgr STRATIX10_EMAC1_CLK>;
> - clock-names = "stmmaceth";
> + clocks = <&clkmgr STRATIX10_EMAC1_CLK>, <&clkmgr STRATIX10_PERI_EMAC_PTP_CLK>;
> + clock-names = "stmmaceth", "ptp_ref";
> tx-fifo-depth = <16384>;
> rx-fifo-depth = <16384>;
> snps,multicast-filter-bins = <256>;
> @@ -192,8 +192,8 @@
> mac-address = [00 00 00 00 00 00];
> resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
> reset-names = "stmmaceth", "stmmaceth-ocp";
> - clocks = <&clkmgr STRATIX10_EMAC2_CLK>;
> - clock-names = "stmmaceth";
> + clocks = <&clkmgr STRATIX10_EMAC2_CLK>, <&clkmgr STRATIX10_PERI_EMAC_PTP_CLK>;
> + clock-names = "stmmaceth", "ptp_ref";
> tx-fifo-depth = <16384>;
> rx-fifo-depth = <16384>;
> snps,multicast-filter-bins = <256>;
>
Should STRATIX10_EMAC_PTP_CLK be used instead of
STRATIX10_PERI_EMAC_PTP_CLK since this is the gate of the clkgmr?
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 3/3] ARM64: dts: stratix10: Add stmmac ptp_ref clock
2019-05-20 16:39 ` Thor Thayer
@ 2019-05-21 13:09 ` Dalon L Westergreen
2019-05-21 20:27 ` Dinh Nguyen
0 siblings, 1 reply; 8+ messages in thread
From: Dalon L Westergreen @ 2019-05-21 13:09 UTC (permalink / raw)
To: thor.thayer, dinguyen, devicetree
On Mon, 2019-05-20 at 11:39 -0500, Thor Thayer wrote:
> On 5/15/19 11:20 AM, Dalon Westergreen wrote:
> > Add the default stmmac ptp_ref clock for stratix10. The stmmac
> > driver defaults the ptp_ref clock to the main stmmac clock
> > if the ptp_ref clock is not set in the devicetree. This is
> > inappropriate for the stratix10. The default ptp_ref clock is
> > STRATIX10_PERI_EMAC_PTP_CLK in the clock manager.
> >
> > Signed-off-by: Dalon Westergreen <
> > dalon.westergreen@linux.intel.com
> > >
> > ---
> > arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 12 ++++++------
> > 1 file changed, 6 insertions(+), 6 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> > b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> > index adedd563125a..f464e7ba3402 100644
> > --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> > +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> > @@ -160,8 +160,8 @@
> > mac-address = [00 00 00 00 00 00];
> > resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
> > reset-names = "stmmaceth", "stmmaceth-ocp";
> > - clocks = <&clkmgr STRATIX10_EMAC0_CLK>;
> > - clock-names = "stmmaceth";
> > + clocks = <&clkmgr STRATIX10_EMAC0_CLK>, <&clkmgr
> > STRATIX10_PERI_EMAC_PTP_CLK>;
> > + clock-names = "stmmaceth", "ptp_ref";
> > tx-fifo-depth = <16384>;
> > rx-fifo-depth = <16384>;
> > snps,multicast-filter-bins = <256>;
> > @@ -176,8 +176,8 @@
> > mac-address = [00 00 00 00 00 00];
> > resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
> > reset-names = "stmmaceth", "stmmaceth-ocp";
> > - clocks = <&clkmgr STRATIX10_EMAC1_CLK>;
> > - clock-names = "stmmaceth";
> > + clocks = <&clkmgr STRATIX10_EMAC1_CLK>, <&clkmgr
> > STRATIX10_PERI_EMAC_PTP_CLK>;
> > + clock-names = "stmmaceth", "ptp_ref";
> > tx-fifo-depth = <16384>;
> > rx-fifo-depth = <16384>;
> > snps,multicast-filter-bins = <256>;
> > @@ -192,8 +192,8 @@
> > mac-address = [00 00 00 00 00 00];
> > resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
> > reset-names = "stmmaceth", "stmmaceth-ocp";
> > - clocks = <&clkmgr STRATIX10_EMAC2_CLK>;
> > - clock-names = "stmmaceth";
> > + clocks = <&clkmgr STRATIX10_EMAC2_CLK>, <&clkmgr
> > STRATIX10_PERI_EMAC_PTP_CLK>;
> > + clock-names = "stmmaceth", "ptp_ref";
> > tx-fifo-depth = <16384>;
> > rx-fifo-depth = <16384>;
> > snps,multicast-filter-bins = <256>;
> >
>
> Should STRATIX10_EMAC_PTP_CLK be used instead of
> STRATIX10_PERI_EMAC_PTP_CLK since this is the gate of the clkgmr?
>
Either can be used, but the default in the hps configuration is the
peripheral pll output and not the main pll output.
--dalon
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 3/3] ARM64: dts: stratix10: Add stmmac ptp_ref clock
2019-05-21 13:09 ` Dalon L Westergreen
@ 2019-05-21 20:27 ` Dinh Nguyen
2019-05-22 14:47 ` Dalon L Westergreen
0 siblings, 1 reply; 8+ messages in thread
From: Dinh Nguyen @ 2019-05-21 20:27 UTC (permalink / raw)
To: dalon.westergreen, thor.thayer, devicetree
On 5/21/19 8:09 AM, Dalon L Westergreen wrote:
> On Mon, 2019-05-20 at 11:39 -0500, Thor Thayer wrote:
>> On 5/15/19 11:20 AM, Dalon Westergreen wrote:
>>> Add the default stmmac ptp_ref clock for stratix10. The stmmac
>>> driver defaults the ptp_ref clock to the main stmmac clock
>>> if the ptp_ref clock is not set in the devicetree. This is
>>> inappropriate for the stratix10. The default ptp_ref clock is
>>> STRATIX10_PERI_EMAC_PTP_CLK in the clock manager.
>>>
>>> Signed-off-by: Dalon Westergreen <
>>> dalon.westergreen@linux.intel.com
>>>>
>>> ---
>>> arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 12 ++++++------
>>> 1 file changed, 6 insertions(+), 6 deletions(-)
>>>
>>> diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
>>> b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
>>> index adedd563125a..f464e7ba3402 100644
>>> --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
>>> +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
>>> @@ -160,8 +160,8 @@
>>> mac-address = [00 00 00 00 00 00];
>>> resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
>>> reset-names = "stmmaceth", "stmmaceth-ocp";
>>> - clocks = <&clkmgr STRATIX10_EMAC0_CLK>;
>>> - clock-names = "stmmaceth";
>>> + clocks = <&clkmgr STRATIX10_EMAC0_CLK>, <&clkmgr
>>> STRATIX10_PERI_EMAC_PTP_CLK>;
>>> + clock-names = "stmmaceth", "ptp_ref";
>>> tx-fifo-depth = <16384>;
>>> rx-fifo-depth = <16384>;
>>> snps,multicast-filter-bins = <256>;
>>> @@ -176,8 +176,8 @@
>>> mac-address = [00 00 00 00 00 00];
>>> resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
>>> reset-names = "stmmaceth", "stmmaceth-ocp";
>>> - clocks = <&clkmgr STRATIX10_EMAC1_CLK>;
>>> - clock-names = "stmmaceth";
>>> + clocks = <&clkmgr STRATIX10_EMAC1_CLK>, <&clkmgr
>>> STRATIX10_PERI_EMAC_PTP_CLK>;
>>> + clock-names = "stmmaceth", "ptp_ref";
>>> tx-fifo-depth = <16384>;
>>> rx-fifo-depth = <16384>;
>>> snps,multicast-filter-bins = <256>;
>>> @@ -192,8 +192,8 @@
>>> mac-address = [00 00 00 00 00 00];
>>> resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
>>> reset-names = "stmmaceth", "stmmaceth-ocp";
>>> - clocks = <&clkmgr STRATIX10_EMAC2_CLK>;
>>> - clock-names = "stmmaceth";
>>> + clocks = <&clkmgr STRATIX10_EMAC2_CLK>, <&clkmgr
>>> STRATIX10_PERI_EMAC_PTP_CLK>;
>>> + clock-names = "stmmaceth", "ptp_ref";
>>> tx-fifo-depth = <16384>;
>>> rx-fifo-depth = <16384>;
>>> snps,multicast-filter-bins = <256>;
>>>
>>
>> Should STRATIX10_EMAC_PTP_CLK be used instead of
>> STRATIX10_PERI_EMAC_PTP_CLK since this is the gate of the clkgmr?
>>
>
> Either can be used, but the default in the hps configuration is the
> peripheral pll output and not the main pll output.
>
I think it should be the emac_ptp_clk. If you look at the clock tree,
the emac_ptp_clk(50 MHz) and is derived from the peri_emac_ptp_clk(200
MHz).
You can look at the clock tree by doing a 'cat
/sys/kernel/debug/clk/clk_summary'.
Dinh
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 3/3] ARM64: dts: stratix10: Add stmmac ptp_ref clock
2019-05-21 20:27 ` Dinh Nguyen
@ 2019-05-22 14:47 ` Dalon L Westergreen
0 siblings, 0 replies; 8+ messages in thread
From: Dalon L Westergreen @ 2019-05-22 14:47 UTC (permalink / raw)
To: Dinh Nguyen, thor.thayer, devicetree
On Tue, 2019-05-21 at 15:27 -0500, Dinh Nguyen wrote:
>
> On 5/21/19 8:09 AM, Dalon L Westergreen wrote:
> > On Mon, 2019-05-20 at 11:39 -0500, Thor Thayer wrote:
> > > On 5/15/19 11:20 AM, Dalon Westergreen wrote:
> > > > Add the default stmmac ptp_ref clock for stratix10. The stmmac
> > > > driver defaults the ptp_ref clock to the main stmmac clock
> > > > if the ptp_ref clock is not set in the devicetree. This is
> > > > inappropriate for the stratix10. The default ptp_ref clock is
> > > > STRATIX10_PERI_EMAC_PTP_CLK in the clock manager.
> > > >
> > > > Signed-off-by: Dalon Westergreen <
> > > > dalon.westergreen@linux.intel.com
> > > >
> > > >
> > > > ---
> > > > arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 12 ++++++------
> > > > 1 file changed, 6 insertions(+), 6 deletions(-)
> > > >
> > > > diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> > > > b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> > > > index adedd563125a..f464e7ba3402 100644
> > > > --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> > > > +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> > > > @@ -160,8 +160,8 @@
> > > > mac-address = [00 00 00 00 00 00];
> > > > resets = <&rst EMAC0_RESET>, <&rst
> > > > EMAC0_OCP_RESET>;
> > > > reset-names = "stmmaceth", "stmmaceth-ocp";
> > > > - clocks = <&clkmgr STRATIX10_EMAC0_CLK>;
> > > > - clock-names = "stmmaceth";
> > > > + clocks = <&clkmgr STRATIX10_EMAC0_CLK>, <&clkmgr
> > > > STRATIX10_PERI_EMAC_PTP_CLK>;
> > > > + clock-names = "stmmaceth", "ptp_ref";
> > > > tx-fifo-depth = <16384>;
> > > > rx-fifo-depth = <16384>;
> > > > snps,multicast-filter-bins = <256>;
> > > > @@ -176,8 +176,8 @@
> > > > mac-address = [00 00 00 00 00 00];
> > > > resets = <&rst EMAC1_RESET>, <&rst
> > > > EMAC1_OCP_RESET>;
> > > > reset-names = "stmmaceth", "stmmaceth-ocp";
> > > > - clocks = <&clkmgr STRATIX10_EMAC1_CLK>;
> > > > - clock-names = "stmmaceth";
> > > > + clocks = <&clkmgr STRATIX10_EMAC1_CLK>, <&clkmgr
> > > > STRATIX10_PERI_EMAC_PTP_CLK>;
> > > > + clock-names = "stmmaceth", "ptp_ref";
> > > > tx-fifo-depth = <16384>;
> > > > rx-fifo-depth = <16384>;
> > > > snps,multicast-filter-bins = <256>;
> > > > @@ -192,8 +192,8 @@
> > > > mac-address = [00 00 00 00 00 00];
> > > > resets = <&rst EMAC2_RESET>, <&rst
> > > > EMAC2_OCP_RESET>;
> > > > reset-names = "stmmaceth", "stmmaceth-ocp";
> > > > - clocks = <&clkmgr STRATIX10_EMAC2_CLK>;
> > > > - clock-names = "stmmaceth";
> > > > + clocks = <&clkmgr STRATIX10_EMAC2_CLK>, <&clkmgr
> > > > STRATIX10_PERI_EMAC_PTP_CLK>;
> > > > + clock-names = "stmmaceth", "ptp_ref";
> > > > tx-fifo-depth = <16384>;
> > > > rx-fifo-depth = <16384>;
> > > > snps,multicast-filter-bins = <256>;
> > > >
> > >
> > > Should STRATIX10_EMAC_PTP_CLK be used instead of
> > > STRATIX10_PERI_EMAC_PTP_CLK since this is the gate of the clkgmr?
> > >
> >
> > Either can be used, but the default in the hps configuration is the
> > peripheral pll output and not the main pll output.
> >
>
> I think it should be the emac_ptp_clk. If you look at the clock tree,
> the emac_ptp_clk(50 MHz) and is derived from the peri_emac_ptp_clk(200
> MHz).
>
> You can look at the clock tree by doing a 'cat
> /sys/kernel/debug/clk/clk_summary'.
>
> Dinh
>
I dont disagree, but this devicetree is a representation of what was implemented
in the devkit no? Should we first request that this is changed in the design?
or should i set this to STRATIX10_EMAC_PTP_CLK and overide it in the top level
socdk devicetree?
dalon
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2019-05-22 14:47 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-12-13 23:03 [PATCH 1/3] ARM: dts: cyclone5: Add stmmac ptp_ref clock dwesterg
2018-12-13 23:03 ` [PATCH 2/3] ARM: dts: arria10: " dwesterg
2018-12-13 23:03 ` [PATCH 3/3] ARM64: dts: stratix10: " dwesterg
2019-05-15 16:20 [PATCH 1/3] ARM: dts: cyclone5: " Dalon Westergreen
2019-05-15 16:20 ` [PATCH 3/3] ARM64: dts: stratix10: " Dalon Westergreen
2019-05-20 16:39 ` Thor Thayer
2019-05-21 13:09 ` Dalon L Westergreen
2019-05-21 20:27 ` Dinh Nguyen
2019-05-22 14:47 ` Dalon L Westergreen
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