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* [v3 1/2] drm/i915/icl: Ungate ddi clocks before IO enable
@ 2019-03-25 11:26 Vandita Kulkarni
  2019-03-25 11:26 ` [v3 2/2] drm/i915/icl: Fix port disable sequence for mipi-dsi Vandita Kulkarni
                   ` (6 more replies)
  0 siblings, 7 replies; 9+ messages in thread
From: Vandita Kulkarni @ 2019-03-25 11:26 UTC (permalink / raw)
  To: intel-gfx; +Cc: ville.syrjala, jani.nikula

IO enable sequencing needs ddi clocks enabled.
These clocks will be gated at a later point in
the enable sequence.

v2: Fix the commit header (Uma)
v3: Remove the redundant read (Ville)

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/icl_dsi.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 92440ff..4aef5dd 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -589,6 +589,12 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder,
 		val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
 	}
 	I915_WRITE(DPCLKA_CFGCR0_ICL, val);
+
+	for_each_dsi_port(port, intel_dsi->ports) {
+		val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
+	}
+	I915_WRITE(DPCLKA_CFGCR0_ICL, val);
+
 	POSTING_READ(DPCLKA_CFGCR0_ICL);
 
 	mutex_unlock(&dev_priv->dpll_lock);
-- 
1.9.1

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^ permalink raw reply related	[flat|nested] 9+ messages in thread

end of thread, other threads:[~2019-04-03  6:52 UTC | newest]

Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-03-25 11:26 [v3 1/2] drm/i915/icl: Ungate ddi clocks before IO enable Vandita Kulkarni
2019-03-25 11:26 ` [v3 2/2] drm/i915/icl: Fix port disable sequence for mipi-dsi Vandita Kulkarni
2019-03-26  6:07   ` Shankar, Uma
2019-03-25 12:33 ` ✗ Fi.CI.BAT: failure for series starting with [v3,1/2] drm/i915/icl: Ungate ddi clocks before IO enable Patchwork
2019-03-27 15:04 ` [v3 1/2] " Jani Nikula
2019-03-27 19:36 ` ✓ Fi.CI.BAT: success for series starting with [v3,1/2] drm/i915/icl: Ungate ddi clocks before IO enable (rev2) Patchwork
2019-03-28 15:04 ` ✗ Fi.CI.IGT: failure " Patchwork
2019-04-02 18:48 ` ✓ Fi.CI.BAT: success for series starting with [v3,1/2] drm/i915/icl: Ungate ddi clocks before IO enable (rev3) Patchwork
2019-04-03  6:52 ` ✓ Fi.CI.IGT: " Patchwork

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