From: Lucas De Marchi <lucas.demarchi@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Subject: [PATCH 00/28] Initial support for Tiger Lake
Date: Tue, 25 Jun 2019 10:54:09 -0700 [thread overview]
Message-ID: <20190625175437.14840-1-lucas.demarchi@intel.com> (raw)
Basic pumbling to add Tiger Lake platform to i915, support for the 4th
pipe, additional combo phy, power well definitions, clock changes, DDI
changes and registers moving around.
More to come soon.
Anusha Srivatsa (1):
drm/i915: Add modular FIA
Daniele Ceraolo Spurio (1):
drm/i915/tgl: add initial Tiger Lake definitions
Imre Deak (1):
drm/i915/tgl: Add power well support
José Roberto de Souza (3):
drm/i915/tgl: Check if pipe D is fused
drm/i915/tgl: Add TRANSCODER_A_VDSC power domain
drm/i915/tgl: Update DPLL clock reference register
Lucas De Marchi (6):
drm/i915: rework reading pipe disable fuses
drm/i915: Add 4th pipe and transcoder
drm/i915/tgl: Add TGL PCI IDs
drm/i915/tgl: apply Display WA #1178 to fix type C dongles
drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization
drm/i915/tgl: Add DPLL registers
Mahesh Kumar (9):
drm/i915/tgl: Add TGL PCH detection in virtualized environment
drm/i915/tgl: update ddi/tc clock_off bits
drm/i915/tgl: Add gmbus gpio pin to port mapping
drm/i915/tgl: port to ddc pin mapping
drm/i915/tgl: select correct bit for port select
drm/i915/tgl: Add third combophy offset
drm/i915/tgl: extend intel_port_is_combophy/tc
drm/i915/tgl: init ddi port A-C for Tiger Lake
drm/i915/tgl: Add vbt value mapping for DDC Bus pin
Michel Thierry (1):
x86/gpu: add TGL stolen memory support
Mika Kahola (1):
drm/i915/tgl: Add power well to support 4th pipe
Radhakrishna Sripada (1):
drm/i915/tgl: Introduce Tiger Lake PCH
Rodrigo Vivi (1):
drm/i915/gen12: MBUS B credit change
Vandita Kulkarni (3):
drm/i915/tgl: Add new pll ids
drm/i915/tgl: Add pll manager
drm/i915/tgl: Add additional ports for Tiger Lake
arch/x86/kernel/early-quirks.c | 1 +
drivers/gpu/drm/i915/display/intel_bios.c | 17 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 69 ++-
drivers/gpu/drm/i915/display/intel_display.c | 64 ++-
drivers/gpu/drm/i915/display/intel_display.h | 14 +
.../drm/i915/display/intel_display_power.c | 522 +++++++++++++++++-
.../drm/i915/display/intel_display_power.h | 30 +-
drivers/gpu/drm/i915/display/intel_dp.c | 25 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 50 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 23 +-
drivers/gpu/drm/i915/display/intel_gmbus.c | 20 +-
drivers/gpu/drm/i915/display/intel_hdmi.c | 16 +-
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 3 +
drivers/gpu/drm/i915/display/intel_vdsc.c | 11 +-
drivers/gpu/drm/i915/i915_debugfs.c | 3 +-
drivers/gpu/drm/i915/i915_drv.c | 8 +-
drivers/gpu/drm/i915/i915_drv.h | 4 +
drivers/gpu/drm/i915/i915_pci.c | 31 ++
drivers/gpu/drm/i915/i915_reg.h | 81 ++-
drivers/gpu/drm/i915/intel_device_info.c | 40 +-
drivers/gpu/drm/i915/intel_device_info.h | 3 +
drivers/gpu/drm/i915/intel_drv.h | 2 +
include/drm/i915_component.h | 2 +-
include/drm/i915_drm.h | 3 +
include/drm/i915_pciids.h | 10 +
25 files changed, 940 insertions(+), 112 deletions(-)
--
2.21.0
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next reply other threads:[~2019-06-25 17:54 UTC|newest]
Thread overview: 61+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-25 17:54 Lucas De Marchi [this message]
2019-06-25 17:54 ` [PATCH 01/28] drm/i915: Add modular FIA Lucas De Marchi
2019-06-26 15:50 ` Ville Syrjälä
2019-06-26 17:48 ` Lucas De Marchi
2019-06-26 17:56 ` Ville Syrjälä
2019-06-25 17:54 ` [PATCH 02/28] drm/i915: rework reading pipe disable fuses Lucas De Marchi
2019-06-26 15:51 ` Ville Syrjälä
2019-06-25 17:54 ` [PATCH 03/28] drm/i915: Add 4th pipe and transcoder Lucas De Marchi
2019-07-08 13:00 ` Ville Syrjälä
2019-06-25 17:54 ` [PATCH 04/28] drm/i915/tgl: add initial Tiger Lake definitions Lucas De Marchi
2019-06-26 17:40 ` Srivatsa, Anusha
2019-06-25 17:54 ` [PATCH 05/28] drm/i915/tgl: Introduce Tiger Lake PCH Lucas De Marchi
2019-07-07 10:49 ` Gupta, Anshuman
2019-07-08 10:59 ` Gupta, Anshuman
2019-06-25 17:54 ` [PATCH 06/28] drm/i915/tgl: Add TGL PCH detection in virtualized environment Lucas De Marchi
2019-06-26 18:27 ` Srivatsa, Anusha
2019-06-25 17:54 ` [PATCH 07/28] drm/i915/tgl: Add TGL PCI IDs Lucas De Marchi
2019-07-08 10:55 ` Gupta, Anshuman
2019-07-08 13:31 ` Lucas De Marchi
2019-06-25 17:54 ` [PATCH 08/28] x86/gpu: add TGL stolen memory support Lucas De Marchi
2019-07-09 12:03 ` Rodrigo Vivi
2019-06-25 17:54 ` [PATCH 09/28] drm/i915/tgl: Check if pipe D is fused Lucas De Marchi
2019-06-26 21:24 ` Srivatsa, Anusha
2019-06-25 17:54 ` [PATCH 10/28] drm/i915/tgl: Add power well support Lucas De Marchi
2019-06-27 19:15 ` Manasi Navare
2019-06-27 20:23 ` Lucas De Marchi
2019-06-27 19:31 ` Souza, Jose
2019-06-27 20:22 ` Lucas De Marchi
2019-06-25 17:54 ` [PATCH 11/28] drm/i915/tgl: Add power well to support 4th pipe Lucas De Marchi
2019-07-01 17:54 ` Ville Syrjälä
2019-06-25 17:54 ` [PATCH 12/28] drm/i915/tgl: Add TRANSCODER_A_VDSC power domain Lucas De Marchi
2019-06-27 19:16 ` Manasi Navare
2019-06-27 19:28 ` Souza, Jose
2019-06-27 19:30 ` Souza, Jose
2019-06-27 19:33 ` Manasi Navare
2019-06-28 9:55 ` Ville Syrjälä
2019-06-28 16:31 ` Lucas De Marchi
2019-07-01 17:32 ` Ville Syrjälä
2019-07-01 17:36 ` Ville Syrjälä
2019-07-08 21:05 ` Lucas De Marchi
2019-06-25 17:54 ` [PATCH 13/28] drm/i915/tgl: Add new pll ids Lucas De Marchi
2019-06-26 23:12 ` Srivatsa, Anusha
2019-06-25 17:54 ` [PATCH 14/28] drm/i915/tgl: Add pll manager Lucas De Marchi
2019-06-25 17:54 ` [PATCH 15/28] drm/i915/tgl: Add additional ports for Tiger Lake Lucas De Marchi
2019-06-25 17:54 ` [PATCH 16/28] drm/i915/tgl: update ddi/tc clock_off bits Lucas De Marchi
2019-06-25 17:54 ` [PATCH 17/28] drm/i915/tgl: Add gmbus gpio pin to port mapping Lucas De Marchi
2019-06-25 17:54 ` [PATCH 18/28] drm/i915/tgl: port to ddc pin mapping Lucas De Marchi
2019-06-25 17:54 ` [PATCH 19/28] drm/i915/tgl: select correct bit for port select Lucas De Marchi
2019-06-25 17:54 ` [PATCH 20/28] drm/i915/tgl: Add third combophy offset Lucas De Marchi
2019-06-25 17:54 ` [PATCH 21/28] drm/i915/tgl: extend intel_port_is_combophy/tc Lucas De Marchi
2019-06-25 17:54 ` [PATCH 22/28] drm/i915/tgl: init ddi port A-C for Tiger Lake Lucas De Marchi
2019-06-25 17:54 ` [PATCH 23/28] drm/i915/tgl: Add vbt value mapping for DDC Bus pin Lucas De Marchi
2019-06-25 17:54 ` [PATCH 24/28] drm/i915/tgl: apply Display WA #1178 to fix type C dongles Lucas De Marchi
2019-06-25 17:54 ` [PATCH 25/28] drm/i915/gen12: MBUS B credit change Lucas De Marchi
2019-06-25 17:54 ` [PATCH 26/28] drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization Lucas De Marchi
2019-06-25 17:54 ` [PATCH 27/28] drm/i915/tgl: Add DPLL registers Lucas De Marchi
2019-06-25 17:54 ` [PATCH 28/28] drm/i915/tgl: Update DPLL clock reference register Lucas De Marchi
2019-06-26 0:00 ` ✗ Fi.CI.CHECKPATCH: warning for Initial support for Tiger Lake Patchwork
2019-06-26 0:54 ` ✓ Fi.CI.BAT: success " Patchwork
2019-06-26 1:43 ` [PATCH 00/28] " Souza, Jose
2019-06-26 5:10 ` ✓ Fi.CI.IGT: success for " Patchwork
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