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From: Lucas De Marchi <lucas.demarchi@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Mahesh Kumar <mahesh1.kumar@intel.com>,
	Lucas De Marchi <lucas.demarchi@intel.com>
Subject: [PATCH 21/28] drm/i915/tgl: extend intel_port_is_combophy/tc
Date: Tue, 25 Jun 2019 10:54:30 -0700	[thread overview]
Message-ID: <20190625175437.14840-22-lucas.demarchi@intel.com> (raw)
In-Reply-To: <20190625175437.14840-1-lucas.demarchi@intel.com>

From: Mahesh Kumar <mahesh1.kumar@intel.com>

TGL has 3 combophy ports, so extend check for tigerlake in
intel_port_is_combophy/tc function.

Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 4d5832a3bf45..72bd85e98b8d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6565,10 +6565,10 @@ bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port)
 	if (port == PORT_NONE)
 		return false;
 
-	if (IS_ELKHARTLAKE(dev_priv))
+	if (IS_ELKHARTLAKE(dev_priv) || INTEL_GEN(dev_priv) >= 12)
 		return port <= PORT_C;
 
-	if (INTEL_GEN(dev_priv) >= 11)
+	if (IS_GEN(dev_priv, 11))
 		return port <= PORT_B;
 
 	return false;
@@ -6576,7 +6576,10 @@ bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port)
 
 bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port)
 {
-	if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
+	if (INTEL_GEN(dev_priv) >= 12)
+		return port >= PORT_D && port <= PORT_I;
+
+	if (IS_GEN(dev_priv, 11) && !IS_ELKHARTLAKE(dev_priv))
 		return port >= PORT_C && port <= PORT_F;
 
 	return false;
@@ -6587,6 +6590,9 @@ enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
 	if (!intel_port_is_tc(dev_priv, port))
 		return PORT_TC_NONE;
 
+	if (INTEL_GEN(dev_priv) >= 12)
+		return port - PORT_D;
+
 	return port - PORT_C;
 }
 
-- 
2.21.0

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  parent reply	other threads:[~2019-06-25 17:55 UTC|newest]

Thread overview: 61+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-06-25 17:54 [PATCH 00/28] Initial support for Tiger Lake Lucas De Marchi
2019-06-25 17:54 ` [PATCH 01/28] drm/i915: Add modular FIA Lucas De Marchi
2019-06-26 15:50   ` Ville Syrjälä
2019-06-26 17:48     ` Lucas De Marchi
2019-06-26 17:56       ` Ville Syrjälä
2019-06-25 17:54 ` [PATCH 02/28] drm/i915: rework reading pipe disable fuses Lucas De Marchi
2019-06-26 15:51   ` Ville Syrjälä
2019-06-25 17:54 ` [PATCH 03/28] drm/i915: Add 4th pipe and transcoder Lucas De Marchi
2019-07-08 13:00   ` Ville Syrjälä
2019-06-25 17:54 ` [PATCH 04/28] drm/i915/tgl: add initial Tiger Lake definitions Lucas De Marchi
2019-06-26 17:40   ` Srivatsa, Anusha
2019-06-25 17:54 ` [PATCH 05/28] drm/i915/tgl: Introduce Tiger Lake PCH Lucas De Marchi
2019-07-07 10:49   ` Gupta, Anshuman
2019-07-08 10:59     ` Gupta, Anshuman
2019-06-25 17:54 ` [PATCH 06/28] drm/i915/tgl: Add TGL PCH detection in virtualized environment Lucas De Marchi
2019-06-26 18:27   ` Srivatsa, Anusha
2019-06-25 17:54 ` [PATCH 07/28] drm/i915/tgl: Add TGL PCI IDs Lucas De Marchi
2019-07-08 10:55   ` Gupta, Anshuman
2019-07-08 13:31     ` Lucas De Marchi
2019-06-25 17:54 ` [PATCH 08/28] x86/gpu: add TGL stolen memory support Lucas De Marchi
2019-07-09 12:03   ` Rodrigo Vivi
2019-06-25 17:54 ` [PATCH 09/28] drm/i915/tgl: Check if pipe D is fused Lucas De Marchi
2019-06-26 21:24   ` Srivatsa, Anusha
2019-06-25 17:54 ` [PATCH 10/28] drm/i915/tgl: Add power well support Lucas De Marchi
2019-06-27 19:15   ` Manasi Navare
2019-06-27 20:23     ` Lucas De Marchi
2019-06-27 19:31   ` Souza, Jose
2019-06-27 20:22     ` Lucas De Marchi
2019-06-25 17:54 ` [PATCH 11/28] drm/i915/tgl: Add power well to support 4th pipe Lucas De Marchi
2019-07-01 17:54   ` Ville Syrjälä
2019-06-25 17:54 ` [PATCH 12/28] drm/i915/tgl: Add TRANSCODER_A_VDSC power domain Lucas De Marchi
2019-06-27 19:16   ` Manasi Navare
2019-06-27 19:28   ` Souza, Jose
2019-06-27 19:30     ` Souza, Jose
2019-06-27 19:33     ` Manasi Navare
2019-06-28  9:55   ` Ville Syrjälä
2019-06-28 16:31     ` Lucas De Marchi
2019-07-01 17:32       ` Ville Syrjälä
2019-07-01 17:36         ` Ville Syrjälä
2019-07-08 21:05         ` Lucas De Marchi
2019-06-25 17:54 ` [PATCH 13/28] drm/i915/tgl: Add new pll ids Lucas De Marchi
2019-06-26 23:12   ` Srivatsa, Anusha
2019-06-25 17:54 ` [PATCH 14/28] drm/i915/tgl: Add pll manager Lucas De Marchi
2019-06-25 17:54 ` [PATCH 15/28] drm/i915/tgl: Add additional ports for Tiger Lake Lucas De Marchi
2019-06-25 17:54 ` [PATCH 16/28] drm/i915/tgl: update ddi/tc clock_off bits Lucas De Marchi
2019-06-25 17:54 ` [PATCH 17/28] drm/i915/tgl: Add gmbus gpio pin to port mapping Lucas De Marchi
2019-06-25 17:54 ` [PATCH 18/28] drm/i915/tgl: port to ddc pin mapping Lucas De Marchi
2019-06-25 17:54 ` [PATCH 19/28] drm/i915/tgl: select correct bit for port select Lucas De Marchi
2019-06-25 17:54 ` [PATCH 20/28] drm/i915/tgl: Add third combophy offset Lucas De Marchi
2019-06-25 17:54 ` Lucas De Marchi [this message]
2019-06-25 17:54 ` [PATCH 22/28] drm/i915/tgl: init ddi port A-C for Tiger Lake Lucas De Marchi
2019-06-25 17:54 ` [PATCH 23/28] drm/i915/tgl: Add vbt value mapping for DDC Bus pin Lucas De Marchi
2019-06-25 17:54 ` [PATCH 24/28] drm/i915/tgl: apply Display WA #1178 to fix type C dongles Lucas De Marchi
2019-06-25 17:54 ` [PATCH 25/28] drm/i915/gen12: MBUS B credit change Lucas De Marchi
2019-06-25 17:54 ` [PATCH 26/28] drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization Lucas De Marchi
2019-06-25 17:54 ` [PATCH 27/28] drm/i915/tgl: Add DPLL registers Lucas De Marchi
2019-06-25 17:54 ` [PATCH 28/28] drm/i915/tgl: Update DPLL clock reference register Lucas De Marchi
2019-06-26  0:00 ` ✗ Fi.CI.CHECKPATCH: warning for Initial support for Tiger Lake Patchwork
2019-06-26  0:54 ` ✓ Fi.CI.BAT: success " Patchwork
2019-06-26  1:43 ` [PATCH 00/28] " Souza, Jose
2019-06-26  5:10 ` ✓ Fi.CI.IGT: success for " Patchwork

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