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From: Lucas De Marchi <lucas.demarchi@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Mahesh Kumar <mahesh1.kumar@intel.com>,
	Lucas De Marchi <lucas.demarchi@intel.com>
Subject: [PATCH 23/28] drm/i915/tgl: Add vbt value mapping for DDC Bus pin
Date: Tue, 25 Jun 2019 10:54:32 -0700	[thread overview]
Message-ID: <20190625175437.14840-24-lucas.demarchi@intel.com> (raw)
In-Reply-To: <20190625175437.14840-1-lucas.demarchi@intel.com>

From: Mahesh Kumar <mahesh1.kumar@intel.com>

Add VBT-value to DDC bus pin mapping for the same.

Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bios.c     | 17 ++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_vbt_defs.h |  3 +++
 2 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 0c9808132d67..a08bc4f617c8 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1354,12 +1354,27 @@ static const u8 mcc_ddc_pin_map[] = {
 	[MCC_DDC_BUS_DDI_C] = GMBUS_PIN_9_TC1_ICP,
 };
 
+static const u8 tgp_ddc_pin_map[] = {
+	[ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT,
+	[ICL_DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT,
+	[TGL_DDC_BUS_DDI_C] = GMBUS_PIN_3_BXT,
+	[ICL_DDC_BUS_PORT_1] = GMBUS_PIN_9_TC1_ICP,
+	[ICL_DDC_BUS_PORT_2] = GMBUS_PIN_10_TC2_ICP,
+	[ICL_DDC_BUS_PORT_3] = GMBUS_PIN_11_TC3_ICP,
+	[ICL_DDC_BUS_PORT_4] = GMBUS_PIN_12_TC4_ICP,
+	[TGL_DDC_BUS_PORT_5] = GMBUS_PIN_13_TC5_TGP,
+	[TGL_DDC_BUS_PORT_6] = GMBUS_PIN_14_TC6_TGP,
+};
+
 static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
 {
 	const u8 *ddc_pin_map;
 	int n_entries;
 
-	if (HAS_PCH_MCC(dev_priv)) {
+	if (HAS_PCH_TGP(dev_priv)) {
+		ddc_pin_map = tgp_ddc_pin_map;
+		n_entries = ARRAY_SIZE(tgp_ddc_pin_map);
+	} else if (HAS_PCH_MCC(dev_priv)) {
 		ddc_pin_map = mcc_ddc_pin_map;
 		n_entries = ARRAY_SIZE(mcc_ddc_pin_map);
 	} else if (HAS_PCH_ICP(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 2f4894e9a03d..93f5c9d204d6 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -310,10 +310,13 @@ enum vbt_gmbus_ddi {
 	DDC_BUS_DDI_F,
 	ICL_DDC_BUS_DDI_A = 0x1,
 	ICL_DDC_BUS_DDI_B,
+	TGL_DDC_BUS_DDI_C,
 	ICL_DDC_BUS_PORT_1 = 0x4,
 	ICL_DDC_BUS_PORT_2,
 	ICL_DDC_BUS_PORT_3,
 	ICL_DDC_BUS_PORT_4,
+	TGL_DDC_BUS_PORT_5,
+	TGL_DDC_BUS_PORT_6,
 	MCC_DDC_BUS_DDI_A = 0x1,
 	MCC_DDC_BUS_DDI_B,
 	MCC_DDC_BUS_DDI_C = 0x4,
-- 
2.21.0

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  parent reply	other threads:[~2019-06-25 17:55 UTC|newest]

Thread overview: 61+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-06-25 17:54 [PATCH 00/28] Initial support for Tiger Lake Lucas De Marchi
2019-06-25 17:54 ` [PATCH 01/28] drm/i915: Add modular FIA Lucas De Marchi
2019-06-26 15:50   ` Ville Syrjälä
2019-06-26 17:48     ` Lucas De Marchi
2019-06-26 17:56       ` Ville Syrjälä
2019-06-25 17:54 ` [PATCH 02/28] drm/i915: rework reading pipe disable fuses Lucas De Marchi
2019-06-26 15:51   ` Ville Syrjälä
2019-06-25 17:54 ` [PATCH 03/28] drm/i915: Add 4th pipe and transcoder Lucas De Marchi
2019-07-08 13:00   ` Ville Syrjälä
2019-06-25 17:54 ` [PATCH 04/28] drm/i915/tgl: add initial Tiger Lake definitions Lucas De Marchi
2019-06-26 17:40   ` Srivatsa, Anusha
2019-06-25 17:54 ` [PATCH 05/28] drm/i915/tgl: Introduce Tiger Lake PCH Lucas De Marchi
2019-07-07 10:49   ` Gupta, Anshuman
2019-07-08 10:59     ` Gupta, Anshuman
2019-06-25 17:54 ` [PATCH 06/28] drm/i915/tgl: Add TGL PCH detection in virtualized environment Lucas De Marchi
2019-06-26 18:27   ` Srivatsa, Anusha
2019-06-25 17:54 ` [PATCH 07/28] drm/i915/tgl: Add TGL PCI IDs Lucas De Marchi
2019-07-08 10:55   ` Gupta, Anshuman
2019-07-08 13:31     ` Lucas De Marchi
2019-06-25 17:54 ` [PATCH 08/28] x86/gpu: add TGL stolen memory support Lucas De Marchi
2019-07-09 12:03   ` Rodrigo Vivi
2019-06-25 17:54 ` [PATCH 09/28] drm/i915/tgl: Check if pipe D is fused Lucas De Marchi
2019-06-26 21:24   ` Srivatsa, Anusha
2019-06-25 17:54 ` [PATCH 10/28] drm/i915/tgl: Add power well support Lucas De Marchi
2019-06-27 19:15   ` Manasi Navare
2019-06-27 20:23     ` Lucas De Marchi
2019-06-27 19:31   ` Souza, Jose
2019-06-27 20:22     ` Lucas De Marchi
2019-06-25 17:54 ` [PATCH 11/28] drm/i915/tgl: Add power well to support 4th pipe Lucas De Marchi
2019-07-01 17:54   ` Ville Syrjälä
2019-06-25 17:54 ` [PATCH 12/28] drm/i915/tgl: Add TRANSCODER_A_VDSC power domain Lucas De Marchi
2019-06-27 19:16   ` Manasi Navare
2019-06-27 19:28   ` Souza, Jose
2019-06-27 19:30     ` Souza, Jose
2019-06-27 19:33     ` Manasi Navare
2019-06-28  9:55   ` Ville Syrjälä
2019-06-28 16:31     ` Lucas De Marchi
2019-07-01 17:32       ` Ville Syrjälä
2019-07-01 17:36         ` Ville Syrjälä
2019-07-08 21:05         ` Lucas De Marchi
2019-06-25 17:54 ` [PATCH 13/28] drm/i915/tgl: Add new pll ids Lucas De Marchi
2019-06-26 23:12   ` Srivatsa, Anusha
2019-06-25 17:54 ` [PATCH 14/28] drm/i915/tgl: Add pll manager Lucas De Marchi
2019-06-25 17:54 ` [PATCH 15/28] drm/i915/tgl: Add additional ports for Tiger Lake Lucas De Marchi
2019-06-25 17:54 ` [PATCH 16/28] drm/i915/tgl: update ddi/tc clock_off bits Lucas De Marchi
2019-06-25 17:54 ` [PATCH 17/28] drm/i915/tgl: Add gmbus gpio pin to port mapping Lucas De Marchi
2019-06-25 17:54 ` [PATCH 18/28] drm/i915/tgl: port to ddc pin mapping Lucas De Marchi
2019-06-25 17:54 ` [PATCH 19/28] drm/i915/tgl: select correct bit for port select Lucas De Marchi
2019-06-25 17:54 ` [PATCH 20/28] drm/i915/tgl: Add third combophy offset Lucas De Marchi
2019-06-25 17:54 ` [PATCH 21/28] drm/i915/tgl: extend intel_port_is_combophy/tc Lucas De Marchi
2019-06-25 17:54 ` [PATCH 22/28] drm/i915/tgl: init ddi port A-C for Tiger Lake Lucas De Marchi
2019-06-25 17:54 ` Lucas De Marchi [this message]
2019-06-25 17:54 ` [PATCH 24/28] drm/i915/tgl: apply Display WA #1178 to fix type C dongles Lucas De Marchi
2019-06-25 17:54 ` [PATCH 25/28] drm/i915/gen12: MBUS B credit change Lucas De Marchi
2019-06-25 17:54 ` [PATCH 26/28] drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization Lucas De Marchi
2019-06-25 17:54 ` [PATCH 27/28] drm/i915/tgl: Add DPLL registers Lucas De Marchi
2019-06-25 17:54 ` [PATCH 28/28] drm/i915/tgl: Update DPLL clock reference register Lucas De Marchi
2019-06-26  0:00 ` ✗ Fi.CI.CHECKPATCH: warning for Initial support for Tiger Lake Patchwork
2019-06-26  0:54 ` ✓ Fi.CI.BAT: success " Patchwork
2019-06-26  1:43 ` [PATCH 00/28] " Souza, Jose
2019-06-26  5:10 ` ✓ Fi.CI.IGT: success for " Patchwork

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