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From: Andes <uboot@andestech.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v2 1/7] dm: cache: Add enable and disable ops for cache uclass
Date: Tue, 9 Jul 2019 17:28:08 +0800	[thread overview]
Message-ID: <20190709092814.21363-2-uboot@andestech.com> (raw)
In-Reply-To: <20190709092814.21363-1-uboot@andestech.com>

From: Rick Chen <rick@andestech.com>

The L2 cache will be enabled in init flow of dm cache
driver when it detect L2 node in dtb.

When U-Boot jump to Linux Kernel, the disable ops will
be called to flush and disable the L2 cache via the dm
cache driver.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
---
 drivers/cache/cache-uclass.c | 20 ++++++++++++++++++++
 include/cache.h              | 31 +++++++++++++++++++++++++++++++
 test/dm/cache.c              |  2 ++
 3 files changed, 53 insertions(+)

diff --git a/drivers/cache/cache-uclass.c b/drivers/cache/cache-uclass.c
index 97ce024..3b20a10 100644
--- a/drivers/cache/cache-uclass.c
+++ b/drivers/cache/cache-uclass.c
@@ -17,6 +17,26 @@ int cache_get_info(struct udevice *dev, struct cache_info *info)
 	return ops->get_info(dev, info);
 }
 
+int cache_enable(struct udevice *dev)
+{
+	struct cache_ops *ops = cache_get_ops(dev);
+
+	if (!ops->enable)
+		return -ENOSYS;
+
+	return ops->enable(dev);
+}
+
+int cache_disable(struct udevice *dev)
+{
+	struct cache_ops *ops = cache_get_ops(dev);
+
+	if (!ops->disable)
+		return -ENOSYS;
+
+	return ops->disable(dev);
+}
+
 UCLASS_DRIVER(cache) = {
 	.id		= UCLASS_CACHE,
 	.name		= "cache",
diff --git a/include/cache.h b/include/cache.h
index c6334ca..32f59fd 100644
--- a/include/cache.h
+++ b/include/cache.h
@@ -22,6 +22,22 @@ struct cache_ops {
 	 * @return 0 if OK, -ve on error
 	 */
 	int (*get_info)(struct udevice *dev, struct cache_info *info);
+
+	/**
+	 * enable() - Enable cache
+	 *
+	 * @dev:	Device to check (UCLASS_CACHE)
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*enable)(struct udevice *dev);
+
+	/**
+	 * disable() - Flush and disable cache
+	 *
+	 * @dev:	Device to check (UCLASS_CACHE)
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*disable)(struct udevice *dev);
 };
 
 #define cache_get_ops(dev)	((struct cache_ops *)(dev)->driver->ops)
@@ -35,4 +51,19 @@ struct cache_ops {
  */
 int cache_get_info(struct udevice *dev, struct cache_info *info);
 
+/**
+ * cache_enable() - Enable cache
+ *
+ * @dev:	Device to check (UCLASS_CACHE)
+ * @return 0 if OK, -ve on error
+ */
+int cache_enable(struct udevice *dev);
+
+/**
+ * cache_disable() - Flush and disable cache
+ *
+ * @dev:	Device to check (UCLASS_CACHE)
+ * @return 0 if OK, -ve on error
+ */
+int cache_disable(struct udevice *dev);
 #endif
diff --git a/test/dm/cache.c b/test/dm/cache.c
index d4144aa..2e244b1 100644
--- a/test/dm/cache.c
+++ b/test/dm/cache.c
@@ -14,6 +14,8 @@ static int dm_test_reset(struct unit_test_state *uts)
 
 	ut_assertok(uclass_get_device(UCLASS_CACHE, 0, &dev_cache));
 	ut_assertok(cache_get_info(dev, &info));
+	ut_assertok(cache_enable(dev));
+	ut_assertok(cache_disable(dev));
 
 	return 0;
 }
-- 
2.7.4

  reply	other threads:[~2019-07-09  9:28 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-09  9:28 [U-Boot] [PATCH v2 0/7] Support Andes RISC-V l2cache on AE350 platform Andes
2019-07-09  9:28 ` Andes [this message]
2019-07-11  2:49   ` [U-Boot] [PATCH v2 1/7] dm: cache: Add enable and disable ops for cache uclass Bin Meng
2019-07-17  7:33     ` Rick Chen
2019-07-09  9:28 ` [U-Boot] [PATCH v2 2/7] dm: cache: add v5l2 cache controller driver Andes
2019-07-11  3:04   ` Bin Meng
2019-07-17  7:30     ` Rick Chen
2019-07-09  9:28 ` [U-Boot] [PATCH v2 3/7] riscv: ae350: use the v5l2 driver to configure the cache Andes
2019-07-11  3:05   ` Bin Meng
2019-07-09  9:28 ` [U-Boot] [PATCH v2 4/7] riscv: ax25: add imply v5l2 cache controller Andes
2019-07-11  3:28   ` Bin Meng
2019-07-09  9:28 ` [U-Boot] [PATCH v2 5/7] riscv: cache: Flush L2 cache before jump to linux Andes
2019-07-11  4:20   ` Bin Meng
2019-07-17  7:24     ` Rick Chen
2019-07-09  9:28 ` [U-Boot] [PATCH v2 6/7] riscv: dts: move out AE350 L2 node from cpus node Andes
2019-07-11  4:21   ` Bin Meng
2019-07-09  9:28 ` [U-Boot] [PATCH v2 7/7] riscv: ax25: use CCTL to flush d-cache Andes
2019-07-11  5:35   ` Bin Meng

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