From: Andes <uboot@andestech.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v2 3/7] riscv: ae350: use the v5l2 driver to configure the cache
Date: Tue, 9 Jul 2019 17:28:10 +0800 [thread overview]
Message-ID: <20190709092814.21363-4-uboot@andestech.com> (raw)
In-Reply-To: <20190709092814.21363-1-uboot@andestech.com>
From: Rick Chen <rick@andestech.com>
Find the UCLASS_CACHE driver to configure the cache controller's
settings.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Cc: KC Lin <kclin@andestech.com>
---
board/AndesTech/ax25-ae350/ax25-ae350.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c b/board/AndesTech/ax25-ae350/ax25-ae350.c
index 3d65ce7..448ab0c 100644
--- a/board/AndesTech/ax25-ae350/ax25-ae350.c
+++ b/board/AndesTech/ax25-ae350/ax25-ae350.c
@@ -11,6 +11,7 @@
#include <linux/io.h>
#include <faraday/ftsmc020.h>
#include <fdtdec.h>
+#include <dm.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -93,10 +94,18 @@ int smc_init(void)
return 0;
}
+void v5l2_init(void)
+{
+ struct udevice *dev;
+
+ uclass_get_device(UCLASS_CACHE, 0, &dev);
+}
+
#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
smc_init();
+ v5l2_init();
return 0;
}
--
2.7.4
next prev parent reply other threads:[~2019-07-09 9:28 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-09 9:28 [U-Boot] [PATCH v2 0/7] Support Andes RISC-V l2cache on AE350 platform Andes
2019-07-09 9:28 ` [U-Boot] [PATCH v2 1/7] dm: cache: Add enable and disable ops for cache uclass Andes
2019-07-11 2:49 ` Bin Meng
2019-07-17 7:33 ` Rick Chen
2019-07-09 9:28 ` [U-Boot] [PATCH v2 2/7] dm: cache: add v5l2 cache controller driver Andes
2019-07-11 3:04 ` Bin Meng
2019-07-17 7:30 ` Rick Chen
2019-07-09 9:28 ` Andes [this message]
2019-07-11 3:05 ` [U-Boot] [PATCH v2 3/7] riscv: ae350: use the v5l2 driver to configure the cache Bin Meng
2019-07-09 9:28 ` [U-Boot] [PATCH v2 4/7] riscv: ax25: add imply v5l2 cache controller Andes
2019-07-11 3:28 ` Bin Meng
2019-07-09 9:28 ` [U-Boot] [PATCH v2 5/7] riscv: cache: Flush L2 cache before jump to linux Andes
2019-07-11 4:20 ` Bin Meng
2019-07-17 7:24 ` Rick Chen
2019-07-09 9:28 ` [U-Boot] [PATCH v2 6/7] riscv: dts: move out AE350 L2 node from cpus node Andes
2019-07-11 4:21 ` Bin Meng
2019-07-09 9:28 ` [U-Boot] [PATCH v2 7/7] riscv: ax25: use CCTL to flush d-cache Andes
2019-07-11 5:35 ` Bin Meng
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