From: Bin Meng <bmeng.cn@gmail.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v2 6/7] riscv: dts: move out AE350 L2 node from cpus node
Date: Thu, 11 Jul 2019 12:21:06 +0800 [thread overview]
Message-ID: <CAEUhbmUXgLeqFQbGbJjtxs91raQ7Mp5zscNKU6Xz_BFJ6voiXA@mail.gmail.com> (raw)
In-Reply-To: <20190709092814.21363-7-uboot@andestech.com>
On Tue, Jul 9, 2019 at 5:34 PM Andes <uboot@andestech.com> wrote:
>
> From: Rick Chen <rick@andestech.com>
>
> When L2 node exists inside cpus node, uclass_get_device
> can not parse L2 node successfully. So move it outside
> from cpus node.
>
> Also add tag-ram-ctl and data-ram-ctl attributes for
> v5l2 cache controller driver. This can adjust timing
> by requirement from dtb to improve performance.
>
> Signed-off-by: Rick Chen <rick@andestech.com>
> Cc: Greentime Hu <greentime@andestech.com>
> Cc: KC Lin <kclin@andestech.com>
> ---
> arch/riscv/dts/ae350_32.dts | 17 +++++++++++------
> arch/riscv/dts/ae350_64.dts | 17 +++++++++++------
> 2 files changed, 22 insertions(+), 12 deletions(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
next prev parent reply other threads:[~2019-07-11 4:21 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-09 9:28 [U-Boot] [PATCH v2 0/7] Support Andes RISC-V l2cache on AE350 platform Andes
2019-07-09 9:28 ` [U-Boot] [PATCH v2 1/7] dm: cache: Add enable and disable ops for cache uclass Andes
2019-07-11 2:49 ` Bin Meng
2019-07-17 7:33 ` Rick Chen
2019-07-09 9:28 ` [U-Boot] [PATCH v2 2/7] dm: cache: add v5l2 cache controller driver Andes
2019-07-11 3:04 ` Bin Meng
2019-07-17 7:30 ` Rick Chen
2019-07-09 9:28 ` [U-Boot] [PATCH v2 3/7] riscv: ae350: use the v5l2 driver to configure the cache Andes
2019-07-11 3:05 ` Bin Meng
2019-07-09 9:28 ` [U-Boot] [PATCH v2 4/7] riscv: ax25: add imply v5l2 cache controller Andes
2019-07-11 3:28 ` Bin Meng
2019-07-09 9:28 ` [U-Boot] [PATCH v2 5/7] riscv: cache: Flush L2 cache before jump to linux Andes
2019-07-11 4:20 ` Bin Meng
2019-07-17 7:24 ` Rick Chen
2019-07-09 9:28 ` [U-Boot] [PATCH v2 6/7] riscv: dts: move out AE350 L2 node from cpus node Andes
2019-07-11 4:21 ` Bin Meng [this message]
2019-07-09 9:28 ` [U-Boot] [PATCH v2 7/7] riscv: ax25: use CCTL to flush d-cache Andes
2019-07-11 5:35 ` Bin Meng
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