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From: Bin Meng <bmeng.cn@gmail.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v2 5/7] riscv: cache: Flush L2 cache before jump to linux
Date: Thu, 11 Jul 2019 12:20:32 +0800	[thread overview]
Message-ID: <CAEUhbmUDfnH3s8pq0RMyyi76cQtdjJPnVHBcBdhqCPvOVRd=_A@mail.gmail.com> (raw)
In-Reply-To: <20190709092814.21363-6-uboot@andestech.com>

On Tue, Jul 9, 2019 at 5:34 PM Andes <uboot@andestech.com> wrote:
>
> From: Rick Chen <rick@andestech.com>
>
> Flush and disable cache in cleanup_before_linux()
> which will be called before jump to linux.
>
> The sequence will be preferred as below:
> L1 flush -> L1 disable -> L2 flush -> L2 disable
>
> Signed-off-by: Rick Chen <rick@andestech.com>
> Cc: Greentime Hu <greentime@andestech.com>
> Cc: KC Lin <kclin@andestech.com>
> ---
>  arch/riscv/cpu/ax25/cpu.c | 26 ++++++++++++++++++++++++++
>  1 file changed, 26 insertions(+)
>
> diff --git a/arch/riscv/cpu/ax25/cpu.c b/arch/riscv/cpu/ax25/cpu.c
> index 76689b2..31a714e 100644
> --- a/arch/riscv/cpu/ax25/cpu.c
> +++ b/arch/riscv/cpu/ax25/cpu.c
> @@ -7,6 +7,29 @@
>  /* CPU specific code */
>  #include <common.h>
>  #include <asm/cache.h>
> +#include <dm.h>
> +#include <dm/uclass-internal.h>
> +#include <cache.h>
> +
> +void enable_v5l2(void)
> +{
> +       struct udevice *dev = NULL;
> +
> +       uclass_find_first_device(UCLASS_CACHE, &dev);
> +
> +       if (dev)
> +               cache_enable(dev);
> +}
> +
> +void disable_v5l2(void)
> +{
> +       struct udevice *dev = NULL;
> +
> +       uclass_find_first_device(UCLASS_CACHE, &dev);
> +
> +       if (dev)
> +               cache_disable(dev);
> +}
>
>  /*
>   * cleanup_before_linux() is called just before we call linux
> @@ -22,6 +45,9 @@ int cleanup_before_linux(void)
>         cache_flush();
>         icache_disable();
>         dcache_disable();
> +#ifdef CONFIG_RISCV_NDS_CACHE
> +       disable_v5l2();
> +#endif

Since dcache_disable() is a weak symbol, could you please move the
codes in disable_v5l2() to the AX25 specific implementation of
dcache_disable()?

Regards,
Bin

  reply	other threads:[~2019-07-11  4:20 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-09  9:28 [U-Boot] [PATCH v2 0/7] Support Andes RISC-V l2cache on AE350 platform Andes
2019-07-09  9:28 ` [U-Boot] [PATCH v2 1/7] dm: cache: Add enable and disable ops for cache uclass Andes
2019-07-11  2:49   ` Bin Meng
2019-07-17  7:33     ` Rick Chen
2019-07-09  9:28 ` [U-Boot] [PATCH v2 2/7] dm: cache: add v5l2 cache controller driver Andes
2019-07-11  3:04   ` Bin Meng
2019-07-17  7:30     ` Rick Chen
2019-07-09  9:28 ` [U-Boot] [PATCH v2 3/7] riscv: ae350: use the v5l2 driver to configure the cache Andes
2019-07-11  3:05   ` Bin Meng
2019-07-09  9:28 ` [U-Boot] [PATCH v2 4/7] riscv: ax25: add imply v5l2 cache controller Andes
2019-07-11  3:28   ` Bin Meng
2019-07-09  9:28 ` [U-Boot] [PATCH v2 5/7] riscv: cache: Flush L2 cache before jump to linux Andes
2019-07-11  4:20   ` Bin Meng [this message]
2019-07-17  7:24     ` Rick Chen
2019-07-09  9:28 ` [U-Boot] [PATCH v2 6/7] riscv: dts: move out AE350 L2 node from cpus node Andes
2019-07-11  4:21   ` Bin Meng
2019-07-09  9:28 ` [U-Boot] [PATCH v2 7/7] riscv: ax25: use CCTL to flush d-cache Andes
2019-07-11  5:35   ` Bin Meng

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