* [PATCH 1/2] drm/i915/display/tgl: Bump up the mode vertical limits to support 8K @ 2019-07-09 21:47 Manasi Navare 2019-07-09 21:47 ` [PATCH 2/2] drm/i915/display/tgl: Bump up the plane/fb height " Manasi Navare ` (6 more replies) 0 siblings, 7 replies; 16+ messages in thread From: Manasi Navare @ 2019-07-09 21:47 UTC (permalink / raw) To: intel-gfx On TGL+ we support 8K display resolution, hence bump up the vertical active limits to 4320 in intel_mode_valid() Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index f07081815b80..0d5c8af01f54 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -15764,8 +15764,13 @@ intel_mode_valid(struct drm_device *dev, DRM_MODE_FLAG_CLKDIV2)) return MODE_BAD; - if (INTEL_GEN(dev_priv) >= 9 || - IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { + if (INTEL_GEN(dev_priv) >=12) { + hdisplay_max = 8192; + vdisplay_max = 4320; + htotal_max = 8192; + vtotal_max = 8192; + } else if (INTEL_GEN(dev_priv) >= 9 || + IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */ vdisplay_max = 4096; htotal_max = 8192; -- 2.19.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 2/2] drm/i915/display/tgl: Bump up the plane/fb height to support 8K 2019-07-09 21:47 [PATCH 1/2] drm/i915/display/tgl: Bump up the mode vertical limits to support 8K Manasi Navare @ 2019-07-09 21:47 ` Manasi Navare 2019-07-09 23:07 ` Souza, Jose 2019-07-10 19:18 ` Ville Syrjälä 2019-07-09 22:07 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/display/tgl: Bump up the mode vertical limits " Patchwork ` (5 subsequent siblings) 6 siblings, 2 replies; 16+ messages in thread From: Manasi Navare @ 2019-07-09 21:47 UTC (permalink / raw) To: intel-gfx On TGL+, the plane height for 8K planes can be 4320, so bump it up To support 4320, we need to increase the number of bits used to read plane_height to 13 as opposed to older 12 bits. Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 21 ++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 0d5c8af01f54..be9a54cb5ecc 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -3343,6 +3343,16 @@ static int icl_max_plane_width(const struct drm_framebuffer *fb, return 5120; } +static int skl_max_plane_height(void) +{ + return 4096; +} + +static int tgl_max_plane_height(void) +{ + return 4320; +} + static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state, int main_x, int main_y, u32 main_offset) { @@ -3391,9 +3401,13 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state) int w = drm_rect_width(&plane_state->base.src) >> 16; int h = drm_rect_height(&plane_state->base.src) >> 16; int max_width; - int max_height = 4096; + int max_height; u32 alignment, offset, aux_offset = plane_state->color_plane[1].offset; + if (INTEL_GEN(dev_priv) >= 12) + max_height = tgl_max_plane_height(); + else + max_height = skl_max_plane_height(); if (INTEL_GEN(dev_priv) >= 11) max_width = icl_max_plane_width(fb, 0, rotation); else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) @@ -9865,7 +9879,10 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc, offset = I915_READ(PLANE_OFFSET(pipe, plane_id)); val = I915_READ(PLANE_SIZE(pipe, plane_id)); - fb->height = ((val >> 16) & 0xfff) + 1; + if (INTEL_GEN(dev_priv) >= 12) + fb->height = ((val >> 16) & 0x1fff) + 1; + else + fb->height = ((val >> 16) & 0xfff) + 1; fb->width = ((val >> 0) & 0x1fff) + 1; val = I915_READ(PLANE_STRIDE(pipe, plane_id)); -- 2.19.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH 2/2] drm/i915/display/tgl: Bump up the plane/fb height to support 8K 2019-07-09 21:47 ` [PATCH 2/2] drm/i915/display/tgl: Bump up the plane/fb height " Manasi Navare @ 2019-07-09 23:07 ` Souza, Jose 2019-07-10 18:57 ` Manasi Navare 2019-07-10 19:18 ` Ville Syrjälä 1 sibling, 1 reply; 16+ messages in thread From: Souza, Jose @ 2019-07-09 23:07 UTC (permalink / raw) To: intel-gfx, Navare, Manasi D On Tue, 2019-07-09 at 14:47 -0700, Manasi Navare wrote: > On TGL+, the plane height for 8K planes can be 4320, so bump it up > To support 4320, we need to increase the number of bits used to > read plane_height to 13 as opposed to older 12 bits. > > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> > --- > drivers/gpu/drm/i915/display/intel_display.c | 21 > ++++++++++++++++++-- > 1 file changed, 19 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > b/drivers/gpu/drm/i915/display/intel_display.c > index 0d5c8af01f54..be9a54cb5ecc 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -3343,6 +3343,16 @@ static int icl_max_plane_width(const struct > drm_framebuffer *fb, > return 5120; > } > > +static int skl_max_plane_height(void) > +{ > + return 4096; > +} > + > +static int tgl_max_plane_height(void) > +{ > + return 4320; > +} > + > static bool skl_check_main_ccs_coordinates(struct intel_plane_state > *plane_state, > int main_x, int main_y, u32 > main_offset) > { > @@ -3391,9 +3401,13 @@ static int skl_check_main_surface(struct > intel_plane_state *plane_state) > int w = drm_rect_width(&plane_state->base.src) >> 16; > int h = drm_rect_height(&plane_state->base.src) >> 16; > int max_width; > - int max_height = 4096; > + int max_height; > u32 alignment, offset, aux_offset = plane_state- > >color_plane[1].offset; > > + if (INTEL_GEN(dev_priv) >= 12) > + max_height = tgl_max_plane_height(); > + else > + max_height = skl_max_plane_height(); Give a line between max_width block, also I would move the height after the width. > if (INTEL_GEN(dev_priv) >= 11) > max_width = icl_max_plane_width(fb, 0, rotation); > else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) > @@ -9865,7 +9879,10 @@ skylake_get_initial_plane_config(struct > intel_crtc *crtc, > offset = I915_READ(PLANE_OFFSET(pipe, plane_id)); > > val = I915_READ(PLANE_SIZE(pipe, plane_id)); > - fb->height = ((val >> 16) & 0xfff) + 1; > + if (INTEL_GEN(dev_priv) >= 12) > + fb->height = ((val >> 16) & 0x1fff) + 1; > + else > + fb->height = ((val >> 16) & 0xfff) + 1; > fb->width = ((val >> 0) & 0x1fff) + 1; > > val = I915_READ(PLANE_STRIDE(pipe, plane_id)); _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 2/2] drm/i915/display/tgl: Bump up the plane/fb height to support 8K 2019-07-09 23:07 ` Souza, Jose @ 2019-07-10 18:57 ` Manasi Navare 0 siblings, 0 replies; 16+ messages in thread From: Manasi Navare @ 2019-07-10 18:57 UTC (permalink / raw) To: Souza, Jose; +Cc: intel-gfx On Tue, Jul 09, 2019 at 04:07:23PM -0700, Souza, Jose wrote: > On Tue, 2019-07-09 at 14:47 -0700, Manasi Navare wrote: > > On TGL+, the plane height for 8K planes can be 4320, so bump it up > > To support 4320, we need to increase the number of bits used to > > read plane_height to 13 as opposed to older 12 bits. > > > > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_display.c | 21 > > ++++++++++++++++++-- > > 1 file changed, 19 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > > b/drivers/gpu/drm/i915/display/intel_display.c > > index 0d5c8af01f54..be9a54cb5ecc 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > @@ -3343,6 +3343,16 @@ static int icl_max_plane_width(const struct > > drm_framebuffer *fb, > > return 5120; > > } > > > > +static int skl_max_plane_height(void) > > +{ > > + return 4096; > > +} > > + > > +static int tgl_max_plane_height(void) > > +{ > > + return 4320; > > +} > > + > > static bool skl_check_main_ccs_coordinates(struct intel_plane_state > > *plane_state, > > int main_x, int main_y, u32 > > main_offset) > > { > > @@ -3391,9 +3401,13 @@ static int skl_check_main_surface(struct > > intel_plane_state *plane_state) > > int w = drm_rect_width(&plane_state->base.src) >> 16; > > int h = drm_rect_height(&plane_state->base.src) >> 16; > > int max_width; > > - int max_height = 4096; > > + int max_height; > > u32 alignment, offset, aux_offset = plane_state- > > >color_plane[1].offset; > > > > + if (INTEL_GEN(dev_priv) >= 12) > > + max_height = tgl_max_plane_height(); > > + else > > + max_height = skl_max_plane_height(); > > Give a line between max_width block, also I would move the height after > the width. Ok, will make this change, can I add your r-b with this change? Manasi > > > if (INTEL_GEN(dev_priv) >= 11) > > max_width = icl_max_plane_width(fb, 0, rotation); > > else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) > > @@ -9865,7 +9879,10 @@ skylake_get_initial_plane_config(struct > > intel_crtc *crtc, > > offset = I915_READ(PLANE_OFFSET(pipe, plane_id)); > > > > val = I915_READ(PLANE_SIZE(pipe, plane_id)); > > - fb->height = ((val >> 16) & 0xfff) + 1; > > + if (INTEL_GEN(dev_priv) >= 12) > > + fb->height = ((val >> 16) & 0x1fff) + 1; > > + else > > + fb->height = ((val >> 16) & 0xfff) + 1; > > fb->width = ((val >> 0) & 0x1fff) + 1; > > > > val = I915_READ(PLANE_STRIDE(pipe, plane_id)); _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 2/2] drm/i915/display/tgl: Bump up the plane/fb height to support 8K 2019-07-09 21:47 ` [PATCH 2/2] drm/i915/display/tgl: Bump up the plane/fb height " Manasi Navare 2019-07-09 23:07 ` Souza, Jose @ 2019-07-10 19:18 ` Ville Syrjälä 2019-07-10 19:36 ` Manasi Navare 1 sibling, 1 reply; 16+ messages in thread From: Ville Syrjälä @ 2019-07-10 19:18 UTC (permalink / raw) To: Manasi Navare; +Cc: intel-gfx On Tue, Jul 09, 2019 at 02:47:35PM -0700, Manasi Navare wrote: > On TGL+, the plane height for 8K planes can be 4320, so bump it up > To support 4320, we need to increase the number of bits used to > read plane_height to 13 as opposed to older 12 bits. > > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> > --- > drivers/gpu/drm/i915/display/intel_display.c | 21 ++++++++++++++++++-- > 1 file changed, 19 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index 0d5c8af01f54..be9a54cb5ecc 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -3343,6 +3343,16 @@ static int icl_max_plane_width(const struct drm_framebuffer *fb, > return 5120; > } > > +static int skl_max_plane_height(void) > +{ > + return 4096; > +} > + > +static int tgl_max_plane_height(void) > +{ > + return 4320; icl has this limit already. > +} > + > static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state, > int main_x, int main_y, u32 main_offset) > { > @@ -3391,9 +3401,13 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state) > int w = drm_rect_width(&plane_state->base.src) >> 16; > int h = drm_rect_height(&plane_state->base.src) >> 16; > int max_width; > - int max_height = 4096; > + int max_height; > u32 alignment, offset, aux_offset = plane_state->color_plane[1].offset; > > + if (INTEL_GEN(dev_priv) >= 12) > + max_height = tgl_max_plane_height(); > + else > + max_height = skl_max_plane_height(); > if (INTEL_GEN(dev_priv) >= 11) > max_width = icl_max_plane_width(fb, 0, rotation); > else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) > @@ -9865,7 +9879,10 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc, > offset = I915_READ(PLANE_OFFSET(pipe, plane_id)); > > val = I915_READ(PLANE_SIZE(pipe, plane_id)); > - fb->height = ((val >> 16) & 0xfff) + 1; > + if (INTEL_GEN(dev_priv) >= 12) > + fb->height = ((val >> 16) & 0x1fff) + 1; > + else > + fb->height = ((val >> 16) & 0xfff) + 1; > fb->width = ((val >> 0) & 0x1fff) + 1; > > val = I915_READ(PLANE_STRIDE(pipe, plane_id)); > -- > 2.19.1 -- Ville Syrjälä Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 2/2] drm/i915/display/tgl: Bump up the plane/fb height to support 8K 2019-07-10 19:18 ` Ville Syrjälä @ 2019-07-10 19:36 ` Manasi Navare 0 siblings, 0 replies; 16+ messages in thread From: Manasi Navare @ 2019-07-10 19:36 UTC (permalink / raw) To: Ville Syrjälä; +Cc: intel-gfx On Wed, Jul 10, 2019 at 10:18:38PM +0300, Ville Syrjälä wrote: > On Tue, Jul 09, 2019 at 02:47:35PM -0700, Manasi Navare wrote: > > On TGL+, the plane height for 8K planes can be 4320, so bump it up > > To support 4320, we need to increase the number of bits used to > > read plane_height to 13 as opposed to older 12 bits. > > > > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_display.c | 21 ++++++++++++++++++-- > > 1 file changed, 19 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > > index 0d5c8af01f54..be9a54cb5ecc 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > @@ -3343,6 +3343,16 @@ static int icl_max_plane_width(const struct drm_framebuffer *fb, > > return 5120; > > } > > > > +static int skl_max_plane_height(void) > > +{ > > + return 4096; > > +} > > + > > +static int tgl_max_plane_height(void) > > +{ > > + return 4320; Yes icl does but we start supporting 8K from tgl, should this be changed to icl_max_plane_height() and return 4320? Manasi > > icl has this limit already. > > > +} > > + > > static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state, > > int main_x, int main_y, u32 main_offset) > > { > > @@ -3391,9 +3401,13 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state) > > int w = drm_rect_width(&plane_state->base.src) >> 16; > > int h = drm_rect_height(&plane_state->base.src) >> 16; > > int max_width; > > - int max_height = 4096; > > + int max_height; > > u32 alignment, offset, aux_offset = plane_state->color_plane[1].offset; > > > > + if (INTEL_GEN(dev_priv) >= 12) > > + max_height = tgl_max_plane_height(); > > + else > > + max_height = skl_max_plane_height(); > > if (INTEL_GEN(dev_priv) >= 11) > > max_width = icl_max_plane_width(fb, 0, rotation); > > else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) > > @@ -9865,7 +9879,10 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc, > > offset = I915_READ(PLANE_OFFSET(pipe, plane_id)); > > > > val = I915_READ(PLANE_SIZE(pipe, plane_id)); > > - fb->height = ((val >> 16) & 0xfff) + 1; > > + if (INTEL_GEN(dev_priv) >= 12) > > + fb->height = ((val >> 16) & 0x1fff) + 1; > > + else > > + fb->height = ((val >> 16) & 0xfff) + 1; > > fb->width = ((val >> 0) & 0x1fff) + 1; > > > > val = I915_READ(PLANE_STRIDE(pipe, plane_id)); > > -- > > 2.19.1 > > -- > Ville Syrjälä > Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 16+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/display/tgl: Bump up the mode vertical limits to support 8K 2019-07-09 21:47 [PATCH 1/2] drm/i915/display/tgl: Bump up the mode vertical limits to support 8K Manasi Navare 2019-07-09 21:47 ` [PATCH 2/2] drm/i915/display/tgl: Bump up the plane/fb height " Manasi Navare @ 2019-07-09 22:07 ` Patchwork 2019-07-09 22:49 ` ✓ Fi.CI.BAT: success " Patchwork ` (4 subsequent siblings) 6 siblings, 0 replies; 16+ messages in thread From: Patchwork @ 2019-07-09 22:07 UTC (permalink / raw) To: Manasi Navare; +Cc: intel-gfx == Series Details == Series: series starting with [1/2] drm/i915/display/tgl: Bump up the mode vertical limits to support 8K URL : https://patchwork.freedesktop.org/series/63458/ State : warning == Summary == $ dim checkpatch origin/drm-tip 90e13413f8fd drm/i915/display/tgl: Bump up the mode vertical limits to support 8K -:27: ERROR:SPACING: spaces required around that '>=' (ctx:WxV) #27: FILE: drivers/gpu/drm/i915/display/intel_display.c:15767: + if (INTEL_GEN(dev_priv) >=12) { ^ total: 1 errors, 0 warnings, 0 checks, 15 lines checked dc819529058c drm/i915/display/tgl: Bump up the plane/fb height to support 8K _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 16+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/display/tgl: Bump up the mode vertical limits to support 8K 2019-07-09 21:47 [PATCH 1/2] drm/i915/display/tgl: Bump up the mode vertical limits to support 8K Manasi Navare 2019-07-09 21:47 ` [PATCH 2/2] drm/i915/display/tgl: Bump up the plane/fb height " Manasi Navare 2019-07-09 22:07 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/display/tgl: Bump up the mode vertical limits " Patchwork @ 2019-07-09 22:49 ` Patchwork 2019-07-09 23:04 ` [PATCH 1/2] " Souza, Jose ` (3 subsequent siblings) 6 siblings, 0 replies; 16+ messages in thread From: Patchwork @ 2019-07-09 22:49 UTC (permalink / raw) To: Manasi Navare; +Cc: intel-gfx == Series Details == Series: series starting with [1/2] drm/i915/display/tgl: Bump up the mode vertical limits to support 8K URL : https://patchwork.freedesktop.org/series/63458/ State : success == Summary == CI Bug Log - changes from CI_DRM_6446 -> Patchwork_13591 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13591/ Known issues ------------ Here are the changes found in Patchwork_13591 that come from known issues: ### IGT changes ### #### Possible fixes #### * {igt@gem_ctx_switch@legacy-render}: - fi-cml-u: [INCOMPLETE][1] ([fdo#110566]) -> [PASS][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/fi-cml-u/igt@gem_ctx_switch@legacy-render.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13591/fi-cml-u/igt@gem_ctx_switch@legacy-render.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485 [fdo#110566]: https://bugs.freedesktop.org/show_bug.cgi?id=110566 [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045 [fdo#111046 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111046 Participating hosts (51 -> 46) ------------------------------ Additional (2): fi-byt-j1900 fi-snb-2600 Missing (7): fi-kbl-soraka fi-hsw-4770r fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_6446 -> Patchwork_13591 CI_DRM_6446: 835fbe24abe47946fc514871f5cbe334d0be9854 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5092: 2a66ae6626d5583240509f84117d1345a799b75a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_13591: dc819529058c1e30cee0b2f6928c72ae2df15cde @ git://anongit.freedesktop.org/gfx-ci/linux == Kernel 32bit build == Warning: Kernel 32bit buildtest failed: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13591/build_32bit.log CALL scripts/checksyscalls.sh CALL scripts/atomic/check-atomics.sh CHK include/generated/compile.h Kernel: arch/x86/boot/bzImage is ready (#1) Building modules, stage 2. MODPOST 112 modules ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! scripts/Makefile.modpost:91: recipe for target '__modpost' failed make[1]: *** [__modpost] Error 1 Makefile:1287: recipe for target 'modules' failed make: *** [modules] Error 2 == Linux commits == dc819529058c drm/i915/display/tgl: Bump up the plane/fb height to support 8K 90e13413f8fd drm/i915/display/tgl: Bump up the mode vertical limits to support 8K == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13591/ _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/2] drm/i915/display/tgl: Bump up the mode vertical limits to support 8K 2019-07-09 21:47 [PATCH 1/2] drm/i915/display/tgl: Bump up the mode vertical limits to support 8K Manasi Navare ` (2 preceding siblings ...) 2019-07-09 22:49 ` ✓ Fi.CI.BAT: success " Patchwork @ 2019-07-09 23:04 ` Souza, Jose 2019-07-10 18:57 ` Manasi Navare 2019-07-10 0:06 ` [PATCH v2] " Manasi Navare ` (2 subsequent siblings) 6 siblings, 1 reply; 16+ messages in thread From: Souza, Jose @ 2019-07-09 23:04 UTC (permalink / raw) To: intel-gfx, Navare, Manasi D On Tue, 2019-07-09 at 14:47 -0700, Manasi Navare wrote: > On TGL+ we support 8K display resolution, hence bump up the vertical > active limits to 4320 in intel_mode_valid() > > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> > --- > drivers/gpu/drm/i915/display/intel_display.c | 9 +++++++-- > 1 file changed, 7 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > b/drivers/gpu/drm/i915/display/intel_display.c > index f07081815b80..0d5c8af01f54 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -15764,8 +15764,13 @@ intel_mode_valid(struct drm_device *dev, > DRM_MODE_FLAG_CLKDIV2)) > return MODE_BAD; > > - if (INTEL_GEN(dev_priv) >= 9 || > - IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { > + if (INTEL_GEN(dev_priv) >=12) { if (INTEL_GEN(dev_priv) >= 12) { > + hdisplay_max = 8192; > + vdisplay_max = 4320; > + htotal_max = 8192; > + vtotal_max = 8192; > + } else if (INTEL_GEN(dev_priv) >= 9 || > + IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { > hdisplay_max = 8192; /* FDI max 4096 handled elsewhere > */ > vdisplay_max = 4096; > htotal_max = 8192; _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/2] drm/i915/display/tgl: Bump up the mode vertical limits to support 8K 2019-07-09 23:04 ` [PATCH 1/2] " Souza, Jose @ 2019-07-10 18:57 ` Manasi Navare 0 siblings, 0 replies; 16+ messages in thread From: Manasi Navare @ 2019-07-10 18:57 UTC (permalink / raw) To: Souza, Jose; +Cc: intel-gfx On Tue, Jul 09, 2019 at 04:04:58PM -0700, Souza, Jose wrote: > On Tue, 2019-07-09 at 14:47 -0700, Manasi Navare wrote: > > On TGL+ we support 8K display resolution, hence bump up the vertical > > active limits to 4320 in intel_mode_valid() > > > > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_display.c | 9 +++++++-- > > 1 file changed, 7 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > > b/drivers/gpu/drm/i915/display/intel_display.c > > index f07081815b80..0d5c8af01f54 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > @@ -15764,8 +15764,13 @@ intel_mode_valid(struct drm_device *dev, > > DRM_MODE_FLAG_CLKDIV2)) > > return MODE_BAD; > > > > - if (INTEL_GEN(dev_priv) >= 9 || > > - IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { > > + if (INTEL_GEN(dev_priv) >=12) { > > > if (INTEL_GEN(dev_priv) >= 12) { Yup already made this change in v2, r-b with this change? Manasi > > > + hdisplay_max = 8192; > > + vdisplay_max = 4320; > > + htotal_max = 8192; > > + vtotal_max = 8192; > > + } else if (INTEL_GEN(dev_priv) >= 9 || > > + IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { > > hdisplay_max = 8192; /* FDI max 4096 handled elsewhere > > */ > > vdisplay_max = 4096; > > htotal_max = 8192; _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v2] drm/i915/display/tgl: Bump up the mode vertical limits to support 8K 2019-07-09 21:47 [PATCH 1/2] drm/i915/display/tgl: Bump up the mode vertical limits to support 8K Manasi Navare ` (3 preceding siblings ...) 2019-07-09 23:04 ` [PATCH 1/2] " Souza, Jose @ 2019-07-10 0:06 ` Manasi Navare 2019-07-10 19:15 ` Ville Syrjälä 2019-07-10 0:40 ` ✓ Fi.CI.BAT: success for series starting with [v2] drm/i915/display/tgl: Bump up the mode vertical limits to support 8K (rev2) Patchwork 2019-07-11 9:07 ` ✓ Fi.CI.IGT: " Patchwork 6 siblings, 1 reply; 16+ messages in thread From: Manasi Navare @ 2019-07-10 0:06 UTC (permalink / raw) To: intel-gfx On TGL+ we support 8K display resolution, hence bump up the vertical active limits to 4320 in intel_mode_valid() v2: * Checkpatch warning (Manasi) Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index f07081815b80..cfceb27e4b9e 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -15764,8 +15764,13 @@ intel_mode_valid(struct drm_device *dev, DRM_MODE_FLAG_CLKDIV2)) return MODE_BAD; - if (INTEL_GEN(dev_priv) >= 9 || - IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { + if (INTEL_GEN(dev_priv) >= 12) { + hdisplay_max = 8192; + vdisplay_max = 4320; + htotal_max = 8192; + vtotal_max = 8192; + } else if (INTEL_GEN(dev_priv) >= 9 || + IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */ vdisplay_max = 4096; htotal_max = 8192; -- 2.19.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH v2] drm/i915/display/tgl: Bump up the mode vertical limits to support 8K 2019-07-10 0:06 ` [PATCH v2] " Manasi Navare @ 2019-07-10 19:15 ` Ville Syrjälä 2019-07-10 19:24 ` Manasi Navare 0 siblings, 1 reply; 16+ messages in thread From: Ville Syrjälä @ 2019-07-10 19:15 UTC (permalink / raw) To: Manasi Navare; +Cc: intel-gfx On Tue, Jul 09, 2019 at 05:06:13PM -0700, Manasi Navare wrote: > On TGL+ we support 8K display resolution, hence bump up the vertical > active limits to 4320 in intel_mode_valid() > > v2: > * Checkpatch warning (Manasi) > > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> > --- > drivers/gpu/drm/i915/display/intel_display.c | 9 +++++++-- > 1 file changed, 7 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index f07081815b80..cfceb27e4b9e 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -15764,8 +15764,13 @@ intel_mode_valid(struct drm_device *dev, > DRM_MODE_FLAG_CLKDIV2)) > return MODE_BAD; > > - if (INTEL_GEN(dev_priv) >= 9 || > - IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { > + if (INTEL_GEN(dev_priv) >= 12) { > + hdisplay_max = 8192; > + vdisplay_max = 4320; > + htotal_max = 8192; > + vtotal_max = 8192; I wonder if we can safely bump these before we get the joiner stuff sorted. Hmm. I guess it should be fine as the limit that is supposed to overcome is caused by the cdclk max frequency being too low to allow a single pipe to push enough pixels. And since we check that in .mode_valid() we shouldn't accidentally start to advertize support for modes we can't do. Which means these limits should actually be higher than this. 16k for htotal+hdisplay and 8k for vtotal+vdisplay already on icl I believe. > + } else if (INTEL_GEN(dev_priv) >= 9 || > + IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { > hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */ > vdisplay_max = 4096; > htotal_max = 8192; > -- > 2.19.1 -- Ville Syrjälä Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v2] drm/i915/display/tgl: Bump up the mode vertical limits to support 8K 2019-07-10 19:15 ` Ville Syrjälä @ 2019-07-10 19:24 ` Manasi Navare 2019-07-10 19:30 ` Ville Syrjälä 0 siblings, 1 reply; 16+ messages in thread From: Manasi Navare @ 2019-07-10 19:24 UTC (permalink / raw) To: Ville Syrjälä; +Cc: intel-gfx On Wed, Jul 10, 2019 at 10:15:05PM +0300, Ville Syrjälä wrote: > On Tue, Jul 09, 2019 at 05:06:13PM -0700, Manasi Navare wrote: > > On TGL+ we support 8K display resolution, hence bump up the vertical > > active limits to 4320 in intel_mode_valid() > > > > v2: > > * Checkpatch warning (Manasi) > > > > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_display.c | 9 +++++++-- > > 1 file changed, 7 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > > index f07081815b80..cfceb27e4b9e 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > @@ -15764,8 +15764,13 @@ intel_mode_valid(struct drm_device *dev, > > DRM_MODE_FLAG_CLKDIV2)) > > return MODE_BAD; > > > > - if (INTEL_GEN(dev_priv) >= 9 || > > - IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { > > + if (INTEL_GEN(dev_priv) >= 12) { > > + hdisplay_max = 8192; > > + vdisplay_max = 4320; > > + htotal_max = 8192; > > + vtotal_max = 8192; > > I wonder if we can safely bump these before we get the joiner stuff sorted. > Hmm. I guess it should be fine as the limit that is supposed to overcome > is caused by the cdclk max frequency being too low to allow a single > pipe to push enough pixels. And since we check that in .mode_valid() we > shouldn't accidentally start to advertize support for modes we can't do. Yes the intel_dp_mode_valid() will still reject the modes until we have the support for big joiner, so allowing these limits should be fine here. Same for the plane size limits. Plane size limits bumping up is also needed in case of tiled 8K display with transcdoer port sync > > Which means these limits should actually be higher than this. 16k for > htotal+hdisplay and 8k for vtotal+vdisplay already on icl I believe. Where do we set htotal+hdisplay? And I added this for tgl, since we would be supporting the 8K res only on tgl onwards, correct? Manasi > > > + } else if (INTEL_GEN(dev_priv) >= 9 || > > + IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { > > hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */ > > vdisplay_max = 4096; > > htotal_max = 8192; > > -- > > 2.19.1 > > -- > Ville Syrjälä > Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v2] drm/i915/display/tgl: Bump up the mode vertical limits to support 8K 2019-07-10 19:24 ` Manasi Navare @ 2019-07-10 19:30 ` Ville Syrjälä 0 siblings, 0 replies; 16+ messages in thread From: Ville Syrjälä @ 2019-07-10 19:30 UTC (permalink / raw) To: Manasi Navare; +Cc: intel-gfx On Wed, Jul 10, 2019 at 12:24:15PM -0700, Manasi Navare wrote: > On Wed, Jul 10, 2019 at 10:15:05PM +0300, Ville Syrjälä wrote: > > On Tue, Jul 09, 2019 at 05:06:13PM -0700, Manasi Navare wrote: > > > On TGL+ we support 8K display resolution, hence bump up the vertical > > > active limits to 4320 in intel_mode_valid() > > > > > > v2: > > > * Checkpatch warning (Manasi) > > > > > > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> > > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> > > > --- > > > drivers/gpu/drm/i915/display/intel_display.c | 9 +++++++-- > > > 1 file changed, 7 insertions(+), 2 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > > > index f07081815b80..cfceb27e4b9e 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > > @@ -15764,8 +15764,13 @@ intel_mode_valid(struct drm_device *dev, > > > DRM_MODE_FLAG_CLKDIV2)) > > > return MODE_BAD; > > > > > > - if (INTEL_GEN(dev_priv) >= 9 || > > > - IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { > > > + if (INTEL_GEN(dev_priv) >= 12) { > > > + hdisplay_max = 8192; > > > + vdisplay_max = 4320; > > > + htotal_max = 8192; > > > + vtotal_max = 8192; > > > > I wonder if we can safely bump these before we get the joiner stuff sorted. > > Hmm. I guess it should be fine as the limit that is supposed to overcome > > is caused by the cdclk max frequency being too low to allow a single > > pipe to push enough pixels. And since we check that in .mode_valid() we > > shouldn't accidentally start to advertize support for modes we can't do. > > Yes the intel_dp_mode_valid() will still reject the modes until we have the support > for big joiner, so allowing these limits should be fine here. > > Same for the plane size limits. Plane size limits bumping up is also > needed in case of tiled 8K display with transcdoer port sync > > > > > Which means these limits should actually be higher than this. 16k for > > htotal+hdisplay and 8k for vtotal+vdisplay already on icl I believe. > > Where do we set htotal+hdisplay? And I added this for tgl, since we would be > supporting the 8K res only on tgl onwards, correct? We can do 8k on earlier platforms too, assuming the clock is low enough. Also icl already can do the joining stuff no? Anwyays these number are just the straight up transcoder max timings from the spec, and that's what I think they should stay. If we need to impose some other arbitrary limits for other reasons we should do that separately. Hmm. I guess planes is the other thing that's a problem for 8k and such. The documented max width is too small for any single plane to cover such a big pipe. We should perhaps be validating modes against the plane limits as well... -- Ville Syrjälä Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 16+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [v2] drm/i915/display/tgl: Bump up the mode vertical limits to support 8K (rev2) 2019-07-09 21:47 [PATCH 1/2] drm/i915/display/tgl: Bump up the mode vertical limits to support 8K Manasi Navare ` (4 preceding siblings ...) 2019-07-10 0:06 ` [PATCH v2] " Manasi Navare @ 2019-07-10 0:40 ` Patchwork 2019-07-11 9:07 ` ✓ Fi.CI.IGT: " Patchwork 6 siblings, 0 replies; 16+ messages in thread From: Patchwork @ 2019-07-10 0:40 UTC (permalink / raw) To: Manasi Navare; +Cc: intel-gfx == Series Details == Series: series starting with [v2] drm/i915/display/tgl: Bump up the mode vertical limits to support 8K (rev2) URL : https://patchwork.freedesktop.org/series/63458/ State : success == Summary == CI Bug Log - changes from CI_DRM_6446 -> Patchwork_13593 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13593/ Known issues ------------ Here are the changes found in Patchwork_13593 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_flink_basic@bad-open: - fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/fi-icl-u3/igt@gem_flink_basic@bad-open.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13593/fi-icl-u3/igt@gem_flink_basic@bad-open.html * igt@prime_self_import@basic-with_one_bo: - fi-icl-dsi: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/fi-icl-dsi/igt@prime_self_import@basic-with_one_bo.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13593/fi-icl-dsi/igt@prime_self_import@basic-with_one_bo.html #### Possible fixes #### * {igt@gem_ctx_switch@legacy-render}: - fi-cml-u: [INCOMPLETE][5] ([fdo#110566]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/fi-cml-u/igt@gem_ctx_switch@legacy-render.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13593/fi-cml-u/igt@gem_ctx_switch@legacy-render.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][7] ([fdo#109485]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13593/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485 [fdo#110566]: https://bugs.freedesktop.org/show_bug.cgi?id=110566 [fdo#111046 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111046 Participating hosts (51 -> 46) ------------------------------ Additional (2): fi-byt-j1900 fi-snb-2600 Missing (7): fi-kbl-soraka fi-byt-squawks fi-bsw-cyan fi-icl-y fi-icl-guc fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_6446 -> Patchwork_13593 CI_DRM_6446: 835fbe24abe47946fc514871f5cbe334d0be9854 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5092: 2a66ae6626d5583240509f84117d1345a799b75a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_13593: a537b92522385cda1cfb1400f1c9d29f11cb3b6b @ git://anongit.freedesktop.org/gfx-ci/linux == Kernel 32bit build == Warning: Kernel 32bit buildtest failed: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13593/build_32bit.log CALL scripts/checksyscalls.sh CALL scripts/atomic/check-atomics.sh CHK include/generated/compile.h Kernel: arch/x86/boot/bzImage is ready (#1) Building modules, stage 2. MODPOST 112 modules ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! scripts/Makefile.modpost:91: recipe for target '__modpost' failed make[1]: *** [__modpost] Error 1 Makefile:1287: recipe for target 'modules' failed make: *** [modules] Error 2 == Linux commits == a537b9252238 drm/i915/display/tgl: Bump up the plane/fb height to support 8K ed957eb65698 drm/i915/display/tgl: Bump up the mode vertical limits to support 8K == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13593/ _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 16+ messages in thread
* ✓ Fi.CI.IGT: success for series starting with [v2] drm/i915/display/tgl: Bump up the mode vertical limits to support 8K (rev2) 2019-07-09 21:47 [PATCH 1/2] drm/i915/display/tgl: Bump up the mode vertical limits to support 8K Manasi Navare ` (5 preceding siblings ...) 2019-07-10 0:40 ` ✓ Fi.CI.BAT: success for series starting with [v2] drm/i915/display/tgl: Bump up the mode vertical limits to support 8K (rev2) Patchwork @ 2019-07-11 9:07 ` Patchwork 6 siblings, 0 replies; 16+ messages in thread From: Patchwork @ 2019-07-11 9:07 UTC (permalink / raw) To: Manasi Navare; +Cc: intel-gfx == Series Details == Series: series starting with [v2] drm/i915/display/tgl: Bump up the mode vertical limits to support 8K (rev2) URL : https://patchwork.freedesktop.org/series/63458/ State : success == Summary == CI Bug Log - changes from CI_DRM_6446_full -> Patchwork_13593_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_13593_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@i915_suspend@fence-restore-tiled2untiled: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([fdo#108566]) +4 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/shard-apl7/igt@i915_suspend@fence-restore-tiled2untiled.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13593/shard-apl7/igt@i915_suspend@fence-restore-tiled2untiled.html * igt@kms_busy@basic-modeset-a: - shard-iclb: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/shard-iclb6/igt@kms_busy@basic-modeset-a.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13593/shard-iclb1/igt@kms_busy@basic-modeset-a.html * igt@kms_color@pipe-b-ctm-red-to-blue: - shard-skl: [PASS][5] -> [FAIL][6] ([fdo#107201]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/shard-skl1/igt@kms_color@pipe-b-ctm-red-to-blue.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13593/shard-skl5/igt@kms_color@pipe-b-ctm-red-to-blue.html * igt@kms_cursor_legacy@short-flip-before-cursor-toggle: - shard-snb: [PASS][7] -> [SKIP][8] ([fdo#109271]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/shard-snb5/igt@kms_cursor_legacy@short-flip-before-cursor-toggle.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13593/shard-snb2/igt@kms_cursor_legacy@short-flip-before-cursor-toggle.html * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: [PASS][9] -> [FAIL][10] ([fdo#105363]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/shard-skl6/igt@kms_flip@flip-vs-expired-vblank.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13593/shard-skl8/igt@kms_flip@flip-vs-expired-vblank.html * igt@kms_flip_tiling@flip-changes-tiling-yf: - shard-skl: [PASS][11] -> [FAIL][12] ([fdo#108228] / [fdo#108303]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/shard-skl3/igt@kms_flip_tiling@flip-changes-tiling-yf.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13593/shard-skl3/igt@kms_flip_tiling@flip-changes-tiling-yf.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu: - shard-iclb: [PASS][13] -> [FAIL][14] ([fdo#103167]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13593/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu.html * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min: - shard-skl: [PASS][15] -> [FAIL][16] ([fdo#108145]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/shard-skl1/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13593/shard-skl5/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html * igt@kms_psr@psr2_suspend: - shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#109441]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/shard-iclb2/igt@kms_psr@psr2_suspend.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13593/shard-iclb3/igt@kms_psr@psr2_suspend.html * igt@kms_setmode@basic: - shard-kbl: [PASS][19] -> [FAIL][20] ([fdo#99912]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/shard-kbl1/igt@kms_setmode@basic.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13593/shard-kbl6/igt@kms_setmode@basic.html #### Possible fixes #### * igt@i915_pm_rpm@debugfs-read: - shard-skl: [INCOMPLETE][21] ([fdo#107807]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/shard-skl5/igt@i915_pm_rpm@debugfs-read.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13593/shard-skl3/igt@i915_pm_rpm@debugfs-read.html * igt@kms_cursor_crc@pipe-a-cursor-128x42-random: - shard-apl: [INCOMPLETE][23] ([fdo#103927]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/shard-apl7/igt@kms_cursor_crc@pipe-a-cursor-128x42-random.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13593/shard-apl5/igt@kms_cursor_crc@pipe-a-cursor-128x42-random.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-apl: [DMESG-WARN][25] ([fdo#108566]) -> [PASS][26] +4 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13593/shard-apl3/igt@kms_flip@flip-vs-suspend-interruptible.html * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite: - shard-iclb: [FAIL][27] ([fdo#103167]) -> [PASS][28] +3 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13593/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html * igt@kms_psr@no_drrs: - shard-iclb: [FAIL][29] ([fdo#108341]) -> [PASS][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/shard-iclb1/igt@kms_psr@no_drrs.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13593/shard-iclb3/igt@kms_psr@no_drrs.html * igt@kms_psr@psr2_sprite_mmap_gtt: - shard-iclb: [SKIP][31] ([fdo#109441]) -> [PASS][32] +4 similar issues [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/shard-iclb3/igt@kms_psr@psr2_sprite_mmap_gtt.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13593/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html * igt@kms_setmode@basic: - shard-apl: [FAIL][33] ([fdo#99912]) -> [PASS][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/shard-apl8/igt@kms_setmode@basic.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13593/shard-apl5/igt@kms_setmode@basic.html [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363 [fdo#107201]: https://bugs.freedesktop.org/show_bug.cgi?id=107201 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#108228]: https://bugs.freedesktop.org/show_bug.cgi?id=108228 [fdo#108303]: https://bugs.freedesktop.org/show_bug.cgi?id=108303 [fdo#108341]: https://bugs.freedesktop.org/show_bug.cgi?id=108341 [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912 Participating hosts (10 -> 10) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_6446 -> Patchwork_13593 CI_DRM_6446: 835fbe24abe47946fc514871f5cbe334d0be9854 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5092: 2a66ae6626d5583240509f84117d1345a799b75a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_13593: a537b92522385cda1cfb1400f1c9d29f11cb3b6b @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13593/ _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2019-07-11 9:07 UTC | newest] Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-07-09 21:47 [PATCH 1/2] drm/i915/display/tgl: Bump up the mode vertical limits to support 8K Manasi Navare 2019-07-09 21:47 ` [PATCH 2/2] drm/i915/display/tgl: Bump up the plane/fb height " Manasi Navare 2019-07-09 23:07 ` Souza, Jose 2019-07-10 18:57 ` Manasi Navare 2019-07-10 19:18 ` Ville Syrjälä 2019-07-10 19:36 ` Manasi Navare 2019-07-09 22:07 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/display/tgl: Bump up the mode vertical limits " Patchwork 2019-07-09 22:49 ` ✓ Fi.CI.BAT: success " Patchwork 2019-07-09 23:04 ` [PATCH 1/2] " Souza, Jose 2019-07-10 18:57 ` Manasi Navare 2019-07-10 0:06 ` [PATCH v2] " Manasi Navare 2019-07-10 19:15 ` Ville Syrjälä 2019-07-10 19:24 ` Manasi Navare 2019-07-10 19:30 ` Ville Syrjälä 2019-07-10 0:40 ` ✓ Fi.CI.BAT: success for series starting with [v2] drm/i915/display/tgl: Bump up the mode vertical limits to support 8K (rev2) Patchwork 2019-07-11 9:07 ` ✓ Fi.CI.IGT: " Patchwork
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