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From: Lucas De Marchi <lucas.demarchi@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH v3 19/21] drm/i915/tgl: Add vbt value mapping for DDC Bus pin
Date: Thu, 11 Jul 2019 10:31:13 -0700	[thread overview]
Message-ID: <20190711173115.28296-20-lucas.demarchi@intel.com> (raw)
In-Reply-To: <20190711173115.28296-1-lucas.demarchi@intel.com>

From: Mahesh Kumar <mahesh1.kumar@intel.com>

Add VBT-value to DDC bus pin mapping for the same.

Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bios.c     | 17 ++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_vbt_defs.h |  3 +++
 2 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 4fdbb5c35d87..2fe68f72b88f 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1355,12 +1355,27 @@ static const u8 mcc_ddc_pin_map[] = {
 	[MCC_DDC_BUS_DDI_C] = GMBUS_PIN_9_TC1_ICP,
 };
 
+static const u8 tgp_ddc_pin_map[] = {
+	[ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT,
+	[ICL_DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT,
+	[TGL_DDC_BUS_DDI_C] = GMBUS_PIN_3_BXT,
+	[ICL_DDC_BUS_PORT_1] = GMBUS_PIN_9_TC1_ICP,
+	[ICL_DDC_BUS_PORT_2] = GMBUS_PIN_10_TC2_ICP,
+	[ICL_DDC_BUS_PORT_3] = GMBUS_PIN_11_TC3_ICP,
+	[ICL_DDC_BUS_PORT_4] = GMBUS_PIN_12_TC4_ICP,
+	[TGL_DDC_BUS_PORT_5] = GMBUS_PIN_13_TC5_TGP,
+	[TGL_DDC_BUS_PORT_6] = GMBUS_PIN_14_TC6_TGP,
+};
+
 static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
 {
 	const u8 *ddc_pin_map;
 	int n_entries;
 
-	if (HAS_PCH_MCC(dev_priv)) {
+	if (HAS_PCH_TGP(dev_priv)) {
+		ddc_pin_map = tgp_ddc_pin_map;
+		n_entries = ARRAY_SIZE(tgp_ddc_pin_map);
+	} else if (HAS_PCH_MCC(dev_priv)) {
 		ddc_pin_map = mcc_ddc_pin_map;
 		n_entries = ARRAY_SIZE(mcc_ddc_pin_map);
 	} else if (HAS_PCH_ICP(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 2f4894e9a03d..93f5c9d204d6 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -310,10 +310,13 @@ enum vbt_gmbus_ddi {
 	DDC_BUS_DDI_F,
 	ICL_DDC_BUS_DDI_A = 0x1,
 	ICL_DDC_BUS_DDI_B,
+	TGL_DDC_BUS_DDI_C,
 	ICL_DDC_BUS_PORT_1 = 0x4,
 	ICL_DDC_BUS_PORT_2,
 	ICL_DDC_BUS_PORT_3,
 	ICL_DDC_BUS_PORT_4,
+	TGL_DDC_BUS_PORT_5,
+	TGL_DDC_BUS_PORT_6,
 	MCC_DDC_BUS_DDI_A = 0x1,
 	MCC_DDC_BUS_DDI_B,
 	MCC_DDC_BUS_DDI_C = 0x4,
-- 
2.21.0

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  parent reply	other threads:[~2019-07-11 17:55 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-11 17:30 [PATCH v3 00/21] Initial support for Tiger Lake Lucas De Marchi
2019-07-11 17:30 ` [PATCH v3 01/21] drm/i915: Add 4th pipe and transcoder Lucas De Marchi
2019-07-11 17:30 ` [PATCH v3 02/21] drm/i915/tgl: add initial Tiger Lake definitions Lucas De Marchi
2019-07-11 17:30 ` [PATCH v3 03/21] drm/i915/tgl: Introduce Tiger Lake PCH Lucas De Marchi
2019-07-11 17:30 ` [PATCH v3 04/21] drm/i915/tgl: Add TGL PCH detection in virtualized environment Lucas De Marchi
2019-07-11 17:30 ` [PATCH v3 05/21] drm/i915/tgl: Add TGL PCI IDs Lucas De Marchi
2019-07-11 17:31 ` [PATCH v3 06/21] drm/i915/tgl: Check if pipe D is fused Lucas De Marchi
2019-07-11 17:31 ` [PATCH v3 07/21] drm/i915/tgl: rename TRANSCODER_EDP_VDSC to use on transcoder A Lucas De Marchi
2019-07-11 21:24   ` Manasi Navare
2019-07-11 17:31 ` [PATCH v3 08/21] drm/i915/tgl: Add power well support Lucas De Marchi
2019-07-11 17:31 ` [PATCH v3 09/21] drm/i915/tgl: Add power well to support 4th pipe Lucas De Marchi
2019-07-11 17:31 ` [PATCH v3 10/21] drm/i915/tgl: Add new pll ids Lucas De Marchi
2019-07-11 17:31 ` [PATCH v3 11/21] drm/i915/tgl: Add pll manager Lucas De Marchi
2019-07-11 17:31 ` [PATCH v3 12/21] drm/i915/tgl: Add additional ports for Tiger Lake Lucas De Marchi
2019-07-11 20:47   ` Matt Roper
2019-07-11 17:31 ` [PATCH v3 13/21] drm/i915/tgl: Add additional PHYs " Lucas De Marchi
2019-07-11 20:49   ` Matt Roper
2019-07-11 17:31 ` [PATCH v3 14/21] drm/i915/tgl: init ddi port A-C " Lucas De Marchi
2019-07-11 17:31 ` [PATCH v3 15/21] drm/i915/tgl: apply Display WA #1178 to fix type C dongles Lucas De Marchi
2019-07-11 20:52   ` Matt Roper
2019-07-11 21:24     ` Lucas De Marchi
2019-07-11 21:35     ` [PATCH] " Lucas De Marchi
2019-07-11 22:01       ` Matt Roper
2019-07-11 17:31 ` [PATCH v3 16/21] drm/i915/gen12: MBUS B credit change Lucas De Marchi
2019-07-11 17:31 ` [PATCH v3 17/21] drm/i915/tgl: Add gmbus gpio pin to port mapping Lucas De Marchi
2019-07-11 17:31 ` [PATCH v3 18/21] drm/i915/tgl: port to ddc pin mapping Lucas De Marchi
2019-07-11 21:09   ` Matt Roper
2019-07-11 17:31 ` Lucas De Marchi [this message]
2019-07-11 17:31 ` [PATCH v3 20/21] drm/i915/tgl: Add DPLL registers Lucas De Marchi
2019-07-11 17:31 ` [PATCH v3 21/21] drm/i915/tgl: Update DPLL clock reference register Lucas De Marchi
2019-07-11 18:31 ` ✗ Fi.CI.CHECKPATCH: warning for Initial support for Tiger Lake (rev7) Patchwork
2019-07-11 20:20 ` ✓ Fi.CI.BAT: success " Patchwork
2019-07-11 22:31 ` ✗ Fi.CI.CHECKPATCH: warning for Initial support for Tiger Lake (rev8) Patchwork
2019-07-11 22:50 ` ✓ Fi.CI.BAT: success " Patchwork

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