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From: Lucas De Marchi <lucas.demarchi@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH v3 06/21] drm/i915/tgl: Check if pipe D is fused
Date: Thu, 11 Jul 2019 10:31:00 -0700	[thread overview]
Message-ID: <20190711173115.28296-7-lucas.demarchi@intel.com> (raw)
In-Reply-To: <20190711173115.28296-1-lucas.demarchi@intel.com>

From: José Roberto de Souza <jose.souza@intel.com>

On Tiger Lake there is one more pipe - check if it's fused.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 1 +
 drivers/gpu/drm/i915/intel_device_info.c | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6fe3d74f99ff..94e76fa9d114 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7633,6 +7633,7 @@ enum {
 #define SKL_DFSM_PIPE_A_DISABLE		(1 << 30)
 #define SKL_DFSM_PIPE_B_DISABLE		(1 << 21)
 #define SKL_DFSM_PIPE_C_DISABLE		(1 << 28)
+#define TGL_DFSM_PIPE_D_DISABLE		(1 << 22)
 
 #define SKL_DSSM				_MMIO(0x51004)
 #define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz		(1 << 31)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index e0d9a7a37994..f99c9fd497b2 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -938,6 +938,9 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 			enabled_mask &= ~BIT(PIPE_B);
 		if (dfsm & SKL_DFSM_PIPE_C_DISABLE)
 			enabled_mask &= ~BIT(PIPE_C);
+		if (INTEL_GEN(dev_priv) >= 12 &&
+		    (dfsm & TGL_DFSM_PIPE_D_DISABLE))
+			enabled_mask &= ~BIT(PIPE_D);
 
 		/*
 		 * At least one pipe should be enabled and if there are
-- 
2.21.0

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  parent reply	other threads:[~2019-07-11 17:55 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-11 17:30 [PATCH v3 00/21] Initial support for Tiger Lake Lucas De Marchi
2019-07-11 17:30 ` [PATCH v3 01/21] drm/i915: Add 4th pipe and transcoder Lucas De Marchi
2019-07-11 17:30 ` [PATCH v3 02/21] drm/i915/tgl: add initial Tiger Lake definitions Lucas De Marchi
2019-07-11 17:30 ` [PATCH v3 03/21] drm/i915/tgl: Introduce Tiger Lake PCH Lucas De Marchi
2019-07-11 17:30 ` [PATCH v3 04/21] drm/i915/tgl: Add TGL PCH detection in virtualized environment Lucas De Marchi
2019-07-11 17:30 ` [PATCH v3 05/21] drm/i915/tgl: Add TGL PCI IDs Lucas De Marchi
2019-07-11 17:31 ` Lucas De Marchi [this message]
2019-07-11 17:31 ` [PATCH v3 07/21] drm/i915/tgl: rename TRANSCODER_EDP_VDSC to use on transcoder A Lucas De Marchi
2019-07-11 21:24   ` Manasi Navare
2019-07-11 17:31 ` [PATCH v3 08/21] drm/i915/tgl: Add power well support Lucas De Marchi
2019-07-11 17:31 ` [PATCH v3 09/21] drm/i915/tgl: Add power well to support 4th pipe Lucas De Marchi
2019-07-11 17:31 ` [PATCH v3 10/21] drm/i915/tgl: Add new pll ids Lucas De Marchi
2019-07-11 17:31 ` [PATCH v3 11/21] drm/i915/tgl: Add pll manager Lucas De Marchi
2019-07-11 17:31 ` [PATCH v3 12/21] drm/i915/tgl: Add additional ports for Tiger Lake Lucas De Marchi
2019-07-11 20:47   ` Matt Roper
2019-07-11 17:31 ` [PATCH v3 13/21] drm/i915/tgl: Add additional PHYs " Lucas De Marchi
2019-07-11 20:49   ` Matt Roper
2019-07-11 17:31 ` [PATCH v3 14/21] drm/i915/tgl: init ddi port A-C " Lucas De Marchi
2019-07-11 17:31 ` [PATCH v3 15/21] drm/i915/tgl: apply Display WA #1178 to fix type C dongles Lucas De Marchi
2019-07-11 20:52   ` Matt Roper
2019-07-11 21:24     ` Lucas De Marchi
2019-07-11 21:35     ` [PATCH] " Lucas De Marchi
2019-07-11 22:01       ` Matt Roper
2019-07-11 17:31 ` [PATCH v3 16/21] drm/i915/gen12: MBUS B credit change Lucas De Marchi
2019-07-11 17:31 ` [PATCH v3 17/21] drm/i915/tgl: Add gmbus gpio pin to port mapping Lucas De Marchi
2019-07-11 17:31 ` [PATCH v3 18/21] drm/i915/tgl: port to ddc pin mapping Lucas De Marchi
2019-07-11 21:09   ` Matt Roper
2019-07-11 17:31 ` [PATCH v3 19/21] drm/i915/tgl: Add vbt value mapping for DDC Bus pin Lucas De Marchi
2019-07-11 17:31 ` [PATCH v3 20/21] drm/i915/tgl: Add DPLL registers Lucas De Marchi
2019-07-11 17:31 ` [PATCH v3 21/21] drm/i915/tgl: Update DPLL clock reference register Lucas De Marchi
2019-07-11 18:31 ` ✗ Fi.CI.CHECKPATCH: warning for Initial support for Tiger Lake (rev7) Patchwork
2019-07-11 20:20 ` ✓ Fi.CI.BAT: success " Patchwork
2019-07-11 22:31 ` ✗ Fi.CI.CHECKPATCH: warning for Initial support for Tiger Lake (rev8) Patchwork
2019-07-11 22:50 ` ✓ Fi.CI.BAT: success " Patchwork

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