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From: Matt Roper <matthew.d.roper@intel.com>
To: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v3 13/21] drm/i915/tgl: Add additional PHYs for Tiger Lake
Date: Thu, 11 Jul 2019 13:49:15 -0700	[thread overview]
Message-ID: <20190711204915.GJ9024@mdroper-desk.amr.corp.intel.com> (raw)
In-Reply-To: <20190711173115.28296-14-lucas.demarchi@intel.com>

On Thu, Jul 11, 2019 at 10:31:07AM -0700, Lucas De Marchi wrote:
> Tiger Lake has up to 3 combo phys and 6 TC phys. Extend the helper
> conversion functions from port to phy.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 5 ++++-
>  drivers/gpu/drm/i915/display/intel_display.h | 3 +++
>  2 files changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 1d6dc73dfc81..ba48fedd685b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6676,7 +6676,7 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
>  	if (phy == PHY_NONE)
>  		return false;
>  
> -	if (IS_ELKHARTLAKE(dev_priv))
> +	if (IS_ELKHARTLAKE(dev_priv) || INTEL_GEN(dev_priv) >= 12)
>  		return phy <= PHY_C;
>  
>  	if (INTEL_GEN(dev_priv) >= 11)
> @@ -6687,6 +6687,9 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
>  
>  bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
>  {
> +	if (INTEL_GEN(dev_priv) >= 12)
> +		return phy >= PHY_D && phy <= PHY_I;
> +
>  	if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
>  		return phy >= PHY_C && phy <= PHY_F;
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index 72ce27079a56..92931dc26470 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -249,6 +249,9 @@ enum phy {
>  	PHY_D,
>  	PHY_E,
>  	PHY_F,
> +	PHY_G,
> +	PHY_H,
> +	PHY_I,
>  
>  	I915_MAX_PHYS
>  };
> -- 
> 2.21.0
> 

-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2019-07-11 20:49 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-11 17:30 [PATCH v3 00/21] Initial support for Tiger Lake Lucas De Marchi
2019-07-11 17:30 ` [PATCH v3 01/21] drm/i915: Add 4th pipe and transcoder Lucas De Marchi
2019-07-11 17:30 ` [PATCH v3 02/21] drm/i915/tgl: add initial Tiger Lake definitions Lucas De Marchi
2019-07-11 17:30 ` [PATCH v3 03/21] drm/i915/tgl: Introduce Tiger Lake PCH Lucas De Marchi
2019-07-11 17:30 ` [PATCH v3 04/21] drm/i915/tgl: Add TGL PCH detection in virtualized environment Lucas De Marchi
2019-07-11 17:30 ` [PATCH v3 05/21] drm/i915/tgl: Add TGL PCI IDs Lucas De Marchi
2019-07-11 17:31 ` [PATCH v3 06/21] drm/i915/tgl: Check if pipe D is fused Lucas De Marchi
2019-07-11 17:31 ` [PATCH v3 07/21] drm/i915/tgl: rename TRANSCODER_EDP_VDSC to use on transcoder A Lucas De Marchi
2019-07-11 21:24   ` Manasi Navare
2019-07-11 17:31 ` [PATCH v3 08/21] drm/i915/tgl: Add power well support Lucas De Marchi
2019-07-11 17:31 ` [PATCH v3 09/21] drm/i915/tgl: Add power well to support 4th pipe Lucas De Marchi
2019-07-11 17:31 ` [PATCH v3 10/21] drm/i915/tgl: Add new pll ids Lucas De Marchi
2019-07-11 17:31 ` [PATCH v3 11/21] drm/i915/tgl: Add pll manager Lucas De Marchi
2019-07-11 17:31 ` [PATCH v3 12/21] drm/i915/tgl: Add additional ports for Tiger Lake Lucas De Marchi
2019-07-11 20:47   ` Matt Roper
2019-07-11 17:31 ` [PATCH v3 13/21] drm/i915/tgl: Add additional PHYs " Lucas De Marchi
2019-07-11 20:49   ` Matt Roper [this message]
2019-07-11 17:31 ` [PATCH v3 14/21] drm/i915/tgl: init ddi port A-C " Lucas De Marchi
2019-07-11 17:31 ` [PATCH v3 15/21] drm/i915/tgl: apply Display WA #1178 to fix type C dongles Lucas De Marchi
2019-07-11 20:52   ` Matt Roper
2019-07-11 21:24     ` Lucas De Marchi
2019-07-11 21:35     ` [PATCH] " Lucas De Marchi
2019-07-11 22:01       ` Matt Roper
2019-07-11 17:31 ` [PATCH v3 16/21] drm/i915/gen12: MBUS B credit change Lucas De Marchi
2019-07-11 17:31 ` [PATCH v3 17/21] drm/i915/tgl: Add gmbus gpio pin to port mapping Lucas De Marchi
2019-07-11 17:31 ` [PATCH v3 18/21] drm/i915/tgl: port to ddc pin mapping Lucas De Marchi
2019-07-11 21:09   ` Matt Roper
2019-07-11 17:31 ` [PATCH v3 19/21] drm/i915/tgl: Add vbt value mapping for DDC Bus pin Lucas De Marchi
2019-07-11 17:31 ` [PATCH v3 20/21] drm/i915/tgl: Add DPLL registers Lucas De Marchi
2019-07-11 17:31 ` [PATCH v3 21/21] drm/i915/tgl: Update DPLL clock reference register Lucas De Marchi
2019-07-11 18:31 ` ✗ Fi.CI.CHECKPATCH: warning for Initial support for Tiger Lake (rev7) Patchwork
2019-07-11 20:20 ` ✓ Fi.CI.BAT: success " Patchwork
2019-07-11 22:31 ` ✗ Fi.CI.CHECKPATCH: warning for Initial support for Tiger Lake (rev8) Patchwork
2019-07-11 22:50 ` ✓ Fi.CI.BAT: success " Patchwork

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