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From: Matt Roper <matthew.d.roper@intel.com>
To: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v3 12/21] drm/i915/tgl: Add additional ports for Tiger Lake
Date: Thu, 11 Jul 2019 13:47:37 -0700	[thread overview]
Message-ID: <20190711204737.GI9024@mdroper-desk.amr.corp.intel.com> (raw)
In-Reply-To: <20190711173115.28296-13-lucas.demarchi@intel.com>

On Thu, Jul 11, 2019 at 10:31:06AM -0700, Lucas De Marchi wrote:
> From: Vandita Kulkarni <vandita.kulkarni@intel.com>
> 
> There are 2 new additional typeC ports in Tiger Lake and PORT-C is now a
> combophy port. This results in 6 typeC ports and 3 combophy ports.
> These 6 TC ports can be DP alternate mode, DP over thunderbolt, native
> DP on legacy DP connector or native HDMI on legacy connector.
> 
> v2: Rebase on new modular FIA code (Lucas)
> v3: Also add new port in port_identifier(), even though it can't
>     possibly be used there (requested by José)
> v4: Add conversion port->tc_port in helper function after introction of
>     phy namespace (Lucas)
> 
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Looks correct to me.

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c     | 12 ++++++++++++
>  drivers/gpu/drm/i915/display/intel_display.c |  3 +++
>  drivers/gpu/drm/i915/display/intel_display.h |  8 ++++++++
>  include/drm/i915_component.h                 |  2 +-
>  include/drm/i915_drm.h                       |  3 +++
>  5 files changed, 27 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 1662e5c2be1c..8445244aa593 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4286,6 +4286,18 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
>  		intel_dig_port->ddi_io_power_domain =
>  			POWER_DOMAIN_PORT_DDI_F_IO;
>  		break;
> +	case PORT_G:
> +		intel_dig_port->ddi_io_power_domain =
> +			POWER_DOMAIN_PORT_DDI_G_IO;
> +		break;
> +	case PORT_H:
> +		intel_dig_port->ddi_io_power_domain =
> +			POWER_DOMAIN_PORT_DDI_H_IO;
> +		break;
> +	case PORT_I:
> +		intel_dig_port->ddi_io_power_domain =
> +			POWER_DOMAIN_PORT_DDI_I_IO;
> +		break;
>  	default:
>  		MISSING_CASE(port);
>  	}
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index d6ba15c59746..1d6dc73dfc81 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6706,6 +6706,9 @@ enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
>  	if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
>  		return PORT_TC_NONE;
>  
> +	if (INTEL_GEN(dev_priv) >= 12)
> +		return port - PORT_D;
> +
>  	return port - PORT_C;
>  }
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index 1f75b0a627fd..72ce27079a56 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -177,6 +177,12 @@ static inline const char *port_identifier(enum port port)
>  		return "Port E";
>  	case PORT_F:
>  		return "Port F";
> +	case PORT_G:
> +		return "Port G";
> +	case PORT_H:
> +		return "Port H";
> +	case PORT_I:
> +		return "Port I";
>  	default:
>  		return "<invalid>";
>  	}
> @@ -189,6 +195,8 @@ enum tc_port {
>  	PORT_TC2,
>  	PORT_TC3,
>  	PORT_TC4,
> +	PORT_TC5,
> +	PORT_TC6,
>  
>  	I915_MAX_TC_PORTS
>  };
> diff --git a/include/drm/i915_component.h b/include/drm/i915_component.h
> index dcb95bd9dee6..55c3b123581b 100644
> --- a/include/drm/i915_component.h
> +++ b/include/drm/i915_component.h
> @@ -34,7 +34,7 @@ enum i915_component_type {
>  /* MAX_PORT is the number of port
>   * It must be sync with I915_MAX_PORTS defined i915_drv.h
>   */
> -#define MAX_PORTS 6
> +#define MAX_PORTS 9
>  
>  /**
>   * struct i915_audio_component - Used for direct communication between i915 and hda drivers
> diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
> index 7523e9a7b6e2..eb30062359d1 100644
> --- a/include/drm/i915_drm.h
> +++ b/include/drm/i915_drm.h
> @@ -109,6 +109,9 @@ enum port {
>  	PORT_D,
>  	PORT_E,
>  	PORT_F,
> +	PORT_G,
> +	PORT_H,
> +	PORT_I,
>  
>  	I915_MAX_PORTS
>  };
> -- 
> 2.21.0
> 

-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2019-07-11 20:47 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-11 17:30 [PATCH v3 00/21] Initial support for Tiger Lake Lucas De Marchi
2019-07-11 17:30 ` [PATCH v3 01/21] drm/i915: Add 4th pipe and transcoder Lucas De Marchi
2019-07-11 17:30 ` [PATCH v3 02/21] drm/i915/tgl: add initial Tiger Lake definitions Lucas De Marchi
2019-07-11 17:30 ` [PATCH v3 03/21] drm/i915/tgl: Introduce Tiger Lake PCH Lucas De Marchi
2019-07-11 17:30 ` [PATCH v3 04/21] drm/i915/tgl: Add TGL PCH detection in virtualized environment Lucas De Marchi
2019-07-11 17:30 ` [PATCH v3 05/21] drm/i915/tgl: Add TGL PCI IDs Lucas De Marchi
2019-07-11 17:31 ` [PATCH v3 06/21] drm/i915/tgl: Check if pipe D is fused Lucas De Marchi
2019-07-11 17:31 ` [PATCH v3 07/21] drm/i915/tgl: rename TRANSCODER_EDP_VDSC to use on transcoder A Lucas De Marchi
2019-07-11 21:24   ` Manasi Navare
2019-07-11 17:31 ` [PATCH v3 08/21] drm/i915/tgl: Add power well support Lucas De Marchi
2019-07-11 17:31 ` [PATCH v3 09/21] drm/i915/tgl: Add power well to support 4th pipe Lucas De Marchi
2019-07-11 17:31 ` [PATCH v3 10/21] drm/i915/tgl: Add new pll ids Lucas De Marchi
2019-07-11 17:31 ` [PATCH v3 11/21] drm/i915/tgl: Add pll manager Lucas De Marchi
2019-07-11 17:31 ` [PATCH v3 12/21] drm/i915/tgl: Add additional ports for Tiger Lake Lucas De Marchi
2019-07-11 20:47   ` Matt Roper [this message]
2019-07-11 17:31 ` [PATCH v3 13/21] drm/i915/tgl: Add additional PHYs " Lucas De Marchi
2019-07-11 20:49   ` Matt Roper
2019-07-11 17:31 ` [PATCH v3 14/21] drm/i915/tgl: init ddi port A-C " Lucas De Marchi
2019-07-11 17:31 ` [PATCH v3 15/21] drm/i915/tgl: apply Display WA #1178 to fix type C dongles Lucas De Marchi
2019-07-11 20:52   ` Matt Roper
2019-07-11 21:24     ` Lucas De Marchi
2019-07-11 21:35     ` [PATCH] " Lucas De Marchi
2019-07-11 22:01       ` Matt Roper
2019-07-11 17:31 ` [PATCH v3 16/21] drm/i915/gen12: MBUS B credit change Lucas De Marchi
2019-07-11 17:31 ` [PATCH v3 17/21] drm/i915/tgl: Add gmbus gpio pin to port mapping Lucas De Marchi
2019-07-11 17:31 ` [PATCH v3 18/21] drm/i915/tgl: port to ddc pin mapping Lucas De Marchi
2019-07-11 21:09   ` Matt Roper
2019-07-11 17:31 ` [PATCH v3 19/21] drm/i915/tgl: Add vbt value mapping for DDC Bus pin Lucas De Marchi
2019-07-11 17:31 ` [PATCH v3 20/21] drm/i915/tgl: Add DPLL registers Lucas De Marchi
2019-07-11 17:31 ` [PATCH v3 21/21] drm/i915/tgl: Update DPLL clock reference register Lucas De Marchi
2019-07-11 18:31 ` ✗ Fi.CI.CHECKPATCH: warning for Initial support for Tiger Lake (rev7) Patchwork
2019-07-11 20:20 ` ✓ Fi.CI.BAT: success " Patchwork
2019-07-11 22:31 ` ✗ Fi.CI.CHECKPATCH: warning for Initial support for Tiger Lake (rev8) Patchwork
2019-07-11 22:50 ` ✓ Fi.CI.BAT: success " Patchwork

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