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From: Segher Boessenkool <segher@kernel.crashing.org>
To: Arnd Bergmann <arnd@arndb.de>
Cc: Nathan Chancellor <natechancellor@gmail.com>,
	Nick Desaulniers <ndesaulniers@google.com>,
	Michael Ellerman <mpe@ellerman.id.au>,
	christophe leroy <christophe.leroy@c-s.fr>,
	kbuild test robot <lkp@intel.com>,
	Benjamin Herrenschmidt <benh@kernel.crashing.org>,
	Paul Mackerras <paulus@samba.org>,
	linuxppc-dev <linuxppc-dev@lists.ozlabs.org>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	clang-built-linux <clang-built-linux@googlegroups.com>
Subject: Re: [PATCH] powerpc: workaround clang codegen bug in dcbz
Date: Tue, 30 Jul 2019 14:35:02 -0500	[thread overview]
Message-ID: <20190730193502.GR31406@gate.crashing.org> (raw)
In-Reply-To: <CAK8P3a0_ovcX9tOo1UQ3_1UmM=+A2X=yErw27i2pHOj4XD40-A@mail.gmail.com>

On Tue, Jul 30, 2019 at 08:24:14PM +0200, Arnd Bergmann wrote:
> On Tue, Jul 30, 2019 at 6:16 PM Segher Boessenkool
> <segher@kernel.crashing.org> wrote:
> > in_le32 and friends?  Yeah, huh.  If LLVM copies that to the stack as
> > well, its (not byte reversing) read will be atomic just fine, so things
> > will still work correctly.
> 
> byteorder is fine, the problem I was thinking of is when moving the load/store
> instructions around the barriers that synchronize with DMA, or turning
> them into different-size accesses. Changing two consecutive 16-bit mmio reads
> into an unaligned 32-bit read will rarely have the intended effect ;-)

Most such barriers will also work on the copy accesses, I think.  But
yes it depends on exactly how it is written.  The {in,out}_{be,le}<N>
ones use sync;store for out and sync;load;trap;isync for in, so they
should be safe ;-)

(Well, almost -- writes to I/O will not necessarily actually happen
before other stores, not from these macros alone at least).

Should be pretty easy to check what LLVM makes of this?


Segher

WARNING: multiple messages have this Message-ID (diff)
From: Segher Boessenkool <segher@kernel.crashing.org>
To: Arnd Bergmann <arnd@arndb.de>
Cc: kbuild test robot <lkp@intel.com>,
	Nick Desaulniers <ndesaulniers@google.com>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	clang-built-linux <clang-built-linux@googlegroups.com>,
	Paul Mackerras <paulus@samba.org>,
	Nathan Chancellor <natechancellor@gmail.com>,
	linuxppc-dev <linuxppc-dev@lists.ozlabs.org>
Subject: Re: [PATCH] powerpc: workaround clang codegen bug in dcbz
Date: Tue, 30 Jul 2019 14:35:02 -0500	[thread overview]
Message-ID: <20190730193502.GR31406@gate.crashing.org> (raw)
In-Reply-To: <CAK8P3a0_ovcX9tOo1UQ3_1UmM=+A2X=yErw27i2pHOj4XD40-A@mail.gmail.com>

On Tue, Jul 30, 2019 at 08:24:14PM +0200, Arnd Bergmann wrote:
> On Tue, Jul 30, 2019 at 6:16 PM Segher Boessenkool
> <segher@kernel.crashing.org> wrote:
> > in_le32 and friends?  Yeah, huh.  If LLVM copies that to the stack as
> > well, its (not byte reversing) read will be atomic just fine, so things
> > will still work correctly.
> 
> byteorder is fine, the problem I was thinking of is when moving the load/store
> instructions around the barriers that synchronize with DMA, or turning
> them into different-size accesses. Changing two consecutive 16-bit mmio reads
> into an unaligned 32-bit read will rarely have the intended effect ;-)

Most such barriers will also work on the copy accesses, I think.  But
yes it depends on exactly how it is written.  The {in,out}_{be,le}<N>
ones use sync;store for out and sync;load;trap;isync for in, so they
should be safe ;-)

(Well, almost -- writes to I/O will not necessarily actually happen
before other stores, not from these macros alone at least).

Should be pretty easy to check what LLVM makes of this?


Segher

  reply	other threads:[~2019-07-30 19:35 UTC|newest]

Thread overview: 52+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-29 20:25 [PATCH] powerpc: workaround clang codegen bug in dcbz Nick Desaulniers
2019-07-29 20:25 ` Nick Desaulniers
2019-07-29 20:32 ` Nathan Chancellor
2019-07-29 20:32   ` Nathan Chancellor
2019-07-29 20:45   ` Nick Desaulniers
2019-07-29 20:45     ` Nick Desaulniers
2019-07-29 20:47     ` Nathan Chancellor
2019-07-29 20:47       ` Nathan Chancellor
2019-07-29 20:49       ` Nick Desaulniers
2019-07-29 20:49         ` Nick Desaulniers
2019-07-29 21:52   ` Segher Boessenkool
2019-07-29 21:52     ` Segher Boessenkool
2019-07-30  7:34     ` Arnd Bergmann
2019-07-30  7:34       ` Arnd Bergmann
2019-07-30 11:17       ` Michael Ellerman
2019-07-30 11:17         ` Michael Ellerman
2019-08-09 18:21         ` [PATCH] powerpc: fix inline asm constraints for dcbz Nick Desaulniers
2019-08-09 18:21           ` Nick Desaulniers
2019-08-09 18:28           ` Arnd Bergmann
2019-08-09 18:28             ` Arnd Bergmann
2019-08-09 20:03             ` Christophe Leroy
2019-08-09 20:03               ` Christophe Leroy
2019-08-09 20:12               ` Arnd Bergmann
2019-08-09 20:12                 ` Arnd Bergmann
2019-08-09 22:03                 ` Nick Desaulniers
2019-08-09 22:03                   ` Nick Desaulniers
2019-08-09 22:10                 ` Segher Boessenkool
2019-08-09 22:10                   ` Segher Boessenkool
2019-08-09 22:00               ` Segher Boessenkool
2019-08-09 22:00                 ` Segher Boessenkool
2019-08-09 22:03               ` [PATCH v3] Revert "powerpc: slightly improve cache helpers" Nick Desaulniers
2019-08-09 22:03                 ` Nick Desaulniers
2019-08-10  9:09                 ` Michael Ellerman
2019-08-10  9:09                   ` Michael Ellerman
2019-08-09 21:55             ` [PATCH] powerpc: fix inline asm constraints for dcbz Segher Boessenkool
2019-08-09 21:55               ` Segher Boessenkool
2019-08-09 20:36           ` Nathan Chancellor
2019-08-09 20:36             ` Nathan Chancellor
2019-07-30 13:48       ` [PATCH] powerpc: workaround clang codegen bug in dcbz Segher Boessenkool
2019-07-30 13:48         ` Segher Boessenkool
2019-07-30 14:30         ` Arnd Bergmann
2019-07-30 14:30           ` Arnd Bergmann
2019-07-30 16:16           ` Segher Boessenkool
2019-07-30 16:16             ` Segher Boessenkool
2019-07-30 17:07             ` Segher Boessenkool
2019-07-30 18:24               ` Arnd Bergmann
2019-07-30 18:24             ` Arnd Bergmann
2019-07-30 18:24               ` Arnd Bergmann
2019-07-30 19:35               ` Segher Boessenkool [this message]
2019-07-30 19:35                 ` Segher Boessenkool
2019-07-30  5:31   ` Christophe Leroy
2019-07-30  5:31     ` Christophe Leroy

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