* [PATCH 0/4] Initial TGL submission changes
@ 2019-07-31 0:48 Daniele Ceraolo Spurio
2019-07-31 0:48 ` [PATCH 1/4] drm/i915/tgl: add Gen12 default indirect ctx offset Daniele Ceraolo Spurio
` (6 more replies)
0 siblings, 7 replies; 14+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-07-31 0:48 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
New lrc-related defines, new csb parser and TGL sfc pairing.
There are required changes for the context image as well, I'll send them
separately as I haven't done the math for the lrc size yet.
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Daniele Ceraolo Spurio (3):
drm/i915/tgl: add Gen12 default indirect ctx offset
drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID
drm/i915/tgl: Gen12 csb support
Michel Thierry (1):
drm/i915/tgl: Report valid VDBoxes with SFC capability
drivers/gpu/drm/i915/gem/i915_gem_context.c | 4 +-
drivers/gpu/drm/i915/gt/intel_engine_types.h | 13 ++++
drivers/gpu/drm/i915/gt/intel_lrc.c | 77 ++++++++++++++++++--
drivers/gpu/drm/i915/gt/intel_lrc_reg.h | 1 +
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/intel_device_info.c | 3 +-
6 files changed, 90 insertions(+), 10 deletions(-)
--
2.22.0
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^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH 1/4] drm/i915/tgl: add Gen12 default indirect ctx offset 2019-07-31 0:48 [PATCH 0/4] Initial TGL submission changes Daniele Ceraolo Spurio @ 2019-07-31 0:48 ` Daniele Ceraolo Spurio 2019-07-31 0:49 ` [PATCH 2/4] drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID Daniele Ceraolo Spurio ` (5 subsequent siblings) 6 siblings, 0 replies; 14+ messages in thread From: Daniele Ceraolo Spurio @ 2019-07-31 0:48 UTC (permalink / raw) To: intel-gfx; +Cc: Michel Thierry, Lucas De Marchi Gen12 uses a new indirect ctx offset. Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by: Michel Thierry <michel.thierry@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> --- drivers/gpu/drm/i915/gt/intel_lrc.c | 4 ++++ drivers/gpu/drm/i915/gt/intel_lrc_reg.h | 1 + 2 files changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index d9061d9348cb..c379184ac987 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -2891,6 +2891,10 @@ static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine) default: MISSING_CASE(INTEL_GEN(engine->i915)); /* fall through */ + case 12: + indirect_ctx_offset = + GEN12_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; + break; case 11: indirect_ctx_offset = GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; diff --git a/drivers/gpu/drm/i915/gt/intel_lrc_reg.h b/drivers/gpu/drm/i915/gt/intel_lrc_reg.h index 6bf34738b4e5..b8f20ad71169 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc_reg.h +++ b/drivers/gpu/drm/i915/gt/intel_lrc_reg.h @@ -64,5 +64,6 @@ #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26 #define GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x19 #define GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x1A +#define GEN12_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0xD #endif /* _INTEL_LRC_REG_H_ */ -- 2.22.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 2/4] drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID 2019-07-31 0:48 [PATCH 0/4] Initial TGL submission changes Daniele Ceraolo Spurio 2019-07-31 0:48 ` [PATCH 1/4] drm/i915/tgl: add Gen12 default indirect ctx offset Daniele Ceraolo Spurio @ 2019-07-31 0:49 ` Daniele Ceraolo Spurio 2019-07-31 0:49 ` [PATCH 3/4] drm/i915/tgl: Gen12 csb support Daniele Ceraolo Spurio ` (4 subsequent siblings) 6 siblings, 0 replies; 14+ messages in thread From: Daniele Ceraolo Spurio @ 2019-07-31 0:49 UTC (permalink / raw) To: intel-gfx; +Cc: Lucas De Marchi Like Gen11, Gen12 has 11 available bits for the ctx id field. However, the last value (0x7FF) is reserved to indicate engine idle, so we need to reduce the maximum number of contexts by 1 compared to Gen11. Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> --- drivers/gpu/drm/i915/gem/i915_gem_context.c | 4 +++- drivers/gpu/drm/i915/i915_drv.h | 2 ++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c index b28c7ca681a8..67d76ef6a7ae 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c @@ -172,7 +172,9 @@ static inline int new_hw_id(struct drm_i915_private *i915, gfp_t gfp) lockdep_assert_held(&i915->contexts.mutex); - if (INTEL_GEN(i915) >= 11) + if (INTEL_GEN(i915) >= 12) + max = GEN12_MAX_CONTEXT_HW_ID; + else if (INTEL_GEN(i915) >= 11) max = GEN11_MAX_CONTEXT_HW_ID; else if (USES_GUC_SUBMISSION(i915)) /* diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 3eeb21ff04c2..20161f4ebd19 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1580,6 +1580,8 @@ struct drm_i915_private { #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */ #define MAX_GUC_CONTEXT_HW_ID (1 << 20) /* exclusive */ #define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */ +/* in Gen12 ID 0x7FF is reserved to indicate idle */ +#define GEN12_MAX_CONTEXT_HW_ID (GEN11_MAX_CONTEXT_HW_ID - 1) struct list_head hw_id_list; } contexts; -- 2.22.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 3/4] drm/i915/tgl: Gen12 csb support 2019-07-31 0:48 [PATCH 0/4] Initial TGL submission changes Daniele Ceraolo Spurio 2019-07-31 0:48 ` [PATCH 1/4] drm/i915/tgl: add Gen12 default indirect ctx offset Daniele Ceraolo Spurio 2019-07-31 0:49 ` [PATCH 2/4] drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID Daniele Ceraolo Spurio @ 2019-07-31 0:49 ` Daniele Ceraolo Spurio 2019-07-31 6:29 ` Tvrtko Ursulin 2019-07-31 7:33 ` Chris Wilson 2019-07-31 0:49 ` [PATCH 4/4] drm/i915/tgl: Report valid VDBoxes with SFC capability Daniele Ceraolo Spurio ` (3 subsequent siblings) 6 siblings, 2 replies; 14+ messages in thread From: Daniele Ceraolo Spurio @ 2019-07-31 0:49 UTC (permalink / raw) To: intel-gfx The CSB format has been reworked for Gen12 to include information on both the context we're switching away from and the context we're switching to. After the change, some of the events don't have their own bit anymore and need to be inferred from other values in the csb. One of the context IDs (0x7FF) has also been reserved to indicate the invalid ctx, i.e. engine idle. Note that the full context ID includes the SW counter as well, but since we currently only care if the context is valid or not we can ignore that part. Bspec: 45555, 46144 Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> --- drivers/gpu/drm/i915/gt/intel_engine_types.h | 13 ++++ drivers/gpu/drm/i915/gt/intel_lrc.c | 73 +++++++++++++++++--- 2 files changed, 78 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h index da61dd329210..98adc764d4f8 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h @@ -139,6 +139,13 @@ struct st_preempt_hang { bool inject_hang; }; +enum intel_csb_step { + CSB_NOP, + CSB_PROMOTE, + CSB_PREEMPT, + CSB_COMPLETE, +}; + /** * struct intel_engine_execlists - execlist submission queue and port state * @@ -251,6 +258,12 @@ struct intel_engine_execlists { */ u8 csb_head; + /** + * @csb_parse: platform-specific function to parse the status buffer + */ + enum intel_csb_step + (*csb_parse)(const struct intel_engine_execlists *, const u32 *csb); + I915_SELFTEST_DECLARE(struct st_preempt_hang preempt_hang;) }; diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index c379184ac987..00afdcd71bd4 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -163,6 +163,13 @@ #define CTX_DESC_FORCE_RESTORE BIT_ULL(2) +#define GEN12_CTX_STATUS_SWITCHED_TO_NEW_QUEUE (0x1) /* lower csb dword */ +#define GEN12_CTX_SWITCH_DETAIL(csb_dw) ((csb_dw) & 0xF) /* upper csb dword */ +#define GEN12_CSB_SW_CTX_ID_MASK GENMASK_ULL(25, 15) +#define GEN12_IDLE_CTX_ID 0x7FF +#define GEN12_CSB_CTX_VALID(csb_dw) \ + (FIELD_GET(GEN12_CSB_SW_CTX_ID_MASK, csb_dw) != GEN12_IDLE_CTX_ID) + /* Typical size of the average request (2 pipecontrols and a MI_BB) */ #define EXECLISTS_REQUEST_SIZE 64 /* bytes */ #define WA_TAIL_DWORDS 2 @@ -1315,14 +1322,59 @@ reset_in_progress(const struct intel_engine_execlists *execlists) return unlikely(!__tasklet_is_enabled(&execlists->tasklet)); } -enum csb_step { - CSB_NOP, - CSB_PROMOTE, - CSB_PREEMPT, - CSB_COMPLETE, -}; +/* + * Starting with Gen12, the status has a new format: + * + * bit 0: switched to new queue + * bit 1: reserved + * bit 2: semaphore wait mode (poll or signal), Only valid when + * switch detail is set to "wait on semaphore" + * bits 3-5: engine class + * bits 6-11: engine instance + * bits 12-14: reserved + * bits 15-25: sw context id of the lrc we're switching to + * bits 26-31: sw counter of the lrc we're switching to + * bits 32-35: context switch detail + * - 0: ctx complete + * - 1: wait on sync flip + * - 2: wait on vblank + * - 3: wait on scanline + * - 4: wait on semaphore + * - 5: context preempted (not on SEMAPHORE_WAIT or + * WAIT_FOR_EVENT) + * bit 36: reserved + * bits 37-43: wait detail (for switch detail 1 to 4) + * bits 44-46: reserved + * bits 47-57: sw context id of the lrc we're switching away from + * bits 58-63: sw counter of the lrc we're switching away from + */ +static enum intel_csb_step +gen12_csb_parse(const struct intel_engine_execlists *execlists, const u32 *csb) +{ + u32 lower_dw = csb[0]; + u32 upper_dw = csb[1]; + bool ctx_to_valid = GEN12_CSB_CTX_VALID(lower_dw); + bool ctx_away_valid = GEN12_CSB_CTX_VALID(upper_dw); + bool new_queue = lower_dw & GEN12_CTX_STATUS_SWITCHED_TO_NEW_QUEUE; + + if (!ctx_away_valid && ctx_to_valid) + return CSB_PROMOTE; + + if (new_queue && ctx_away_valid) + return CSB_PREEMPT; -static inline enum csb_step + /* we do not expect a ctx switch on unsuccessful wait */ + GEM_BUG_ON(GEN12_CTX_SWITCH_DETAIL(upper_dw)); + + if (*execlists->active) { + GEM_BUG_ON(!ctx_away_valid); + return CSB_COMPLETE; + } + + return CSB_NOP; +} + +static enum intel_csb_step csb_parse(const struct intel_engine_execlists *execlists, const u32 *csb) { unsigned int status = *csb; @@ -1401,7 +1453,7 @@ static void process_csb(struct intel_engine_cs *engine) engine->name, head, buf[2 * head + 0], buf[2 * head + 1]); - switch (csb_parse(execlists, buf + 2 * head)) { + switch (execlists->csb_parse(execlists, buf + 2 * head)) { case CSB_PREEMPT: /* cancel old inflight, prepare for switch */ trace_ports(execlists, "preempted", execlists->active); @@ -2878,6 +2930,11 @@ int intel_execlists_submission_init(struct intel_engine_cs *engine) else execlists->csb_size = GEN11_CSB_ENTRIES; + if (INTEL_GEN(i915) >= 12) + execlists->csb_parse = gen12_csb_parse; + else + execlists->csb_parse = csb_parse; + reset_csb_pointers(engine); return 0; -- 2.22.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH 3/4] drm/i915/tgl: Gen12 csb support 2019-07-31 0:49 ` [PATCH 3/4] drm/i915/tgl: Gen12 csb support Daniele Ceraolo Spurio @ 2019-07-31 6:29 ` Tvrtko Ursulin 2019-07-31 17:33 ` Daniele Ceraolo Spurio 2019-07-31 7:33 ` Chris Wilson 1 sibling, 1 reply; 14+ messages in thread From: Tvrtko Ursulin @ 2019-07-31 6:29 UTC (permalink / raw) To: Daniele Ceraolo Spurio, intel-gfx On 31/07/2019 01:49, Daniele Ceraolo Spurio wrote: > The CSB format has been reworked for Gen12 to include information on > both the context we're switching away from and the context we're > switching to. After the change, some of the events don't have their > own bit anymore and need to be inferred from other values in the csb. > One of the context IDs (0x7FF) has also been reserved to indicate > the invalid ctx, i.e. engine idle. > > Note that the full context ID includes the SW counter as well, but since > we currently only care if the context is valid or not we can ignore that > part. > > Bspec: 45555, 46144 > Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> > Cc: Chris Wilson <chris@chris-wilson.co.uk> > Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> > --- > drivers/gpu/drm/i915/gt/intel_engine_types.h | 13 ++++ > drivers/gpu/drm/i915/gt/intel_lrc.c | 73 +++++++++++++++++--- > 2 files changed, 78 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h > index da61dd329210..98adc764d4f8 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h > +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h > @@ -139,6 +139,13 @@ struct st_preempt_hang { > bool inject_hang; > }; > > +enum intel_csb_step { > + CSB_NOP, > + CSB_PROMOTE, > + CSB_PREEMPT, > + CSB_COMPLETE, > +}; > + > /** > * struct intel_engine_execlists - execlist submission queue and port state > * > @@ -251,6 +258,12 @@ struct intel_engine_execlists { > */ > u8 csb_head; > > + /** > + * @csb_parse: platform-specific function to parse the status buffer > + */ > + enum intel_csb_step > + (*csb_parse)(const struct intel_engine_execlists *, const u32 *csb); Nitpick - inconsistent naming and not-naming function parameters. > + > I915_SELFTEST_DECLARE(struct st_preempt_hang preempt_hang;) > }; > > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c > index c379184ac987..00afdcd71bd4 100644 > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c > @@ -163,6 +163,13 @@ > > #define CTX_DESC_FORCE_RESTORE BIT_ULL(2) > > +#define GEN12_CTX_STATUS_SWITCHED_TO_NEW_QUEUE (0x1) /* lower csb dword */ > +#define GEN12_CTX_SWITCH_DETAIL(csb_dw) ((csb_dw) & 0xF) /* upper csb dword */ > +#define GEN12_CSB_SW_CTX_ID_MASK GENMASK_ULL(25, 15) Does this need to be ULL? Seems to only been used on u32 types. Maybe it makes no practical difference... > +#define GEN12_IDLE_CTX_ID 0x7FF > +#define GEN12_CSB_CTX_VALID(csb_dw) \ > + (FIELD_GET(GEN12_CSB_SW_CTX_ID_MASK, csb_dw) != GEN12_IDLE_CTX_ID) > + > /* Typical size of the average request (2 pipecontrols and a MI_BB) */ > #define EXECLISTS_REQUEST_SIZE 64 /* bytes */ > #define WA_TAIL_DWORDS 2 > @@ -1315,14 +1322,59 @@ reset_in_progress(const struct intel_engine_execlists *execlists) > return unlikely(!__tasklet_is_enabled(&execlists->tasklet)); > } > > -enum csb_step { > - CSB_NOP, > - CSB_PROMOTE, > - CSB_PREEMPT, > - CSB_COMPLETE, > -}; > +/* > + * Starting with Gen12, the status has a new format: > + * > + * bit 0: switched to new queue > + * bit 1: reserved > + * bit 2: semaphore wait mode (poll or signal), Only valid when Nitpick - random capitalized word in a sea of non-sentences. > + * switch detail is set to "wait on semaphore" > + * bits 3-5: engine class > + * bits 6-11: engine instance > + * bits 12-14: reserved > + * bits 15-25: sw context id of the lrc we're switching to > + * bits 26-31: sw counter of the lrc we're switching to I'd perhaps drop the "we are" language from here since it is not we (driver) but represents what GPU thinks is happening. "sw context id of the lrc GPU switched to"? > + * bits 32-35: context switch detail > + * - 0: ctx complete > + * - 1: wait on sync flip > + * - 2: wait on vblank > + * - 3: wait on scanline > + * - 4: wait on semaphore > + * - 5: context preempted (not on SEMAPHORE_WAIT or > + * WAIT_FOR_EVENT) > + * bit 36: reserved > + * bits 37-43: wait detail (for switch detail 1 to 4) > + * bits 44-46: reserved > + * bits 47-57: sw context id of the lrc we're switching away from > + * bits 58-63: sw counter of the lrc we're switching away from > + */ > +static enum intel_csb_step > +gen12_csb_parse(const struct intel_engine_execlists *execlists, const u32 *csb) > +{ > + u32 lower_dw = csb[0]; > + u32 upper_dw = csb[1]; > + bool ctx_to_valid = GEN12_CSB_CTX_VALID(lower_dw); > + bool ctx_away_valid = GEN12_CSB_CTX_VALID(upper_dw); > + bool new_queue = lower_dw & GEN12_CTX_STATUS_SWITCHED_TO_NEW_QUEUE; > + > + if (!ctx_away_valid && ctx_to_valid) > + return CSB_PROMOTE; > + > + if (new_queue && ctx_away_valid) > + return CSB_PREEMPT; > > -static inline enum csb_step > + /* we do not expect a ctx switch on unsuccessful wait */ What is a wait in this context? Oh the wait ctx switch detail values. What about 5 = preempted? Guaranteed to be handled already with the "new_queue & ctx_away_valid" check? Should you add GEM_BUG_ON(GEN12_CTX_SWITCH_DETAIL(udw) != 5) on that branch? And expand the comment against this assert to explain the above? > + GEM_BUG_ON(GEN12_CTX_SWITCH_DETAIL(upper_dw)); > + > + if (*execlists->active) { > + GEM_BUG_ON(!ctx_away_valid); > + return CSB_COMPLETE; > + } > + > + return CSB_NOP; > +} > + > +static enum intel_csb_step > csb_parse(const struct intel_engine_execlists *execlists, const u32 *csb) > { > unsigned int status = *csb; > @@ -1401,7 +1453,7 @@ static void process_csb(struct intel_engine_cs *engine) > engine->name, head, > buf[2 * head + 0], buf[2 * head + 1]); > > - switch (csb_parse(execlists, buf + 2 * head)) { > + switch (execlists->csb_parse(execlists, buf + 2 * head)) { > case CSB_PREEMPT: /* cancel old inflight, prepare for switch */ > trace_ports(execlists, "preempted", execlists->active); > > @@ -2878,6 +2930,11 @@ int intel_execlists_submission_init(struct intel_engine_cs *engine) > else > execlists->csb_size = GEN11_CSB_ENTRIES; > > + if (INTEL_GEN(i915) >= 12) > + execlists->csb_parse = gen12_csb_parse; > + else > + execlists->csb_parse = csb_parse; > + > reset_csb_pointers(engine); > > return 0; > Looks simple. Do you have a reviewer who already knows how Gen12 CSB works or someone will need to read up on it to give a proper r-b? Regards, Tvrtko _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 3/4] drm/i915/tgl: Gen12 csb support 2019-07-31 6:29 ` Tvrtko Ursulin @ 2019-07-31 17:33 ` Daniele Ceraolo Spurio 0 siblings, 0 replies; 14+ messages in thread From: Daniele Ceraolo Spurio @ 2019-07-31 17:33 UTC (permalink / raw) To: Tvrtko Ursulin, intel-gfx On 7/30/19 11:29 PM, Tvrtko Ursulin wrote: > > On 31/07/2019 01:49, Daniele Ceraolo Spurio wrote: >> The CSB format has been reworked for Gen12 to include information on >> both the context we're switching away from and the context we're >> switching to. After the change, some of the events don't have their >> own bit anymore and need to be inferred from other values in the csb. >> One of the context IDs (0x7FF) has also been reserved to indicate >> the invalid ctx, i.e. engine idle. >> >> Note that the full context ID includes the SW counter as well, but since >> we currently only care if the context is valid or not we can ignore that >> part. >> >> Bspec: 45555, 46144 >> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> >> Cc: Chris Wilson <chris@chris-wilson.co.uk> >> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> >> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> >> --- >> drivers/gpu/drm/i915/gt/intel_engine_types.h | 13 ++++ >> drivers/gpu/drm/i915/gt/intel_lrc.c | 73 +++++++++++++++++--- >> 2 files changed, 78 insertions(+), 8 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h >> b/drivers/gpu/drm/i915/gt/intel_engine_types.h >> index da61dd329210..98adc764d4f8 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h >> +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h >> @@ -139,6 +139,13 @@ struct st_preempt_hang { >> bool inject_hang; >> }; >> +enum intel_csb_step { >> + CSB_NOP, >> + CSB_PROMOTE, >> + CSB_PREEMPT, >> + CSB_COMPLETE, >> +}; >> + >> /** >> * struct intel_engine_execlists - execlist submission queue and >> port state >> * >> @@ -251,6 +258,12 @@ struct intel_engine_execlists { >> */ >> u8 csb_head; >> + /** >> + * @csb_parse: platform-specific function to parse the status buffer >> + */ >> + enum intel_csb_step >> + (*csb_parse)(const struct intel_engine_execlists *, const u32 *csb); > > Nitpick - inconsistent naming and not-naming function parameters. > >> + >> I915_SELFTEST_DECLARE(struct st_preempt_hang preempt_hang;) >> }; >> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c >> b/drivers/gpu/drm/i915/gt/intel_lrc.c >> index c379184ac987..00afdcd71bd4 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c >> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c >> @@ -163,6 +163,13 @@ >> #define CTX_DESC_FORCE_RESTORE BIT_ULL(2) >> +#define GEN12_CTX_STATUS_SWITCHED_TO_NEW_QUEUE (0x1) /* lower csb >> dword */ >> +#define GEN12_CTX_SWITCH_DETAIL(csb_dw) ((csb_dw) & 0xF) /* upper >> csb dword */ >> +#define GEN12_CSB_SW_CTX_ID_MASK GENMASK_ULL(25, 15) > > Does this need to be ULL? Seems to only been used on u32 types. Maybe it > makes no practical difference... Nope, the RFC worked on the 64b status and so needed ULL, I forgot to scale it down when moving to working on the separate dwords. > >> +#define GEN12_IDLE_CTX_ID 0x7FF >> +#define GEN12_CSB_CTX_VALID(csb_dw) \ >> + (FIELD_GET(GEN12_CSB_SW_CTX_ID_MASK, csb_dw) != GEN12_IDLE_CTX_ID) >> + >> /* Typical size of the average request (2 pipecontrols and a MI_BB) */ >> #define EXECLISTS_REQUEST_SIZE 64 /* bytes */ >> #define WA_TAIL_DWORDS 2 >> @@ -1315,14 +1322,59 @@ reset_in_progress(const struct >> intel_engine_execlists *execlists) >> return unlikely(!__tasklet_is_enabled(&execlists->tasklet)); >> } >> -enum csb_step { >> - CSB_NOP, >> - CSB_PROMOTE, >> - CSB_PREEMPT, >> - CSB_COMPLETE, >> -}; >> +/* >> + * Starting with Gen12, the status has a new format: >> + * >> + * bit 0: switched to new queue >> + * bit 1: reserved >> + * bit 2: semaphore wait mode (poll or signal), Only valid when > > Nitpick - random capitalized word in a sea of non-sentences. > >> + * switch detail is set to "wait on semaphore" >> + * bits 3-5: engine class >> + * bits 6-11: engine instance >> + * bits 12-14: reserved >> + * bits 15-25: sw context id of the lrc we're switching to >> + * bits 26-31: sw counter of the lrc we're switching to > > I'd perhaps drop the "we are" language from here since it is not we > (driver) but represents what GPU thinks is happening. "sw context id of > the lrc GPU switched to"? > ack >> + * bits 32-35: context switch detail >> + * - 0: ctx complete >> + * - 1: wait on sync flip >> + * - 2: wait on vblank >> + * - 3: wait on scanline >> + * - 4: wait on semaphore >> + * - 5: context preempted (not on SEMAPHORE_WAIT or >> + * WAIT_FOR_EVENT) >> + * bit 36: reserved >> + * bits 37-43: wait detail (for switch detail 1 to 4) >> + * bits 44-46: reserved >> + * bits 47-57: sw context id of the lrc we're switching away from >> + * bits 58-63: sw counter of the lrc we're switching away from >> + */ >> +static enum intel_csb_step >> +gen12_csb_parse(const struct intel_engine_execlists *execlists, const >> u32 *csb) >> +{ >> + u32 lower_dw = csb[0]; >> + u32 upper_dw = csb[1]; >> + bool ctx_to_valid = GEN12_CSB_CTX_VALID(lower_dw); >> + bool ctx_away_valid = GEN12_CSB_CTX_VALID(upper_dw); >> + bool new_queue = lower_dw & GEN12_CTX_STATUS_SWITCHED_TO_NEW_QUEUE; >> + >> + if (!ctx_away_valid && ctx_to_valid) >> + return CSB_PROMOTE; >> + >> + if (new_queue && ctx_away_valid) >> + return CSB_PREEMPT; >> -static inline enum csb_step >> + /* we do not expect a ctx switch on unsuccessful wait */ > > What is a wait in this context? Oh the wait ctx switch detail values. This is the case where the context switches out on a WAIT_FOR_EVENT or SEMAPHORE_WAIT because the instruction has been set to switch out of the condition is not satisfied (i.e. not polling mode) > What about 5 = preempted? Guaranteed to be handled already with the > "new_queue & ctx_away_valid" check? Should you add > GEM_BUG_ON(GEN12_CTX_SWITCH_DETAIL(udw) != 5) on that branch? And expand > the comment against this assert to explain the above? > It should be guaranteed by the case above, but we can't add a BUG_ON above because when preempting a polling semaphore we get switch_detail = 4 and on a lite restore the switch_detail is undefined. >> + GEM_BUG_ON(GEN12_CTX_SWITCH_DETAIL(upper_dw)); >> + >> + if (*execlists->active) { >> + GEM_BUG_ON(!ctx_away_valid); >> + return CSB_COMPLETE; >> + } >> + >> + return CSB_NOP; >> +} >> + >> +static enum intel_csb_step >> csb_parse(const struct intel_engine_execlists *execlists, const u32 >> *csb) >> { >> unsigned int status = *csb; >> @@ -1401,7 +1453,7 @@ static void process_csb(struct intel_engine_cs >> *engine) >> engine->name, head, >> buf[2 * head + 0], buf[2 * head + 1]); >> - switch (csb_parse(execlists, buf + 2 * head)) { >> + switch (execlists->csb_parse(execlists, buf + 2 * head)) { >> case CSB_PREEMPT: /* cancel old inflight, prepare for switch */ >> trace_ports(execlists, "preempted", execlists->active); >> @@ -2878,6 +2930,11 @@ int intel_execlists_submission_init(struct >> intel_engine_cs *engine) >> else >> execlists->csb_size = GEN11_CSB_ENTRIES; >> + if (INTEL_GEN(i915) >= 12) >> + execlists->csb_parse = gen12_csb_parse; >> + else >> + execlists->csb_parse = csb_parse; >> + >> reset_csb_pointers(engine); >> return 0; >> > > Looks simple. Do you have a reviewer who already knows how Gen12 CSB > works or someone will need to read up on it to give a proper r-b? Unfortunately I need a new reviewer (Michel was the one with the knowledge). Are you volunteering? :) Daniele > > Regards, > > Tvrtko _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 3/4] drm/i915/tgl: Gen12 csb support 2019-07-31 0:49 ` [PATCH 3/4] drm/i915/tgl: Gen12 csb support Daniele Ceraolo Spurio 2019-07-31 6:29 ` Tvrtko Ursulin @ 2019-07-31 7:33 ` Chris Wilson 2019-07-31 20:18 ` Daniele Ceraolo Spurio 1 sibling, 1 reply; 14+ messages in thread From: Chris Wilson @ 2019-07-31 7:33 UTC (permalink / raw) To: Daniele Ceraolo Spurio, intel-gfx Quoting Daniele Ceraolo Spurio (2019-07-31 01:49:01) > @@ -1401,7 +1453,7 @@ static void process_csb(struct intel_engine_cs *engine) > engine->name, head, > buf[2 * head + 0], buf[2 * head + 1]); > > - switch (csb_parse(execlists, buf + 2 * head)) { > + switch (execlists->csb_parse(execlists, buf + 2 * head)) { So I worry about the cost of a retpoline here (tucked away inside an irqs-off loop), and whether a local func avoids the retpoline or if we just have to use an if-ladder. -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 3/4] drm/i915/tgl: Gen12 csb support 2019-07-31 7:33 ` Chris Wilson @ 2019-07-31 20:18 ` Daniele Ceraolo Spurio 0 siblings, 0 replies; 14+ messages in thread From: Daniele Ceraolo Spurio @ 2019-07-31 20:18 UTC (permalink / raw) To: Chris Wilson, intel-gfx On 7/31/19 12:33 AM, Chris Wilson wrote: > Quoting Daniele Ceraolo Spurio (2019-07-31 01:49:01) >> @@ -1401,7 +1453,7 @@ static void process_csb(struct intel_engine_cs *engine) >> engine->name, head, >> buf[2 * head + 0], buf[2 * head + 1]); >> >> - switch (csb_parse(execlists, buf + 2 * head)) { >> + switch (execlists->csb_parse(execlists, buf + 2 * head)) { > > So I worry about the cost of a retpoline here (tucked away inside an > irqs-off loop), and whether a local func avoids the retpoline or if we > just have to use an if-ladder. > -Chris > I've tried with: static enum intel_csb_step (*csb_parse[])(const struct intel_engine_execlists *, const u32 *) = { [CSB_GEN8] = gen8_csb_parse, [CSB_GEN12] = gen12_csb_parse, }; switch (csb_parse[execlists->csb_format](..)) But AFAICS from the objdump the assembly code generated with GCC 8.3 and CONFIG_RETPOLINE=y is more or less the same, there is just 2 extra mov instructions when using the array of functions. I can't spot the retpoline in neither case thought, so not sure if I'm missing something. Should I just go with an if-else? Daniele _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 4/4] drm/i915/tgl: Report valid VDBoxes with SFC capability 2019-07-31 0:48 [PATCH 0/4] Initial TGL submission changes Daniele Ceraolo Spurio ` (2 preceding siblings ...) 2019-07-31 0:49 ` [PATCH 3/4] drm/i915/tgl: Gen12 csb support Daniele Ceraolo Spurio @ 2019-07-31 0:49 ` Daniele Ceraolo Spurio 2019-07-31 5:59 ` Tvrtko Ursulin 2019-07-31 1:10 ` ✗ Fi.CI.CHECKPATCH: warning for Initial TGL submission changes Patchwork ` (2 subsequent siblings) 6 siblings, 1 reply; 14+ messages in thread From: Daniele Ceraolo Spurio @ 2019-07-31 0:49 UTC (permalink / raw) To: intel-gfx; +Cc: Michel Thierry, Lucas De Marchi From: Michel Thierry <michel.thierry@intel.com> In Gen11, only even numbered "logical" VDBoxes are hooked up to a SFC (Scaler & Format Converter) unit. This is not the case in Tigerlake, where each VDBox can access a SFC. We will use this information to decide when the SFC units need to be reset and also pass it to the GuC. Bspec: 48077 Signed-off-by: Michel Thierry <michel.thierry@intel.com> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com> --- drivers/gpu/drm/i915/intel_device_info.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index f99c9fd497b2..2a39b52c3582 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -1022,8 +1022,9 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv) /* * In Gen11, only even numbered logical VDBOXes are * hooked up to an SFC (Scaler & Format Converter) unit. + * In TGL each VDBOX has access to an SFC. */ - if (logical_vdbox++ % 2 == 0) + if (IS_TIGERLAKE(dev_priv) || logical_vdbox++ % 2 == 0) RUNTIME_INFO(dev_priv)->vdbox_sfc_access |= BIT(i); } DRM_DEBUG_DRIVER("vdbox enable: %04x, instances: %04lx\n", -- 2.22.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH 4/4] drm/i915/tgl: Report valid VDBoxes with SFC capability 2019-07-31 0:49 ` [PATCH 4/4] drm/i915/tgl: Report valid VDBoxes with SFC capability Daniele Ceraolo Spurio @ 2019-07-31 5:59 ` Tvrtko Ursulin 2019-07-31 17:09 ` Daniele Ceraolo Spurio 0 siblings, 1 reply; 14+ messages in thread From: Tvrtko Ursulin @ 2019-07-31 5:59 UTC (permalink / raw) To: Daniele Ceraolo Spurio, intel-gfx; +Cc: Michel Thierry, Lucas De Marchi On 31/07/2019 01:49, Daniele Ceraolo Spurio wrote: > From: Michel Thierry <michel.thierry@intel.com> > > In Gen11, only even numbered "logical" VDBoxes are hooked up to a SFC > (Scaler & Format Converter) unit. This is not the case in Tigerlake, > where each VDBox can access a SFC. > > We will use this information to decide when the SFC units need to be reset > and also pass it to the GuC. > > Bspec: 48077 > Signed-off-by: Michel Thierry <michel.thierry@intel.com> > Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> > Cc: Lucas De Marchi <lucas.demarchi@intel.com> > Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com> > --- > drivers/gpu/drm/i915/intel_device_info.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c > index f99c9fd497b2..2a39b52c3582 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.c > +++ b/drivers/gpu/drm/i915/intel_device_info.c > @@ -1022,8 +1022,9 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv) > /* > * In Gen11, only even numbered logical VDBOXes are > * hooked up to an SFC (Scaler & Format Converter) unit. > + * In TGL each VDBOX has access to an SFC. > */ > - if (logical_vdbox++ % 2 == 0) > + if (IS_TIGERLAKE(dev_priv) || logical_vdbox++ % 2 == 0) > RUNTIME_INFO(dev_priv)->vdbox_sfc_access |= BIT(i); > } > DRM_DEBUG_DRIVER("vdbox enable: %04x, instances: %04lx\n", > Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Only uncertainty is if we want to code the condition as Icelake exception instead for more future proofing. Like if "!IS_ICELAKE ||" instead of "IS_TIGERLAKE ||"? Regards, Tvrtko _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 4/4] drm/i915/tgl: Report valid VDBoxes with SFC capability 2019-07-31 5:59 ` Tvrtko Ursulin @ 2019-07-31 17:09 ` Daniele Ceraolo Spurio 0 siblings, 0 replies; 14+ messages in thread From: Daniele Ceraolo Spurio @ 2019-07-31 17:09 UTC (permalink / raw) To: Tvrtko Ursulin, intel-gfx; +Cc: Michel Thierry, Lucas De Marchi On 7/30/19 10:59 PM, Tvrtko Ursulin wrote: > > On 31/07/2019 01:49, Daniele Ceraolo Spurio wrote: >> From: Michel Thierry <michel.thierry@intel.com> >> >> In Gen11, only even numbered "logical" VDBoxes are hooked up to a SFC >> (Scaler & Format Converter) unit. This is not the case in Tigerlake, >> where each VDBox can access a SFC. >> >> We will use this information to decide when the SFC units need to be >> reset >> and also pass it to the GuC. >> >> Bspec: 48077 >> Signed-off-by: Michel Thierry <michel.thierry@intel.com> >> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> >> Cc: Lucas De Marchi <lucas.demarchi@intel.com> >> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com> >> --- >> drivers/gpu/drm/i915/intel_device_info.c | 3 ++- >> 1 file changed, 2 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/i915/intel_device_info.c >> b/drivers/gpu/drm/i915/intel_device_info.c >> index f99c9fd497b2..2a39b52c3582 100644 >> --- a/drivers/gpu/drm/i915/intel_device_info.c >> +++ b/drivers/gpu/drm/i915/intel_device_info.c >> @@ -1022,8 +1022,9 @@ void intel_device_info_init_mmio(struct >> drm_i915_private *dev_priv) >> /* >> * In Gen11, only even numbered logical VDBOXes are >> * hooked up to an SFC (Scaler & Format Converter) unit. >> + * In TGL each VDBOX has access to an SFC. >> */ >> - if (logical_vdbox++ % 2 == 0) >> + if (IS_TIGERLAKE(dev_priv) || logical_vdbox++ % 2 == 0) >> RUNTIME_INFO(dev_priv)->vdbox_sfc_access |= BIT(i); >> } >> DRM_DEBUG_DRIVER("vdbox enable: %04x, instances: %04lx\n", >> > > Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > > Only uncertainty is if we want to code the condition as Icelake > exception instead for more future proofing. Like if "!IS_ICELAKE ||" > instead of "IS_TIGERLAKE ||"? If I'm understanding the specs correctly then this isn't going to apply to all future platform and we'll have some of them that behave like ICL instead. Maybe a device flag would work better? HAS_SFC_FOR_EACH_VCS()? Daniele > > Regards, > > Tvrtko _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 14+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for Initial TGL submission changes 2019-07-31 0:48 [PATCH 0/4] Initial TGL submission changes Daniele Ceraolo Spurio ` (3 preceding siblings ...) 2019-07-31 0:49 ` [PATCH 4/4] drm/i915/tgl: Report valid VDBoxes with SFC capability Daniele Ceraolo Spurio @ 2019-07-31 1:10 ` Patchwork 2019-07-31 1:39 ` ✓ Fi.CI.BAT: success " Patchwork 2019-08-01 15:15 ` ✓ Fi.CI.IGT: " Patchwork 6 siblings, 0 replies; 14+ messages in thread From: Patchwork @ 2019-07-31 1:10 UTC (permalink / raw) To: Daniele Ceraolo Spurio; +Cc: intel-gfx == Series Details == Series: Initial TGL submission changes URL : https://patchwork.freedesktop.org/series/64461/ State : warning == Summary == $ dim checkpatch origin/drm-tip 74d80bbbdcd2 drm/i915/tgl: add Gen12 default indirect ctx offset d43424d8627c drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID 0cef7902632f drm/i915/tgl: Gen12 csb support -:48: WARNING:FUNCTION_ARGUMENTS: function definition argument 'const struct intel_engine_execlists *' should also have an identifier name #48: FILE: drivers/gpu/drm/i915/gt/intel_engine_types.h:264: + enum intel_csb_step total: 0 errors, 1 warnings, 0 checks, 123 lines checked b6503210b823 drm/i915/tgl: Report valid VDBoxes with SFC capability _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 14+ messages in thread
* ✓ Fi.CI.BAT: success for Initial TGL submission changes 2019-07-31 0:48 [PATCH 0/4] Initial TGL submission changes Daniele Ceraolo Spurio ` (4 preceding siblings ...) 2019-07-31 1:10 ` ✗ Fi.CI.CHECKPATCH: warning for Initial TGL submission changes Patchwork @ 2019-07-31 1:39 ` Patchwork 2019-08-01 15:15 ` ✓ Fi.CI.IGT: " Patchwork 6 siblings, 0 replies; 14+ messages in thread From: Patchwork @ 2019-07-31 1:39 UTC (permalink / raw) To: Daniele Ceraolo Spurio; +Cc: intel-gfx == Series Details == Series: Initial TGL submission changes URL : https://patchwork.freedesktop.org/series/64461/ State : success == Summary == CI Bug Log - changes from CI_DRM_6586 -> Patchwork_13815 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/ Known issues ------------ Here are the changes found in Patchwork_13815 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@kms_busy@basic-flip-a: - fi-kbl-7567u: [PASS][1] -> [SKIP][2] ([fdo#109271] / [fdo#109278]) +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/fi-kbl-7567u/igt@kms_busy@basic-flip-a.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/fi-kbl-7567u/igt@kms_busy@basic-flip-a.html * igt@kms_busy@basic-flip-c: - fi-kbl-7500u: [PASS][3] -> [SKIP][4] ([fdo#109271] / [fdo#109278]) +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/fi-kbl-7500u/igt@kms_busy@basic-flip-c.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/fi-kbl-7500u/igt@kms_busy@basic-flip-c.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-kbl-7567u: [PASS][5] -> [WARN][6] ([fdo#109380]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/fi-kbl-7567u/igt@kms_chamelium@common-hpd-after-suspend.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/fi-kbl-7567u/igt@kms_chamelium@common-hpd-after-suspend.html * igt@kms_pipe_crc_basic@read-crc-pipe-c: - fi-kbl-7567u: [PASS][7] -> [SKIP][8] ([fdo#109271]) +23 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/fi-kbl-7567u/igt@kms_pipe_crc_basic@read-crc-pipe-c.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/fi-kbl-7567u/igt@kms_pipe_crc_basic@read-crc-pipe-c.html #### Possible fixes #### * igt@i915_module_load@reload-no-display: - fi-bwr-2160: [INCOMPLETE][9] ([fdo#111174]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/fi-bwr-2160/igt@i915_module_load@reload-no-display.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/fi-bwr-2160/igt@i915_module_load@reload-no-display.html * igt@kms_chamelium@hdmi-edid-read: - {fi-icl-u4}: [FAIL][11] ([fdo#111045] / [fdo#111046 ]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/fi-icl-u4/igt@kms_chamelium@hdmi-edid-read.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/fi-icl-u4/igt@kms_chamelium@hdmi-edid-read.html * igt@kms_chamelium@hdmi-hpd-fast: - {fi-icl-u4}: [FAIL][13] ([fdo#111045]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/fi-icl-u4/igt@kms_chamelium@hdmi-hpd-fast.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/fi-icl-u4/igt@kms_chamelium@hdmi-hpd-fast.html #### Warnings #### * igt@kms_chamelium@common-hpd-after-suspend: - fi-icl-u2: [DMESG-WARN][15] ([fdo#102505] / [fdo#110390]) -> [FAIL][16] ([fdo#109483]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#102505]: https://bugs.freedesktop.org/show_bug.cgi?id=102505 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#109380]: https://bugs.freedesktop.org/show_bug.cgi?id=109380 [fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483 [fdo#110390]: https://bugs.freedesktop.org/show_bug.cgi?id=110390 [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045 [fdo#111046 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111046 [fdo#111049]: https://bugs.freedesktop.org/show_bug.cgi?id=111049 [fdo#111174]: https://bugs.freedesktop.org/show_bug.cgi?id=111174 Participating hosts (54 -> 43) ------------------------------ Missing (11): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-skl-guc fi-byt-squawks fi-bsw-cyan fi-snb-2520m fi-icl-u3 fi-icl-y fi-byt-clapper fi-bdw-samus Build changes ------------- * CI: CI-20190529 -> None * Linux: CI_DRM_6586 -> Patchwork_13815 CI-20190529: 20190529 CI_DRM_6586: 066993443a56467f54fdcf560e89378f8e93a15b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5116: d2e6dd2f789596da5bd06efc2e9448e3160583b6 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_13815: b6503210b82338253ab4a38156901a0a6acbae01 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == b6503210b823 drm/i915/tgl: Report valid VDBoxes with SFC capability 0cef7902632f drm/i915/tgl: Gen12 csb support d43424d8627c drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID 74d80bbbdcd2 drm/i915/tgl: add Gen12 default indirect ctx offset == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/ _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 14+ messages in thread
* ✓ Fi.CI.IGT: success for Initial TGL submission changes 2019-07-31 0:48 [PATCH 0/4] Initial TGL submission changes Daniele Ceraolo Spurio ` (5 preceding siblings ...) 2019-07-31 1:39 ` ✓ Fi.CI.BAT: success " Patchwork @ 2019-08-01 15:15 ` Patchwork 6 siblings, 0 replies; 14+ messages in thread From: Patchwork @ 2019-08-01 15:15 UTC (permalink / raw) To: Daniele Ceraolo Spurio; +Cc: intel-gfx == Series Details == Series: Initial TGL submission changes URL : https://patchwork.freedesktop.org/series/64461/ State : success == Summary == CI Bug Log - changes from CI_DRM_6586_full -> Patchwork_13815_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_13815_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_ctx_isolation@rcs0-s3: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([fdo#108566]) +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-apl2/igt@gem_ctx_isolation@rcs0-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/shard-apl6/igt@gem_ctx_isolation@rcs0-s3.html * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#110854]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-iclb1/igt@gem_exec_balancer@smoke.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/shard-iclb7/igt@gem_exec_balancer@smoke.html * igt@gem_exec_suspend@basic-s3: - shard-skl: [PASS][5] -> ([PASS][6], [INCOMPLETE][7]) ([fdo#104108]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-skl8/igt@gem_exec_suspend@basic-s3.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/shard-skl9/igt@gem_exec_suspend@basic-s3.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/shard-skl4/igt@gem_exec_suspend@basic-s3.html * igt@gem_pwrite@huge-cpu-backwards: - shard-hsw: [PASS][8] -> ([INCOMPLETE][9], [PASS][10]) ([fdo#103540]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-hsw7/igt@gem_pwrite@huge-cpu-backwards.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/shard-hsw5/igt@gem_pwrite@huge-cpu-backwards.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/shard-hsw6/igt@gem_pwrite@huge-cpu-backwards.html * igt@gem_softpin@noreloc-s3: - shard-kbl: [PASS][11] -> ([DMESG-WARN][12], [DMESG-WARN][13]) ([fdo#108566]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-kbl4/igt@gem_softpin@noreloc-s3.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/shard-kbl6/igt@gem_softpin@noreloc-s3.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/shard-kbl4/igt@gem_softpin@noreloc-s3.html * igt@gem_tiled_fence_blits@normal: - shard-iclb: [PASS][14] -> [INCOMPLETE][15] ([fdo#107713]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-iclb2/igt@gem_tiled_fence_blits@normal.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/shard-iclb1/igt@gem_tiled_fence_blits@normal.html * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy: - shard-hsw: [PASS][16] -> ([PASS][17], [FAIL][18]) ([fdo#105767]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-hsw2/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/shard-hsw5/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/shard-hsw6/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html * igt@kms_draw_crc@draw-method-rgb565-pwrite-xtiled: - shard-iclb: [PASS][19] -> [FAIL][20] ([fdo#103184] / [fdo#103232]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-iclb1/igt@kms_draw_crc@draw-method-rgb565-pwrite-xtiled.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/shard-iclb8/igt@kms_draw_crc@draw-method-rgb565-pwrite-xtiled.html * igt@kms_flip@2x-dpms-vs-vblank-race-interruptible: - shard-glk: [PASS][21] -> ([FAIL][22], [PASS][23]) ([fdo#103060]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-glk9/igt@kms_flip@2x-dpms-vs-vblank-race-interruptible.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/shard-glk4/igt@kms_flip@2x-dpms-vs-vblank-race-interruptible.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/shard-glk7/igt@kms_flip@2x-dpms-vs-vblank-race-interruptible.html * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt: - shard-hsw: [PASS][24] -> ([PASS][25], [SKIP][26]) ([fdo#109271]) [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-hsw4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/shard-hsw5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/shard-hsw2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-gtt: - shard-skl: [PASS][27] -> ([FAIL][28], [FAIL][29]) ([fdo#103167]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-skl4/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-gtt.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/shard-skl8/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-gtt.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/shard-skl9/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-gtt.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt: - shard-iclb: [PASS][30] -> [FAIL][31] ([fdo#103167]) +5 similar issues [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/shard-iclb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-kbl: [PASS][32] -> [DMESG-WARN][33] ([fdo#108566]) [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-kbl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/shard-kbl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [PASS][34] -> ([FAIL][35], [FAIL][36]) ([fdo#108145]) [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-skl4/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/shard-skl8/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html * igt@kms_psr2_su@frontbuffer: - shard-iclb: [PASS][37] -> [SKIP][38] ([fdo#109642] / [fdo#111068]) [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-iclb2/igt@kms_psr2_su@frontbuffer.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/shard-iclb1/igt@kms_psr2_su@frontbuffer.html * igt@kms_psr@psr2_primary_page_flip: - shard-iclb: [PASS][39] -> [SKIP][40] ([fdo#109441]) [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/shard-iclb1/igt@kms_psr@psr2_primary_page_flip.html * igt@kms_vblank@pipe-a-ts-continuation-suspend: - shard-kbl: [PASS][41] -> ([DMESG-WARN][42], [PASS][43]) ([fdo#108566]) +8 similar issues [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-kbl2/igt@kms_vblank@pipe-a-ts-continuation-suspend.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/shard-kbl4/igt@kms_vblank@pipe-a-ts-continuation-suspend.html [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/shard-kbl2/igt@kms_vblank@pipe-a-ts-continuation-suspend.html * igt@kms_vblank@pipe-c-ts-continuation-suspend: - shard-apl: [PASS][44] -> ([DMESG-WARN][45], [PASS][46]) ([fdo#108566]) +1 similar issue [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-apl2/igt@kms_vblank@pipe-c-ts-continuation-suspend.html [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/shard-apl5/igt@kms_vblank@pipe-c-ts-continuation-suspend.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/shard-apl6/igt@kms_vblank@pipe-c-ts-continuation-suspend.html #### Possible fixes #### * igt@gem_ctx_isolation@vecs0-s3: - shard-apl: [DMESG-WARN][47] ([fdo#108566]) -> ([PASS][48], [PASS][49]) +1 similar issue [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-apl2/igt@gem_ctx_isolation@vecs0-s3.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/shard-apl6/igt@gem_ctx_isolation@vecs0-s3.html [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/shard-apl5/igt@gem_ctx_isolation@vecs0-s3.html * igt@i915_suspend@fence-restore-tiled2untiled: - shard-apl: [DMESG-WARN][50] ([fdo#108566]) -> [PASS][51] [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-apl5/igt@i915_suspend@fence-restore-tiled2untiled.html [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/shard-apl4/igt@i915_suspend@fence-restore-tiled2untiled.html * igt@kms_cursor_legacy@all-pipes-torture-bo: - shard-iclb: [INCOMPLETE][52] ([fdo#107713]) -> [PASS][53] [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-iclb7/igt@kms_cursor_legacy@all-pipes-torture-bo.html [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/shard-iclb3/igt@kms_cursor_legacy@all-pipes-torture-bo.html * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: - shard-glk: [FAIL][54] ([fdo#105363]) -> ([PASS][55], [PASS][56]) [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-glk7/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/shard-glk6/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/shard-glk7/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html * igt@kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [DMESG-WARN][57] ([fdo#108566]) -> ([PASS][58], [PASS][59]) +1 similar issue [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-kbl4/igt@kms_frontbuffer_tracking@fbc-suspend.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/shard-kbl2/igt@kms_frontbuffer_tracking@fbc-suspend.html [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/shard-kbl1/igt@kms_frontbuffer_tracking@fbc-suspend.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-pwrite: - shard-iclb: [FAIL][60] ([fdo#103167]) -> [PASS][61] +2 similar issues [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-pwrite.html [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/shard-iclb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-pwrite.html * igt@kms_psr@psr2_sprite_plane_move: - shard-iclb: [SKIP][62] ([fdo#109441]) -> [PASS][63] +4 similar issues [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-iclb3/igt@kms_psr@psr2_sprite_plane_move.html [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html #### Warnings #### * igt@gem_softpin@noreloc-s3: - shard-apl: [DMESG-WARN][64] ([fdo#108566]) -> ([DMESG-WARN][65], [PASS][66]) ([fdo#108566]) [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-apl7/igt@gem_softpin@noreloc-s3.html [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/shard-apl8/igt@gem_softpin@noreloc-s3.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/shard-apl3/igt@gem_softpin@noreloc-s3.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-kbl: [DMESG-WARN][67] ([fdo#108566]) -> ([DMESG-WARN][68], [PASS][69]) ([fdo#108566]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/shard-kbl6/igt@kms_flip@flip-vs-suspend-interruptible.html [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible.html [fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060 [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184 [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232 [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540 [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108 [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363 [fdo#105767]: https://bugs.freedesktop.org/show_bug.cgi?id=105767 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 Participating hosts (10 -> 10) ------------------------------ No changes in participating hosts Build changes ------------- * CI: CI-20190529 -> None * Linux: CI_DRM_6586 -> Patchwork_13815 CI-20190529: 20190529 CI_DRM_6586: 066993443a56467f54fdcf560e89378f8e93a15b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5116: d2e6dd2f789596da5bd06efc2e9448e3160583b6 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_13815: b6503210b82338253ab4a38156901a0a6acbae01 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/ _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2019-08-01 15:15 UTC | newest] Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-07-31 0:48 [PATCH 0/4] Initial TGL submission changes Daniele Ceraolo Spurio 2019-07-31 0:48 ` [PATCH 1/4] drm/i915/tgl: add Gen12 default indirect ctx offset Daniele Ceraolo Spurio 2019-07-31 0:49 ` [PATCH 2/4] drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID Daniele Ceraolo Spurio 2019-07-31 0:49 ` [PATCH 3/4] drm/i915/tgl: Gen12 csb support Daniele Ceraolo Spurio 2019-07-31 6:29 ` Tvrtko Ursulin 2019-07-31 17:33 ` Daniele Ceraolo Spurio 2019-07-31 7:33 ` Chris Wilson 2019-07-31 20:18 ` Daniele Ceraolo Spurio 2019-07-31 0:49 ` [PATCH 4/4] drm/i915/tgl: Report valid VDBoxes with SFC capability Daniele Ceraolo Spurio 2019-07-31 5:59 ` Tvrtko Ursulin 2019-07-31 17:09 ` Daniele Ceraolo Spurio 2019-07-31 1:10 ` ✗ Fi.CI.CHECKPATCH: warning for Initial TGL submission changes Patchwork 2019-07-31 1:39 ` ✓ Fi.CI.BAT: success " Patchwork 2019-08-01 15:15 ` ✓ Fi.CI.IGT: " Patchwork
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