* [PATCH] net: phy: smsc: LAN8740: add PHY_RST_AFTER_CLK_EN flag
@ 2019-10-23 9:44 Martin Fuzzey
2019-10-23 15:40 ` Andrew Lunn
2019-10-24 4:45 ` David Miller
0 siblings, 2 replies; 3+ messages in thread
From: Martin Fuzzey @ 2019-10-23 9:44 UTC (permalink / raw)
To: Andrew Lunn; +Cc: netdev
The LAN8740, like the 8720, also requires a reset after enabling clock.
The datasheet [1] 3.8.5.1 says:
"During a Hardware reset, an external clock must be supplied
to the XTAL1/CLKIN signal."
I have observed this issue on a custom i.MX6 based board with
the LAN8740A.
[1] http://ww1.microchip.com/downloads/en/DeviceDoc/8740a.pdf
Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
---
drivers/net/phy/smsc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/phy/smsc.c b/drivers/net/phy/smsc.c
index dc3d92d..b732982 100644
--- a/drivers/net/phy/smsc.c
+++ b/drivers/net/phy/smsc.c
@@ -327,6 +327,7 @@ static int smsc_phy_probe(struct phy_device *phydev)
.name = "SMSC LAN8740",
/* PHY_BASIC_FEATURES */
+ .flags = PHY_RST_AFTER_CLK_EN,
.probe = smsc_phy_probe,
--
1.9.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] net: phy: smsc: LAN8740: add PHY_RST_AFTER_CLK_EN flag
2019-10-23 9:44 [PATCH] net: phy: smsc: LAN8740: add PHY_RST_AFTER_CLK_EN flag Martin Fuzzey
@ 2019-10-23 15:40 ` Andrew Lunn
2019-10-24 4:45 ` David Miller
1 sibling, 0 replies; 3+ messages in thread
From: Andrew Lunn @ 2019-10-23 15:40 UTC (permalink / raw)
To: Martin Fuzzey; +Cc: netdev
On Wed, Oct 23, 2019 at 11:44:24AM +0200, Martin Fuzzey wrote:
> The LAN8740, like the 8720, also requires a reset after enabling clock.
> The datasheet [1] 3.8.5.1 says:
> "During a Hardware reset, an external clock must be supplied
> to the XTAL1/CLKIN signal."
>
> I have observed this issue on a custom i.MX6 based board with
> the LAN8740A.
>
> [1] http://ww1.microchip.com/downloads/en/DeviceDoc/8740a.pdf
>
> Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Andrew
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] net: phy: smsc: LAN8740: add PHY_RST_AFTER_CLK_EN flag
2019-10-23 9:44 [PATCH] net: phy: smsc: LAN8740: add PHY_RST_AFTER_CLK_EN flag Martin Fuzzey
2019-10-23 15:40 ` Andrew Lunn
@ 2019-10-24 4:45 ` David Miller
1 sibling, 0 replies; 3+ messages in thread
From: David Miller @ 2019-10-24 4:45 UTC (permalink / raw)
To: martin.fuzzey; +Cc: andrew, netdev
From: Martin Fuzzey <martin.fuzzey@flowbird.group>
Date: Wed, 23 Oct 2019 11:44:24 +0200
> The LAN8740, like the 8720, also requires a reset after enabling clock.
> The datasheet [1] 3.8.5.1 says:
> "During a Hardware reset, an external clock must be supplied
> to the XTAL1/CLKIN signal."
>
> I have observed this issue on a custom i.MX6 based board with
> the LAN8740A.
>
> [1] http://ww1.microchip.com/downloads/en/DeviceDoc/8740a.pdf
>
> Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
Applied, thanks.
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2019-10-24 4:45 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
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2019-10-23 9:44 [PATCH] net: phy: smsc: LAN8740: add PHY_RST_AFTER_CLK_EN flag Martin Fuzzey
2019-10-23 15:40 ` Andrew Lunn
2019-10-24 4:45 ` David Miller
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