From: Jacob Pan <jacob.jun.pan@linux.intel.com> To: Lu Baolu <baolu.lu@linux.intel.com> Cc: iommu@lists.linux-foundation.org, LKML <linux-kernel@vger.kernel.org>, Joerg Roedel <joro@8bytes.org>, David Woodhouse <dwmw2@infradead.org>, Alex Williamson <alex.williamson@redhat.com>, Jean-Philippe Brucker <jean-philippe@linaro.com>, Yi Liu <yi.l.liu@intel.com>, "Tian, Kevin" <kevin.tian@intel.com>, Raj Ashok <ashok.raj@intel.com>, Christoph Hellwig <hch@infradead.org>, Jonathan Cameron <jic23@kernel.org>, Eric Auger <eric.auger@redhat.com>, jacob.jun.pan@linux.intel.com Subject: Re: [PATCH v7 10/11] iommu/vt-d: Support flushing more translation cache types Date: Fri, 1 Nov 2019 14:28:59 -0700 [thread overview] Message-ID: <20191101142859.708a584d@jacob-builder> (raw) In-Reply-To: <40776827-c053-2a30-5606-d4ccdbd35fc8@linux.intel.com> On Sat, 26 Oct 2019 10:22:43 +0800 Lu Baolu <baolu.lu@linux.intel.com> wrote: > Hi, > > On 10/25/19 3:55 AM, Jacob Pan wrote: > > When Shared Virtual Memory is exposed to a guest via vIOMMU, > > scalable IOTLB invalidation may be passed down from outside IOMMU > > subsystems. This patch adds invalidation functions that can be used > > for additional translation cache types. > > > > Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com> > > --- > > drivers/iommu/dmar.c | 46 > > +++++++++++++++++++++++++++++++++++++++++++++ > > drivers/iommu/intel-pasid.c | 3 ++- include/linux/intel-iommu.h | > > 21 +++++++++++++++++---- 3 files changed, 65 insertions(+), 5 > > deletions(-) > > > > diff --git a/drivers/iommu/dmar.c b/drivers/iommu/dmar.c > > index 49bb7d76e646..0ce2d32ff99e 100644 > > --- a/drivers/iommu/dmar.c > > +++ b/drivers/iommu/dmar.c > > @@ -1346,6 +1346,20 @@ void qi_flush_iotlb(struct intel_iommu > > *iommu, u16 did, u64 addr, qi_submit_sync(&desc, iommu); > > } > > > > +/* PASID-based IOTLB Invalidate */ > > +void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u64 addr, > > u32 pasid, > > + unsigned int size_order, u64 granu, int ih) > > +{ > > + struct qi_desc desc = {.qw2 = 0, .qw3 = 0}; > > + > > + desc.qw0 = QI_EIOTLB_PASID(pasid) | QI_EIOTLB_DID(did) | > > + QI_EIOTLB_GRAN(granu) | QI_EIOTLB_TYPE; > > + desc.qw1 = QI_EIOTLB_ADDR(addr) | QI_EIOTLB_IH(ih) | > > + QI_EIOTLB_AM(size_order); > > + > > + qi_submit_sync(&desc, iommu); > > +} > > + > > void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 > > pfsid, u16 qdep, u64 addr, unsigned mask) > > { > > @@ -1369,6 +1383,38 @@ void qi_flush_dev_iotlb(struct intel_iommu > > *iommu, u16 sid, u16 pfsid, qi_submit_sync(&desc, iommu); > > } > > > > +/* PASID-based device IOTLB Invalidate */ > > +void qi_flush_dev_piotlb(struct intel_iommu *iommu, u16 sid, u16 > > pfsid, > > + u32 pasid, u16 qdep, u64 addr, unsigned > > size_order, u64 granu) +{ > > + struct qi_desc desc; > > Do you need to set qw2 and qw3 to 0? > right, forgot to add struct qi_desc desc = {.qw2 = 0, .qw3 = 0}; > > + > > + desc.qw0 = QI_DEV_EIOTLB_PASID(pasid) | > > QI_DEV_EIOTLB_SID(sid) | > > + QI_DEV_EIOTLB_QDEP(qdep) | QI_DEIOTLB_TYPE | > > + QI_DEV_IOTLB_PFSID(pfsid); > > + desc.qw1 = QI_DEV_EIOTLB_GLOB(granu); > > + > > + /* If S bit is 0, we only flush a single page. If S bit is > > set, > > + * The least significant zero bit indicates the > > invalidation address > > + * range. VT-d spec 6.5.2.6. > > + * e.g. address bit 12[0] indicates 8KB, 13[0] indicates > > 16KB. > > + */ > > + if (!size_order) { > > + desc.qw0 |= QI_DEV_EIOTLB_ADDR(addr) & > > ~QI_DEV_EIOTLB_SIZE; > > + } else { > > + unsigned long mask = 1UL << (VTD_PAGE_SHIFT + > > size_order); > > + desc.qw1 |= QI_DEV_EIOTLB_ADDR(addr & ~mask) | > > QI_DEV_EIOTLB_SIZE; > > + } > > + qi_submit_sync(&desc, iommu); > > +} > > + > > +void qi_flush_pasid_cache(struct intel_iommu *iommu, u16 did, u64 > > granu, int pasid) +{ > > + struct qi_desc desc = {.qw1 = 0, .qw2 = 0, .qw3 = 0}; > > + > > + desc.qw0 = QI_PC_PASID(pasid) | QI_PC_DID(did) | > > QI_PC_GRAN(granu) | QI_PC_TYPE; > > + qi_submit_sync(&desc, iommu); > > +} > > /* > > * Disable Queued Invalidation interface. > > */ > > diff --git a/drivers/iommu/intel-pasid.c > > b/drivers/iommu/intel-pasid.c index f846a907cfcf..6d7a701ef4d3 > > 100644 --- a/drivers/iommu/intel-pasid.c > > +++ b/drivers/iommu/intel-pasid.c > > @@ -491,7 +491,8 @@ pasid_cache_invalidation_with_pasid(struct > > intel_iommu *iommu, { > > struct qi_desc desc; > > > > - desc.qw0 = QI_PC_DID(did) | QI_PC_PASID_SEL | > > QI_PC_PASID(pasid); > > + desc.qw0 = QI_PC_DID(did) | QI_PC_GRAN(QI_PC_PASID_SEL) | > > + QI_PC_PASID(pasid) | QI_PC_TYPE; > > desc.qw1 = 0; > > desc.qw2 = 0; > > desc.qw3 = 0; > > diff --git a/include/linux/intel-iommu.h > > b/include/linux/intel-iommu.h index 6c74c71b1ebf..a25fb3a0ea5b > > 100644 --- a/include/linux/intel-iommu.h > > +++ b/include/linux/intel-iommu.h > > @@ -332,7 +332,7 @@ enum { > > #define QI_IOTLB_GRAN(gran) (((u64)gran) >> > > (DMA_TLB_FLUSH_GRANU_OFFSET-4)) #define QI_IOTLB_ADDR(addr) > > (((u64)addr) & VTD_PAGE_MASK) #define > > QI_IOTLB_IH(ih) (((u64)ih) << 6) -#define > > QI_IOTLB_AM(am) (((u8)am)) +#define > > QI_IOTLB_AM(am) (((u8)am) & 0x3f) > > #define QI_CC_FM(fm) (((u64)fm) << 48) > > #define QI_CC_SID(sid) (((u64)sid) << 32) > > @@ -350,16 +350,21 @@ enum { > > #define QI_PC_DID(did) (((u64)did) << 16) > > #define QI_PC_GRAN(gran) (((u64)gran) << 4) > > > > -#define QI_PC_ALL_PASIDS (QI_PC_TYPE | QI_PC_GRAN(0)) > > -#define QI_PC_PASID_SEL (QI_PC_TYPE | QI_PC_GRAN(1)) > > +/* PASID cache invalidation granu */ > > +#define QI_PC_ALL_PASIDS 0 > > +#define QI_PC_PASID_SEL 1 > > > > #define QI_EIOTLB_ADDR(addr) ((u64)(addr) & VTD_PAGE_MASK) > > #define QI_EIOTLB_IH(ih) (((u64)ih) << 6) > > -#define QI_EIOTLB_AM(am) (((u64)am)) > > +#define QI_EIOTLB_AM(am) (((u64)am) & 0x3f) > > #define QI_EIOTLB_PASID(pasid) (((u64)pasid) << 32) > > #define QI_EIOTLB_DID(did) (((u64)did) << 16) > > #define QI_EIOTLB_GRAN(gran) (((u64)gran) << 4) > > > > +/* QI Dev-IOTLB inv granu */ > > +#define QI_DEV_IOTLB_GRAN_ALL 1 > > +#define QI_DEV_IOTLB_GRAN_PASID_SEL 0 > > + > > #define QI_DEV_EIOTLB_ADDR(a) ((u64)(a) & VTD_PAGE_MASK) > > #define QI_DEV_EIOTLB_SIZE (((u64)1) << 11) > > #define QI_DEV_EIOTLB_GLOB(g) ((u64)g) > > @@ -655,8 +660,16 @@ extern void qi_flush_context(struct > > intel_iommu *iommu, u16 did, u16 sid, u8 fm, u64 type); > > extern void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, > > u64 addr, unsigned int size_order, u64 type); > > +extern void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, > > u64 addr, > > + u32 pasid, unsigned int size_order, u64 > > type, int ih); extern void qi_flush_dev_iotlb(struct intel_iommu > > *iommu, u16 sid, u16 pfsid, u16 qdep, u64 addr, unsigned mask); > > + > > +extern void qi_flush_dev_piotlb(struct intel_iommu *iommu, u16 > > sid, u16 pfsid, > > + u32 pasid, u16 qdep, u64 addr, unsigned > > size_order, u64 granu); + > > +extern void qi_flush_pasid_cache(struct intel_iommu *iommu, u16 > > did, u64 granu, int pasid); + > > extern int qi_submit_sync(struct qi_desc *desc, struct > > intel_iommu *iommu); > > extern int dmar_ir_support(void); > > > > Best regards, > baolu [Jacob Pan]
WARNING: multiple messages have this Message-ID (diff)
From: Jacob Pan <jacob.jun.pan@linux.intel.com> To: Lu Baolu <baolu.lu@linux.intel.com> Cc: "Tian, Kevin" <kevin.tian@intel.com>, Raj Ashok <ashok.raj@intel.com>, David Woodhouse <dwmw2@infradead.org>, iommu@lists.linux-foundation.org, LKML <linux-kernel@vger.kernel.org>, Alex Williamson <alex.williamson@redhat.com>, Jean-Philippe Brucker <jean-philippe@linaro.com>, Jonathan Cameron <jic23@kernel.org> Subject: Re: [PATCH v7 10/11] iommu/vt-d: Support flushing more translation cache types Date: Fri, 1 Nov 2019 14:28:59 -0700 [thread overview] Message-ID: <20191101142859.708a584d@jacob-builder> (raw) In-Reply-To: <40776827-c053-2a30-5606-d4ccdbd35fc8@linux.intel.com> On Sat, 26 Oct 2019 10:22:43 +0800 Lu Baolu <baolu.lu@linux.intel.com> wrote: > Hi, > > On 10/25/19 3:55 AM, Jacob Pan wrote: > > When Shared Virtual Memory is exposed to a guest via vIOMMU, > > scalable IOTLB invalidation may be passed down from outside IOMMU > > subsystems. This patch adds invalidation functions that can be used > > for additional translation cache types. > > > > Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com> > > --- > > drivers/iommu/dmar.c | 46 > > +++++++++++++++++++++++++++++++++++++++++++++ > > drivers/iommu/intel-pasid.c | 3 ++- include/linux/intel-iommu.h | > > 21 +++++++++++++++++---- 3 files changed, 65 insertions(+), 5 > > deletions(-) > > > > diff --git a/drivers/iommu/dmar.c b/drivers/iommu/dmar.c > > index 49bb7d76e646..0ce2d32ff99e 100644 > > --- a/drivers/iommu/dmar.c > > +++ b/drivers/iommu/dmar.c > > @@ -1346,6 +1346,20 @@ void qi_flush_iotlb(struct intel_iommu > > *iommu, u16 did, u64 addr, qi_submit_sync(&desc, iommu); > > } > > > > +/* PASID-based IOTLB Invalidate */ > > +void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u64 addr, > > u32 pasid, > > + unsigned int size_order, u64 granu, int ih) > > +{ > > + struct qi_desc desc = {.qw2 = 0, .qw3 = 0}; > > + > > + desc.qw0 = QI_EIOTLB_PASID(pasid) | QI_EIOTLB_DID(did) | > > + QI_EIOTLB_GRAN(granu) | QI_EIOTLB_TYPE; > > + desc.qw1 = QI_EIOTLB_ADDR(addr) | QI_EIOTLB_IH(ih) | > > + QI_EIOTLB_AM(size_order); > > + > > + qi_submit_sync(&desc, iommu); > > +} > > + > > void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 > > pfsid, u16 qdep, u64 addr, unsigned mask) > > { > > @@ -1369,6 +1383,38 @@ void qi_flush_dev_iotlb(struct intel_iommu > > *iommu, u16 sid, u16 pfsid, qi_submit_sync(&desc, iommu); > > } > > > > +/* PASID-based device IOTLB Invalidate */ > > +void qi_flush_dev_piotlb(struct intel_iommu *iommu, u16 sid, u16 > > pfsid, > > + u32 pasid, u16 qdep, u64 addr, unsigned > > size_order, u64 granu) +{ > > + struct qi_desc desc; > > Do you need to set qw2 and qw3 to 0? > right, forgot to add struct qi_desc desc = {.qw2 = 0, .qw3 = 0}; > > + > > + desc.qw0 = QI_DEV_EIOTLB_PASID(pasid) | > > QI_DEV_EIOTLB_SID(sid) | > > + QI_DEV_EIOTLB_QDEP(qdep) | QI_DEIOTLB_TYPE | > > + QI_DEV_IOTLB_PFSID(pfsid); > > + desc.qw1 = QI_DEV_EIOTLB_GLOB(granu); > > + > > + /* If S bit is 0, we only flush a single page. If S bit is > > set, > > + * The least significant zero bit indicates the > > invalidation address > > + * range. VT-d spec 6.5.2.6. > > + * e.g. address bit 12[0] indicates 8KB, 13[0] indicates > > 16KB. > > + */ > > + if (!size_order) { > > + desc.qw0 |= QI_DEV_EIOTLB_ADDR(addr) & > > ~QI_DEV_EIOTLB_SIZE; > > + } else { > > + unsigned long mask = 1UL << (VTD_PAGE_SHIFT + > > size_order); > > + desc.qw1 |= QI_DEV_EIOTLB_ADDR(addr & ~mask) | > > QI_DEV_EIOTLB_SIZE; > > + } > > + qi_submit_sync(&desc, iommu); > > +} > > + > > +void qi_flush_pasid_cache(struct intel_iommu *iommu, u16 did, u64 > > granu, int pasid) +{ > > + struct qi_desc desc = {.qw1 = 0, .qw2 = 0, .qw3 = 0}; > > + > > + desc.qw0 = QI_PC_PASID(pasid) | QI_PC_DID(did) | > > QI_PC_GRAN(granu) | QI_PC_TYPE; > > + qi_submit_sync(&desc, iommu); > > +} > > /* > > * Disable Queued Invalidation interface. > > */ > > diff --git a/drivers/iommu/intel-pasid.c > > b/drivers/iommu/intel-pasid.c index f846a907cfcf..6d7a701ef4d3 > > 100644 --- a/drivers/iommu/intel-pasid.c > > +++ b/drivers/iommu/intel-pasid.c > > @@ -491,7 +491,8 @@ pasid_cache_invalidation_with_pasid(struct > > intel_iommu *iommu, { > > struct qi_desc desc; > > > > - desc.qw0 = QI_PC_DID(did) | QI_PC_PASID_SEL | > > QI_PC_PASID(pasid); > > + desc.qw0 = QI_PC_DID(did) | QI_PC_GRAN(QI_PC_PASID_SEL) | > > + QI_PC_PASID(pasid) | QI_PC_TYPE; > > desc.qw1 = 0; > > desc.qw2 = 0; > > desc.qw3 = 0; > > diff --git a/include/linux/intel-iommu.h > > b/include/linux/intel-iommu.h index 6c74c71b1ebf..a25fb3a0ea5b > > 100644 --- a/include/linux/intel-iommu.h > > +++ b/include/linux/intel-iommu.h > > @@ -332,7 +332,7 @@ enum { > > #define QI_IOTLB_GRAN(gran) (((u64)gran) >> > > (DMA_TLB_FLUSH_GRANU_OFFSET-4)) #define QI_IOTLB_ADDR(addr) > > (((u64)addr) & VTD_PAGE_MASK) #define > > QI_IOTLB_IH(ih) (((u64)ih) << 6) -#define > > QI_IOTLB_AM(am) (((u8)am)) +#define > > QI_IOTLB_AM(am) (((u8)am) & 0x3f) > > #define QI_CC_FM(fm) (((u64)fm) << 48) > > #define QI_CC_SID(sid) (((u64)sid) << 32) > > @@ -350,16 +350,21 @@ enum { > > #define QI_PC_DID(did) (((u64)did) << 16) > > #define QI_PC_GRAN(gran) (((u64)gran) << 4) > > > > -#define QI_PC_ALL_PASIDS (QI_PC_TYPE | QI_PC_GRAN(0)) > > -#define QI_PC_PASID_SEL (QI_PC_TYPE | QI_PC_GRAN(1)) > > +/* PASID cache invalidation granu */ > > +#define QI_PC_ALL_PASIDS 0 > > +#define QI_PC_PASID_SEL 1 > > > > #define QI_EIOTLB_ADDR(addr) ((u64)(addr) & VTD_PAGE_MASK) > > #define QI_EIOTLB_IH(ih) (((u64)ih) << 6) > > -#define QI_EIOTLB_AM(am) (((u64)am)) > > +#define QI_EIOTLB_AM(am) (((u64)am) & 0x3f) > > #define QI_EIOTLB_PASID(pasid) (((u64)pasid) << 32) > > #define QI_EIOTLB_DID(did) (((u64)did) << 16) > > #define QI_EIOTLB_GRAN(gran) (((u64)gran) << 4) > > > > +/* QI Dev-IOTLB inv granu */ > > +#define QI_DEV_IOTLB_GRAN_ALL 1 > > +#define QI_DEV_IOTLB_GRAN_PASID_SEL 0 > > + > > #define QI_DEV_EIOTLB_ADDR(a) ((u64)(a) & VTD_PAGE_MASK) > > #define QI_DEV_EIOTLB_SIZE (((u64)1) << 11) > > #define QI_DEV_EIOTLB_GLOB(g) ((u64)g) > > @@ -655,8 +660,16 @@ extern void qi_flush_context(struct > > intel_iommu *iommu, u16 did, u16 sid, u8 fm, u64 type); > > extern void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, > > u64 addr, unsigned int size_order, u64 type); > > +extern void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, > > u64 addr, > > + u32 pasid, unsigned int size_order, u64 > > type, int ih); extern void qi_flush_dev_iotlb(struct intel_iommu > > *iommu, u16 sid, u16 pfsid, u16 qdep, u64 addr, unsigned mask); > > + > > +extern void qi_flush_dev_piotlb(struct intel_iommu *iommu, u16 > > sid, u16 pfsid, > > + u32 pasid, u16 qdep, u64 addr, unsigned > > size_order, u64 granu); + > > +extern void qi_flush_pasid_cache(struct intel_iommu *iommu, u16 > > did, u64 granu, int pasid); + > > extern int qi_submit_sync(struct qi_desc *desc, struct > > intel_iommu *iommu); > > extern int dmar_ir_support(void); > > > > Best regards, > baolu [Jacob Pan] _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
next prev parent reply other threads:[~2019-11-01 21:24 UTC|newest] Thread overview: 158+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-10-24 19:54 [PATCH v7 00/11] Nested Shared Virtual Address (SVA) VT-d support Jacob Pan 2019-10-24 19:54 ` Jacob Pan 2019-10-24 19:54 ` [PATCH v7 01/11] iommu/vt-d: Cache virtual command capability register Jacob Pan 2019-10-24 19:54 ` Jacob Pan 2019-10-25 2:53 ` Lu Baolu 2019-10-25 2:53 ` Lu Baolu 2019-10-25 6:06 ` Tian, Kevin 2019-10-25 6:06 ` Tian, Kevin 2019-11-08 10:32 ` Auger Eric 2019-11-08 10:32 ` Auger Eric 2019-10-24 19:54 ` [PATCH v7 02/11] iommu/vt-d: Enlightened PASID allocation Jacob Pan 2019-10-24 19:54 ` Jacob Pan 2019-10-25 6:19 ` Tian, Kevin 2019-10-25 6:19 ` Tian, Kevin 2019-10-29 17:14 ` Jacob Pan 2019-10-29 17:14 ` Jacob Pan 2019-10-29 18:16 ` Tian, Kevin 2019-10-29 18:16 ` Tian, Kevin 2019-11-08 10:33 ` Auger Eric 2019-11-08 10:33 ` Auger Eric 2019-11-08 22:22 ` Jacob Pan 2019-11-08 22:22 ` Jacob Pan 2019-10-24 19:54 ` [PATCH v7 03/11] iommu/vt-d: Add custom allocator for IOASID Jacob Pan 2019-10-24 19:54 ` Jacob Pan 2019-10-25 2:30 ` Lu Baolu 2019-10-25 2:30 ` Lu Baolu 2019-10-25 4:43 ` Jacob Pan 2019-10-25 4:43 ` Jacob Pan 2019-10-25 6:40 ` Tian, Kevin 2019-10-25 6:40 ` Tian, Kevin 2019-10-25 14:39 ` Lu Baolu 2019-10-25 14:39 ` Lu Baolu 2019-10-25 15:52 ` Tian, Kevin 2019-10-25 15:52 ` Tian, Kevin 2019-10-28 22:49 ` Jacob Pan 2019-10-28 22:49 ` Jacob Pan 2019-10-29 2:22 ` Lu Baolu 2019-10-29 2:22 ` Lu Baolu 2019-10-25 6:31 ` Tian, Kevin 2019-10-25 6:31 ` Tian, Kevin 2019-10-28 22:52 ` Jacob Pan 2019-10-28 22:52 ` Jacob Pan 2019-11-08 10:40 ` Auger Eric 2019-11-08 10:40 ` Auger Eric 2019-11-08 22:26 ` Jacob Pan 2019-11-08 22:26 ` Jacob Pan 2019-10-24 19:54 ` [PATCH v7 04/11] iommu/vt-d: Replace Intel specific PASID allocator with IOASID Jacob Pan 2019-10-24 19:54 ` Jacob Pan 2019-10-25 5:47 ` Lu Baolu 2019-10-25 5:47 ` Lu Baolu 2019-11-01 18:29 ` Jacob Pan 2019-11-01 18:29 ` Jacob Pan 2019-10-25 6:41 ` Tian, Kevin 2019-10-25 6:41 ` Tian, Kevin 2019-10-28 22:46 ` Jacob Pan 2019-10-28 22:46 ` Jacob Pan 2019-11-08 11:30 ` Auger Eric 2019-11-08 11:30 ` Auger Eric 2019-11-08 22:55 ` Jacob Pan 2019-11-08 22:55 ` Jacob Pan 2019-11-12 9:54 ` Auger Eric 2019-11-12 9:54 ` Auger Eric 2019-10-24 19:54 ` [PATCH v7 05/11] iommu/vt-d: Move domain helper to header Jacob Pan 2019-10-24 19:54 ` Jacob Pan 2019-10-25 5:26 ` Lu Baolu 2019-10-25 5:26 ` Lu Baolu 2019-10-24 19:54 ` [PATCH v7 06/11] iommu/vt-d: Avoid duplicated code for PASID setup Jacob Pan 2019-10-24 19:54 ` Jacob Pan 2019-10-25 5:32 ` Lu Baolu 2019-10-25 5:32 ` Lu Baolu 2019-10-25 6:42 ` Tian, Kevin 2019-10-25 6:42 ` Tian, Kevin 2019-10-28 22:41 ` Jacob Pan 2019-10-28 22:41 ` Jacob Pan 2019-11-12 9:54 ` Auger Eric 2019-11-12 9:54 ` Auger Eric 2019-10-24 19:55 ` [PATCH v7 07/11] iommu/vt-d: Add nested translation helper function Jacob Pan 2019-10-24 19:55 ` Jacob Pan 2019-10-25 7:04 ` Tian, Kevin 2019-10-25 7:04 ` Tian, Kevin 2019-11-01 21:10 ` Jacob Pan 2019-11-01 21:10 ` Jacob Pan 2019-10-25 15:04 ` Lu Baolu 2019-10-25 15:04 ` Lu Baolu 2019-10-25 16:06 ` Jacob Pan 2019-10-25 16:06 ` Jacob Pan 2019-11-08 13:55 ` Auger Eric 2019-11-08 13:55 ` Auger Eric 2019-10-24 19:55 ` [PATCH v7 08/11] iommu/vt-d: Misc macro clean up for SVM Jacob Pan 2019-10-24 19:55 ` Jacob Pan 2019-10-26 1:00 ` Lu Baolu 2019-10-26 1:00 ` Lu Baolu 2019-10-28 22:38 ` Jacob Pan 2019-10-28 22:38 ` Jacob Pan 2019-10-24 19:55 ` [PATCH v7 09/11] iommu/vt-d: Add bind guest PASID support Jacob Pan 2019-10-24 19:55 ` Jacob Pan 2019-10-25 7:19 ` Tian, Kevin 2019-10-25 7:19 ` Tian, Kevin 2019-10-25 17:33 ` Jacob Pan 2019-10-25 17:33 ` Jacob Pan 2019-10-28 6:03 ` Tian, Kevin 2019-10-28 6:03 ` Tian, Kevin 2019-10-28 16:02 ` Jacob Pan 2019-10-28 16:02 ` Jacob Pan 2019-10-29 7:57 ` Tian, Kevin 2019-10-29 7:57 ` Tian, Kevin 2019-10-29 16:11 ` Jacob Pan 2019-10-29 16:11 ` Jacob Pan 2019-10-29 18:04 ` Tian, Kevin 2019-10-29 18:04 ` Tian, Kevin 2019-10-29 2:33 ` Lu Baolu 2019-10-29 2:33 ` Lu Baolu 2019-10-26 2:01 ` Lu Baolu 2019-10-26 2:01 ` Lu Baolu 2019-10-28 22:29 ` Jacob Pan 2019-10-28 22:29 ` Jacob Pan 2019-10-29 2:54 ` Lu Baolu 2019-10-29 2:54 ` Lu Baolu 2019-10-29 4:11 ` Jacob Pan 2019-10-29 4:11 ` Jacob Pan 2019-10-29 5:04 ` Lu Baolu 2019-10-29 5:04 ` Lu Baolu 2019-10-24 19:55 ` [PATCH v7 10/11] iommu/vt-d: Support flushing more translation cache types Jacob Pan 2019-10-24 19:55 ` Jacob Pan 2019-10-25 7:21 ` Tian, Kevin 2019-10-25 7:21 ` Tian, Kevin 2019-11-01 21:30 ` Jacob Pan 2019-11-01 21:30 ` Jacob Pan 2019-10-26 2:22 ` Lu Baolu 2019-10-26 2:22 ` Lu Baolu 2019-11-01 21:28 ` Jacob Pan [this message] 2019-11-01 21:28 ` Jacob Pan 2019-11-08 16:18 ` Auger Eric 2019-11-08 16:18 ` Auger Eric 2019-11-08 23:05 ` Jacob Pan 2019-11-08 23:05 ` Jacob Pan 2019-10-24 19:55 ` [PATCH v7 11/11] iommu/vt-d: Add svm/sva invalidate function Jacob Pan 2019-10-24 19:55 ` Jacob Pan 2019-10-25 7:27 ` Tian, Kevin 2019-10-25 7:27 ` Tian, Kevin 2019-10-26 2:40 ` Lu Baolu 2019-10-26 2:40 ` Lu Baolu 2019-10-26 7:03 ` Lu Baolu 2019-10-26 7:03 ` Lu Baolu 2019-10-28 6:06 ` Tian, Kevin 2019-10-28 6:06 ` Tian, Kevin 2019-10-28 16:10 ` Jacob Pan 2019-10-28 16:10 ` Jacob Pan 2019-10-29 18:52 ` Tian, Kevin 2019-10-29 18:52 ` Tian, Kevin 2019-10-29 19:25 ` Jacob Pan 2019-10-29 19:25 ` Jacob Pan 2019-10-28 16:13 ` Jacob Pan 2019-10-28 16:13 ` Jacob Pan 2019-11-12 10:28 ` Auger Eric 2019-11-12 10:28 ` Auger Eric 2020-02-15 1:18 ` Jacob Pan 2020-02-15 1:18 ` Jacob Pan
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