From: Animesh Manna <animesh.manna@intel.com> To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: jani.nikula@intel.com, nidhi1.gupta@intel.com, Animesh Manna <animesh.manna@intel.com>, manasi.d.navare@intel.com, uma.shankar@intel.com, anshuman.gupta@intel.com Subject: [PATCH v2 7/9] drm/i915/dp: Register definition for DP compliance register Date: Wed, 18 Dec 2019 20:43:48 +0530 [thread overview] Message-ID: <20191218151350.19579-8-animesh.manna@intel.com> (raw) In-Reply-To: <20191218151350.19579-1-animesh.manna@intel.com> DP_COMP_CTL and DP_COMP_PAT register used to program DP compliance pattern. Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index cbb4689af432..fc54143bd4a4 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -9788,6 +9788,26 @@ enum skl_power_gate { #define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31) #define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4) +/* DDI DP Compliance Control */ +#define DDI_DP_COMP_CTL_A 0x605F0 +#define DDI_DP_COMP_CTL_B 0x615F0 +#define DDI_DP_COMP_CTL(port) _MMIO_PORT(port, DDI_DP_COMP_CTL_A, \ + DDI_DP_COMP_CTL_B) +#define DDI_DP_COMP_CTL_ENABLE (1 << 31) +#define DDI_DP_COMP_CTL_D10_2 (0 << 28) +#define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28) +#define DDI_DP_COMP_CTL_PRBS7 (2 << 28) +#define DDI_DP_COMP_CTL_CUSTOM80 (3 << 28) +#define DDI_DP_COMP_CTL_HBR2 (4 << 28) +#define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28) +#define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0) + +/* DDI DP Compliance Pattern */ +#define DDI_DP_COMP_PAT_A 0x605F4 +#define DDI_DP_COMP_PAT_B 0x615F4 +#define DDI_DP_COMP_PAT(port, i) _MMIO(_PORT(port, DDI_DP_COMP_PAT_A, \ + DDI_DP_COMP_PAT_B) + (i) * 4) + /* Sideband Interface (SBI) is programmed indirectly, via * SBI_ADDR, which contains the register offset; and SBI_DATA, * which contains the payload */ -- 2.24.0 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
WARNING: multiple messages have this Message-ID (diff)
From: Animesh Manna <animesh.manna@intel.com> To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: jani.nikula@intel.com, nidhi1.gupta@intel.com Subject: [Intel-gfx] [PATCH v2 7/9] drm/i915/dp: Register definition for DP compliance register Date: Wed, 18 Dec 2019 20:43:48 +0530 [thread overview] Message-ID: <20191218151350.19579-8-animesh.manna@intel.com> (raw) In-Reply-To: <20191218151350.19579-1-animesh.manna@intel.com> DP_COMP_CTL and DP_COMP_PAT register used to program DP compliance pattern. Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index cbb4689af432..fc54143bd4a4 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -9788,6 +9788,26 @@ enum skl_power_gate { #define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31) #define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4) +/* DDI DP Compliance Control */ +#define DDI_DP_COMP_CTL_A 0x605F0 +#define DDI_DP_COMP_CTL_B 0x615F0 +#define DDI_DP_COMP_CTL(port) _MMIO_PORT(port, DDI_DP_COMP_CTL_A, \ + DDI_DP_COMP_CTL_B) +#define DDI_DP_COMP_CTL_ENABLE (1 << 31) +#define DDI_DP_COMP_CTL_D10_2 (0 << 28) +#define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28) +#define DDI_DP_COMP_CTL_PRBS7 (2 << 28) +#define DDI_DP_COMP_CTL_CUSTOM80 (3 << 28) +#define DDI_DP_COMP_CTL_HBR2 (4 << 28) +#define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28) +#define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0) + +/* DDI DP Compliance Pattern */ +#define DDI_DP_COMP_PAT_A 0x605F4 +#define DDI_DP_COMP_PAT_B 0x615F4 +#define DDI_DP_COMP_PAT(port, i) _MMIO(_PORT(port, DDI_DP_COMP_PAT_A, \ + DDI_DP_COMP_PAT_B) + (i) * 4) + /* Sideband Interface (SBI) is programmed indirectly, via * SBI_ADDR, which contains the register offset; and SBI_DATA, * which contains the payload */ -- 2.24.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2019-12-18 15:25 UTC|newest] Thread overview: 59+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-12-18 15:13 [PATCH v2 0/9] DP Phy compliance auto test Animesh Manna 2019-12-18 15:13 ` [Intel-gfx] " Animesh Manna 2019-12-18 15:13 ` [PATCH v2 1/9] drm/dp: get/set phy compliance pattern Animesh Manna 2019-12-18 15:13 ` [Intel-gfx] " Animesh Manna 2019-12-18 15:13 ` [PATCH v2 2/9] drm/amd/display: Fix compilation issue Animesh Manna 2019-12-18 15:13 ` [Intel-gfx] " Animesh Manna 2019-12-18 15:42 ` Harry Wentland 2019-12-18 15:42 ` [Intel-gfx] " Harry Wentland 2019-12-18 16:13 ` Manna, Animesh 2019-12-18 16:13 ` [Intel-gfx] " Manna, Animesh 2019-12-18 16:22 ` Harry Wentland 2019-12-18 16:22 ` [Intel-gfx] " Harry Wentland 2019-12-18 23:53 ` Manasi Navare 2019-12-18 23:53 ` [Intel-gfx] " Manasi Navare 2019-12-19 13:36 ` Manna, Animesh 2019-12-19 13:36 ` [Intel-gfx] " Manna, Animesh 2019-12-23 17:03 ` [PATCH v3 1/9] drm/amd/display: Align macro name as per DP spec Animesh Manna 2019-12-23 17:03 ` [Intel-gfx] " Animesh Manna 2019-12-23 17:03 ` [PATCH v3 2/9] drm/dp: get/set phy compliance pattern Animesh Manna 2019-12-23 17:03 ` [Intel-gfx] " Animesh Manna 2019-12-23 19:53 ` Harry Wentland 2019-12-23 19:53 ` [Intel-gfx] " Harry Wentland 2019-12-30 16:05 ` Manna, Animesh 2019-12-30 16:05 ` [Intel-gfx] " Manna, Animesh 2019-12-30 16:11 ` Harry Wentland 2019-12-30 16:11 ` [Intel-gfx] " Harry Wentland 2019-12-30 16:30 ` Manna, Animesh 2019-12-30 16:30 ` [Intel-gfx] " Manna, Animesh 2019-12-23 19:53 ` [PATCH v3 1/9] drm/amd/display: Align macro name as per DP spec Harry Wentland 2019-12-23 19:53 ` [Intel-gfx] " Harry Wentland 2019-12-18 15:13 ` [PATCH v2 3/9] drm/i915/dp: Move vswing/pre-emphasis adjustment calculation Animesh Manna 2019-12-18 15:13 ` [Intel-gfx] " Animesh Manna 2019-12-19 10:51 ` Jani Nikula 2019-12-19 10:51 ` [Intel-gfx] " Jani Nikula 2019-12-19 13:27 ` Manna, Animesh 2019-12-19 13:27 ` [Intel-gfx] " Manna, Animesh 2019-12-19 12:33 ` Ville Syrjälä 2019-12-19 12:33 ` [Intel-gfx] " Ville Syrjälä 2019-12-19 13:31 ` Manna, Animesh 2019-12-19 13:31 ` [Intel-gfx] " Manna, Animesh 2019-12-23 16:45 ` [PATCH v3 " Animesh Manna 2019-12-23 16:45 ` [Intel-gfx] " Animesh Manna 2019-12-18 15:13 ` [PATCH v2 4/9] drm/i915/dp: Preparation for DP phy compliance auto test Animesh Manna 2019-12-18 15:13 ` [Intel-gfx] " Animesh Manna 2019-12-18 15:13 ` [PATCH v2 5/9] drm/i915/dsb: Send uevent to testapp Animesh Manna 2019-12-18 15:13 ` [Intel-gfx] " Animesh Manna 2019-12-18 15:13 ` [PATCH v2 6/9] drm/i915/dp: Add debugfs entry for DP phy compliance Animesh Manna 2019-12-18 15:13 ` [Intel-gfx] " Animesh Manna 2019-12-18 15:13 ` Animesh Manna [this message] 2019-12-18 15:13 ` [Intel-gfx] [PATCH v2 7/9] drm/i915/dp: Register definition for DP compliance register Animesh Manna 2019-12-18 15:13 ` [PATCH v2 8/9] drm/i915/dp: Update the pattern as per request Animesh Manna 2019-12-18 15:13 ` [Intel-gfx] " Animesh Manna 2019-12-18 15:13 ` [PATCH v2 9/9] drm/i915/dp: [FIXME] Program vswing, pre-emphasis, test-pattern Animesh Manna 2019-12-18 15:13 ` [Intel-gfx] " Animesh Manna 2019-12-18 18:42 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for DP Phy compliance auto test Patchwork 2019-12-18 18:44 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2019-12-18 19:11 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2019-12-20 4:31 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork 2019-12-23 19:33 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for DP Phy compliance auto test (rev4) Patchwork
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