From: Andre Przywara <andre.przywara@arm.com> To: Maxime Ripard <mripard@kernel.org>, Chen-Yu Tsai <wens@csie.org> Cc: Mark Rutland <mark.rutland@arm.com>, Rob Herring <robh+dt@kernel.org>, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Icenowy Zheng <icenowy@aosc.io> Subject: [PATCH 3/3] ARM: dts: sun8i: R40: Add SPI controllers nodes and pinmuxes Date: Thu, 2 Jan 2020 01:26:57 +0000 [thread overview] Message-ID: <20200102012657.9278-4-andre.przywara@arm.com> (raw) In-Reply-To: <20200102012657.9278-1-andre.przywara@arm.com> The Allwinner R40 SoC contains four SPI controllers, using the newer sun6i design (but at the legacy addresses). The controller seems to be fully compatible to the A64 one, so no driver changes are necessary. The first three controller can be used on two sets of pins, but SPI3 is only routed to one set on Port A. Tested by connecting a SPI flash to a Bananapi M2 Berry on the SPI0 PortC header pins. Signed-off-by: Andre Przywara <andre.przywara@arm.com> --- arch/arm/boot/dts/sun8i-r40.dtsi | 89 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 89 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index 8dcbc4465fbb..af437391dcf4 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -418,6 +418,41 @@ bias-pull-up; }; + spi0_pc_pins: spi0-pc-pins { + pins = "PC0", "PC1", "PC2", "PC23"; + function = "spi0"; + }; + + spi0_pi_pins: spi0-pi-pins { + pins = "PI10", "PI11", "PI12", "PI13", "PI14"; + function = "spi0"; + }; + + spi1_pa_pins: spi1-pa-pins { + pins = "PA0", "PA1", "PA2", "PA3", "PA4"; + function = "spi1"; + }; + + spi1_pi_pins: spi1-pi-pins { + pins = "PI15", "PI16", "PI17", "PI18", "PI19"; + function = "spi1"; + }; + + spi2_pb_pins: spi2-pb-pins { + pins = "PB13", "PB14", "PB15", "PB16", "PB17"; + function = "spi2"; + }; + + spi2_pc_pins: spi2-pc-pins { + pins = "PC19", "PC20", "PC21", "PC22"; + function = "spi2"; + }; + + spi3_pins: spi3-pins { + pins = "PA5", "PA6", "PA7", "PA8", "PA9"; + function = "spi3"; + }; + uart0_pb_pins: uart0-pb-pins { pins = "PB22", "PB23"; function = "uart0"; @@ -594,6 +629,60 @@ #size-cells = <0>; }; + spi0: spi@1c05000 { + compatible = "allwinner,sun8i-r40-spi", + "allwinner,sun8i-h3-spi"; + reg = <0x01c05000 0x1000>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_SPI0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi1: spi@1c06000 { + compatible = "allwinner,sun8i-r40-spi", + "allwinner,sun8i-h3-spi"; + reg = <0x01c06000 0x1000>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_SPI1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi2: spi@1c07000 { + compatible = "allwinner,sun8i-r40-spi", + "allwinner,sun8i-h3-spi"; + reg = <0x01c07000 0x1000>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_SPI2>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi3: spi@1c0f000 { + compatible = "allwinner,sun8i-r40-spi", + "allwinner,sun8i-h3-spi"; + reg = <0x01c0f000 0x1000>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_SPI3>, <&ccu CLK_SPI3>; + clock-names = "ahb", "mod"; + pinctrl-0 = <&spi3_pins>; + pinctrl-names = "default"; + resets = <&ccu RST_BUS_SPI3>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + ahci: sata@1c18000 { compatible = "allwinner,sun8i-r40-ahci"; reg = <0x01c18000 0x1000>; -- 2.14.5
WARNING: multiple messages have this Message-ID (diff)
From: Andre Przywara <andre.przywara@arm.com> To: Maxime Ripard <mripard@kernel.org>, Chen-Yu Tsai <wens@csie.org> Cc: Mark Rutland <mark.rutland@arm.com>, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Rob Herring <robh+dt@kernel.org>, linux-arm-kernel@lists.infradead.org, Icenowy Zheng <icenowy@aosc.io> Subject: [PATCH 3/3] ARM: dts: sun8i: R40: Add SPI controllers nodes and pinmuxes Date: Thu, 2 Jan 2020 01:26:57 +0000 [thread overview] Message-ID: <20200102012657.9278-4-andre.przywara@arm.com> (raw) In-Reply-To: <20200102012657.9278-1-andre.przywara@arm.com> The Allwinner R40 SoC contains four SPI controllers, using the newer sun6i design (but at the legacy addresses). The controller seems to be fully compatible to the A64 one, so no driver changes are necessary. The first three controller can be used on two sets of pins, but SPI3 is only routed to one set on Port A. Tested by connecting a SPI flash to a Bananapi M2 Berry on the SPI0 PortC header pins. Signed-off-by: Andre Przywara <andre.przywara@arm.com> --- arch/arm/boot/dts/sun8i-r40.dtsi | 89 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 89 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index 8dcbc4465fbb..af437391dcf4 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -418,6 +418,41 @@ bias-pull-up; }; + spi0_pc_pins: spi0-pc-pins { + pins = "PC0", "PC1", "PC2", "PC23"; + function = "spi0"; + }; + + spi0_pi_pins: spi0-pi-pins { + pins = "PI10", "PI11", "PI12", "PI13", "PI14"; + function = "spi0"; + }; + + spi1_pa_pins: spi1-pa-pins { + pins = "PA0", "PA1", "PA2", "PA3", "PA4"; + function = "spi1"; + }; + + spi1_pi_pins: spi1-pi-pins { + pins = "PI15", "PI16", "PI17", "PI18", "PI19"; + function = "spi1"; + }; + + spi2_pb_pins: spi2-pb-pins { + pins = "PB13", "PB14", "PB15", "PB16", "PB17"; + function = "spi2"; + }; + + spi2_pc_pins: spi2-pc-pins { + pins = "PC19", "PC20", "PC21", "PC22"; + function = "spi2"; + }; + + spi3_pins: spi3-pins { + pins = "PA5", "PA6", "PA7", "PA8", "PA9"; + function = "spi3"; + }; + uart0_pb_pins: uart0-pb-pins { pins = "PB22", "PB23"; function = "uart0"; @@ -594,6 +629,60 @@ #size-cells = <0>; }; + spi0: spi@1c05000 { + compatible = "allwinner,sun8i-r40-spi", + "allwinner,sun8i-h3-spi"; + reg = <0x01c05000 0x1000>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_SPI0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi1: spi@1c06000 { + compatible = "allwinner,sun8i-r40-spi", + "allwinner,sun8i-h3-spi"; + reg = <0x01c06000 0x1000>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_SPI1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi2: spi@1c07000 { + compatible = "allwinner,sun8i-r40-spi", + "allwinner,sun8i-h3-spi"; + reg = <0x01c07000 0x1000>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_SPI2>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi3: spi@1c0f000 { + compatible = "allwinner,sun8i-r40-spi", + "allwinner,sun8i-h3-spi"; + reg = <0x01c0f000 0x1000>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_SPI3>, <&ccu CLK_SPI3>; + clock-names = "ahb", "mod"; + pinctrl-0 = <&spi3_pins>; + pinctrl-names = "default"; + resets = <&ccu RST_BUS_SPI3>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + ahci: sata@1c18000 { compatible = "allwinner,sun8i-r40-ahci"; reg = <0x01c18000 0x1000>; -- 2.14.5 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-01-02 1:27 UTC|newest] Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-01-02 1:26 [PATCH 0/3] ARM: dts: sun8i: R40: DT fixes and updates Andre Przywara 2020-01-02 1:26 ` Andre Przywara 2020-01-02 1:26 ` [PATCH 1/3] ARM: dts: sun8i: R40: Upgrade GICC reg size to 8K Andre Przywara 2020-01-02 1:26 ` Andre Przywara 2020-01-02 9:31 ` Maxime Ripard 2020-01-02 9:31 ` Maxime Ripard 2020-01-02 1:26 ` [PATCH 2/3] ARM: dts: sun8i: R40: Add PMU node Andre Przywara 2020-01-02 1:26 ` Andre Przywara 2020-01-02 9:32 ` Maxime Ripard 2020-01-02 9:32 ` Maxime Ripard 2020-01-02 1:26 ` Andre Przywara [this message] 2020-01-02 1:26 ` [PATCH 3/3] ARM: dts: sun8i: R40: Add SPI controllers nodes and pinmuxes Andre Przywara 2020-01-02 9:57 ` Maxime Ripard 2020-01-02 9:57 ` Maxime Ripard 2020-01-02 10:41 ` Andre Przywara 2020-01-02 10:41 ` Andre Przywara 2020-01-02 10:54 ` Chen-Yu Tsai 2020-01-02 10:54 ` Chen-Yu Tsai 2020-01-04 10:04 ` Maxime Ripard 2020-01-04 10:04 ` Maxime Ripard 2020-01-05 16:40 ` André Przywara 2020-01-05 16:40 ` André Przywara 2020-01-05 18:28 ` Maxime Ripard 2020-01-05 18:28 ` Maxime Ripard
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