From: Maxime Ripard <mripard@kernel.org>
To: Andre Przywara <andre.przywara@arm.com>
Cc: Chen-Yu Tsai <wens@csie.org>, Mark Rutland <mark.rutland@arm.com>,
Rob Herring <robh+dt@kernel.org>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com,
Icenowy Zheng <icenowy@aosc.io>
Subject: Re: [PATCH 2/3] ARM: dts: sun8i: R40: Add PMU node
Date: Thu, 2 Jan 2020 10:32:11 +0100 [thread overview]
Message-ID: <20200102093211.a5hl7hxfqpkvdg6g@gilmour.lan> (raw)
In-Reply-To: <20200102012657.9278-3-andre.przywara@arm.com>
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On Thu, Jan 02, 2020 at 01:26:56AM +0000, Andre Przywara wrote:
> The ARM Cortex-A7 cores used in the Allwinner R40 SoC have their usual
> Performance Monitoring Unit (PMU), which allows perf to use hardware
> events.
> The SoC integrator just needs to connect each per-core interrupt line
> to the GIC. The R40 manual does not really mention those IRQ lines, but
> experimentation in U-Boot shows that interrupts 152-155 are connected to
> the four cores (similar to the A20).
>
> Tested on a Bananapi M2 Berry, with perf and taskset to confirm the
> association between cores and interrupts.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Applied, thanks!
Maxime
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WARNING: multiple messages have this Message-ID (diff)
From: Maxime Ripard <mripard@kernel.org>
To: Andre Przywara <andre.przywara@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>,
devicetree@vger.kernel.org, linux-sunxi@googlegroups.com,
linux-kernel@vger.kernel.org, Chen-Yu Tsai <wens@csie.org>,
Rob Herring <robh+dt@kernel.org>,
linux-arm-kernel@lists.infradead.org,
Icenowy Zheng <icenowy@aosc.io>
Subject: Re: [PATCH 2/3] ARM: dts: sun8i: R40: Add PMU node
Date: Thu, 2 Jan 2020 10:32:11 +0100 [thread overview]
Message-ID: <20200102093211.a5hl7hxfqpkvdg6g@gilmour.lan> (raw)
In-Reply-To: <20200102012657.9278-3-andre.przywara@arm.com>
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On Thu, Jan 02, 2020 at 01:26:56AM +0000, Andre Przywara wrote:
> The ARM Cortex-A7 cores used in the Allwinner R40 SoC have their usual
> Performance Monitoring Unit (PMU), which allows perf to use hardware
> events.
> The SoC integrator just needs to connect each per-core interrupt line
> to the GIC. The R40 manual does not really mention those IRQ lines, but
> experimentation in U-Boot shows that interrupts 152-155 are connected to
> the four cores (similar to the A20).
>
> Tested on a Bananapi M2 Berry, with perf and taskset to confirm the
> association between cores and interrupts.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Applied, thanks!
Maxime
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next prev parent reply other threads:[~2020-01-02 9:32 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-02 1:26 [PATCH 0/3] ARM: dts: sun8i: R40: DT fixes and updates Andre Przywara
2020-01-02 1:26 ` Andre Przywara
2020-01-02 1:26 ` [PATCH 1/3] ARM: dts: sun8i: R40: Upgrade GICC reg size to 8K Andre Przywara
2020-01-02 1:26 ` Andre Przywara
2020-01-02 9:31 ` Maxime Ripard
2020-01-02 9:31 ` Maxime Ripard
2020-01-02 1:26 ` [PATCH 2/3] ARM: dts: sun8i: R40: Add PMU node Andre Przywara
2020-01-02 1:26 ` Andre Przywara
2020-01-02 9:32 ` Maxime Ripard [this message]
2020-01-02 9:32 ` Maxime Ripard
2020-01-02 1:26 ` [PATCH 3/3] ARM: dts: sun8i: R40: Add SPI controllers nodes and pinmuxes Andre Przywara
2020-01-02 1:26 ` Andre Przywara
2020-01-02 9:57 ` Maxime Ripard
2020-01-02 9:57 ` Maxime Ripard
2020-01-02 10:41 ` Andre Przywara
2020-01-02 10:41 ` Andre Przywara
2020-01-02 10:54 ` Chen-Yu Tsai
2020-01-02 10:54 ` Chen-Yu Tsai
2020-01-04 10:04 ` Maxime Ripard
2020-01-04 10:04 ` Maxime Ripard
2020-01-05 16:40 ` André Przywara
2020-01-05 16:40 ` André Przywara
2020-01-05 18:28 ` Maxime Ripard
2020-01-05 18:28 ` Maxime Ripard
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