From: Atish Patra <atish.patra@wdc.com> To: linux-kernel@vger.kernel.org Cc: Atish Patra <atish.patra@wdc.com>, Albert Ou <aou@eecs.berkeley.edu>, Allison Randal <allison@lohutok.net>, Anup Patel <anup@brainfault.org>, Borislav Petkov <bp@suse.de>, Daniel Lezcano <daniel.lezcano@linaro.org>, "Eric W. Biederman" <ebiederm@xmission.com>, Geert Uytterhoeven <geert@linux-m68k.org>, Heiko Carstens <heiko.carstens@de.ibm.com>, Jason Cooper <jason@lakedaemon.net>, Kees Cook <keescook@chromium.org>, linux-riscv@lists.infradead.org, Mao Han <han_mao@c-sky.com>, Marc Zyngier <maz@kernel.org>, Marek Szyprowski <m.szyprowski@samsung.com>, Michael Ellerman <mpe@ellerman.id.au>, Mike Rapoport <rppt@linux.ibm.com>, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Thomas Gleixner <tglx@linutronix.de>, Vincent Chen <vincent.chen@sifive.com> Subject: [PATCH v8 00/11] Add support for SBI v0.2 and CPU hotplug Date: Tue, 11 Feb 2020 17:48:11 -0800 [thread overview] Message-ID: <20200212014822.28684-1-atish.patra@wdc.com> (raw) The Supervisor Binary Interface(SBI) specification[1] now defines a base extension that provides extendability to add future extensions while maintaining backward compatibility with previous versions. The new version is defined as 0.2 and older version is marked as 0.1. This series adds support v0.2 and a unified calling convention implementation between 0.1 and 0.2. It also add other SBI v0.2 functionality defined in [2]. The base support for SBI v0.2 is already available in OpenSBI v0.5. It also adds SBI HSM extension and cpu-hotplug support for RISC-V which requires additional patches[3] in OpenSBI. [1] https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc [2] https://github.com/riscv/riscv-sbi-doc/pull/27 [3] http://lists.infradead.org/pipermail/opensbi/2020-January/001050.html The patches are also available in following github repositery. OpenSBI : https://github.com/atishp04/opensbi/tree/sbi_hsm_v1 Linux Kernel: https://github.com/atishp04/linux/tree/sbi_v0.2_v8 Changes from v7->v8: 1. Refactored to code to have modular cpu_ops calls. 2. Refactored HSM extension from sbi.c to cpu_ops_sbi.c. 3. Fix plic driver to handle cpu hotplug. Changes from v6->v7: 1. Rebased on v5.5 2. Fixed few compilation issues for !CONFIG_SMP and !CONFIG_RISCV_SBI 3. Added SBI HSM extension 4. Add CPU hotplug support Changes from v5->v6 1. Fixed few compilation issues around config. 2. Fixed hart mask generation issues for RFENCE & IPI extensions. Changes from v4->v5 1. Fixed few minor comments related to static & inline. 2. Make sure that every patch is boot tested individually. Changes from v3->v4. 1. Rebased on for-next. 2. Fixed issuses with checkpatch --strict. 3. Unfied all IPI/fence related functions. 4. Added Hfence related SBI calls. Changes from v2->v3. 1. Moved v0.1 extensions to a new config. 2. Added support for relacement extensions of v0.1 extensions. Changes from v1->v2 1. Removed the legacy calling convention. 2. Moved all SBI related calls to sbi.c. 3. Moved all SBI related macros to uapi. Atish Patra (11): RISC-V: Mark existing SBI as 0.1 SBI. RISC-V: Add basic support for SBI v0.2 RISC-V: Add SBI v0.2 extension definitions RISC-V: Introduce a new config for SBI v0.1 RISC-V: Implement new SBI v0.2 extensions RISC-V: Move relocate and few other functions out of __init RISC-V: Add cpu_ops and modify default booting method RISC-V: Add SBI HSM extension RISC-V: Add supported for ordered booting method using HSM irqchip/sifive-plic: Initialize the plic handler when cpu comes online RISC-V: Support cpu hotplug arch/riscv/Kconfig | 19 +- arch/riscv/include/asm/cpu_ops.h | 46 +++ arch/riscv/include/asm/sbi.h | 194 ++++++---- arch/riscv/include/asm/smp.h | 24 ++ arch/riscv/kernel/Makefile | 6 + arch/riscv/kernel/cpu-hotplug.c | 87 +++++ arch/riscv/kernel/cpu_ops.c | 48 +++ arch/riscv/kernel/cpu_ops_sbi.c | 113 ++++++ arch/riscv/kernel/cpu_ops_spinwait.c | 42 +++ arch/riscv/kernel/head.S | 179 +++++---- arch/riscv/kernel/sbi.c | 524 ++++++++++++++++++++++++++- arch/riscv/kernel/setup.c | 24 +- arch/riscv/kernel/smpboot.c | 56 +-- arch/riscv/kernel/traps.c | 2 +- arch/riscv/kernel/vmlinux.lds.S | 5 +- drivers/irqchip/irq-sifive-plic.c | 34 +- include/linux/cpuhotplug.h | 1 + 17 files changed, 1227 insertions(+), 177 deletions(-) create mode 100644 arch/riscv/include/asm/cpu_ops.h create mode 100644 arch/riscv/kernel/cpu-hotplug.c create mode 100644 arch/riscv/kernel/cpu_ops.c create mode 100644 arch/riscv/kernel/cpu_ops_sbi.c create mode 100644 arch/riscv/kernel/cpu_ops_spinwait.c -- 2.24.0
WARNING: multiple messages have this Message-ID (diff)
From: Atish Patra <atish.patra@wdc.com> To: linux-kernel@vger.kernel.org Cc: Albert Ou <aou@eecs.berkeley.edu>, Jason Cooper <jason@lakedaemon.net>, Vincent Chen <vincent.chen@sifive.com>, Michael Ellerman <mpe@ellerman.id.au>, Anup Patel <anup@brainfault.org>, Daniel Lezcano <daniel.lezcano@linaro.org>, Heiko Carstens <heiko.carstens@de.ibm.com>, Mike Rapoport <rppt@linux.ibm.com>, Atish Patra <atish.patra@wdc.com>, Mao Han <han_mao@c-sky.com>, Geert Uytterhoeven <geert@linux-m68k.org>, "Eric W. Biederman" <ebiederm@xmission.com>, Paul Walmsley <paul.walmsley@sifive.com>, Marc Zyngier <maz@kernel.org>, Marek Szyprowski <m.szyprowski@samsung.com>, Palmer Dabbelt <palmer@dabbelt.com>, linux-riscv@lists.infradead.org, Borislav Petkov <bp@suse.de>, Thomas Gleixner <tglx@linutronix.de>, Allison Randal <allison@lohutok.net>, Kees Cook <keescook@chromium.org> Subject: [PATCH v8 00/11] Add support for SBI v0.2 and CPU hotplug Date: Tue, 11 Feb 2020 17:48:11 -0800 [thread overview] Message-ID: <20200212014822.28684-1-atish.patra@wdc.com> (raw) The Supervisor Binary Interface(SBI) specification[1] now defines a base extension that provides extendability to add future extensions while maintaining backward compatibility with previous versions. The new version is defined as 0.2 and older version is marked as 0.1. This series adds support v0.2 and a unified calling convention implementation between 0.1 and 0.2. It also add other SBI v0.2 functionality defined in [2]. The base support for SBI v0.2 is already available in OpenSBI v0.5. It also adds SBI HSM extension and cpu-hotplug support for RISC-V which requires additional patches[3] in OpenSBI. [1] https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc [2] https://github.com/riscv/riscv-sbi-doc/pull/27 [3] http://lists.infradead.org/pipermail/opensbi/2020-January/001050.html The patches are also available in following github repositery. OpenSBI : https://github.com/atishp04/opensbi/tree/sbi_hsm_v1 Linux Kernel: https://github.com/atishp04/linux/tree/sbi_v0.2_v8 Changes from v7->v8: 1. Refactored to code to have modular cpu_ops calls. 2. Refactored HSM extension from sbi.c to cpu_ops_sbi.c. 3. Fix plic driver to handle cpu hotplug. Changes from v6->v7: 1. Rebased on v5.5 2. Fixed few compilation issues for !CONFIG_SMP and !CONFIG_RISCV_SBI 3. Added SBI HSM extension 4. Add CPU hotplug support Changes from v5->v6 1. Fixed few compilation issues around config. 2. Fixed hart mask generation issues for RFENCE & IPI extensions. Changes from v4->v5 1. Fixed few minor comments related to static & inline. 2. Make sure that every patch is boot tested individually. Changes from v3->v4. 1. Rebased on for-next. 2. Fixed issuses with checkpatch --strict. 3. Unfied all IPI/fence related functions. 4. Added Hfence related SBI calls. Changes from v2->v3. 1. Moved v0.1 extensions to a new config. 2. Added support for relacement extensions of v0.1 extensions. Changes from v1->v2 1. Removed the legacy calling convention. 2. Moved all SBI related calls to sbi.c. 3. Moved all SBI related macros to uapi. Atish Patra (11): RISC-V: Mark existing SBI as 0.1 SBI. RISC-V: Add basic support for SBI v0.2 RISC-V: Add SBI v0.2 extension definitions RISC-V: Introduce a new config for SBI v0.1 RISC-V: Implement new SBI v0.2 extensions RISC-V: Move relocate and few other functions out of __init RISC-V: Add cpu_ops and modify default booting method RISC-V: Add SBI HSM extension RISC-V: Add supported for ordered booting method using HSM irqchip/sifive-plic: Initialize the plic handler when cpu comes online RISC-V: Support cpu hotplug arch/riscv/Kconfig | 19 +- arch/riscv/include/asm/cpu_ops.h | 46 +++ arch/riscv/include/asm/sbi.h | 194 ++++++---- arch/riscv/include/asm/smp.h | 24 ++ arch/riscv/kernel/Makefile | 6 + arch/riscv/kernel/cpu-hotplug.c | 87 +++++ arch/riscv/kernel/cpu_ops.c | 48 +++ arch/riscv/kernel/cpu_ops_sbi.c | 113 ++++++ arch/riscv/kernel/cpu_ops_spinwait.c | 42 +++ arch/riscv/kernel/head.S | 179 +++++---- arch/riscv/kernel/sbi.c | 524 ++++++++++++++++++++++++++- arch/riscv/kernel/setup.c | 24 +- arch/riscv/kernel/smpboot.c | 56 +-- arch/riscv/kernel/traps.c | 2 +- arch/riscv/kernel/vmlinux.lds.S | 5 +- drivers/irqchip/irq-sifive-plic.c | 34 +- include/linux/cpuhotplug.h | 1 + 17 files changed, 1227 insertions(+), 177 deletions(-) create mode 100644 arch/riscv/include/asm/cpu_ops.h create mode 100644 arch/riscv/kernel/cpu-hotplug.c create mode 100644 arch/riscv/kernel/cpu_ops.c create mode 100644 arch/riscv/kernel/cpu_ops_sbi.c create mode 100644 arch/riscv/kernel/cpu_ops_spinwait.c -- 2.24.0
next reply other threads:[~2020-02-12 1:51 UTC|newest] Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-02-12 1:48 Atish Patra [this message] 2020-02-12 1:48 ` [PATCH v8 00/11] Add support for SBI v0.2 and CPU hotplug Atish Patra 2020-02-12 1:48 ` [PATCH v8 01/11] RISC-V: Mark existing SBI as 0.1 SBI Atish Patra 2020-02-12 1:48 ` Atish Patra 2020-02-12 1:48 ` [PATCH v8 02/11] RISC-V: Add basic support for SBI v0.2 Atish Patra 2020-02-12 1:48 ` Atish Patra 2020-02-12 1:48 ` [PATCH v8 03/11] RISC-V: Add SBI v0.2 extension definitions Atish Patra 2020-02-12 1:48 ` Atish Patra 2020-02-12 1:48 ` [PATCH v8 04/11] RISC-V: Introduce a new config for SBI v0.1 Atish Patra 2020-02-12 1:48 ` Atish Patra 2020-02-12 1:48 ` [PATCH v8 05/11] RISC-V: Implement new SBI v0.2 extensions Atish Patra 2020-02-12 1:48 ` Atish Patra 2020-02-12 1:48 ` [PATCH v8 06/11] RISC-V: Move relocate and few other functions out of __init Atish Patra 2020-02-12 1:48 ` Atish Patra 2020-02-12 4:18 ` Anup Patel 2020-02-12 4:18 ` Anup Patel 2020-02-12 18:58 ` Atish Patra 2020-02-12 18:58 ` Atish Patra 2020-02-12 1:48 ` [PATCH v8 07/11] RISC-V: Add cpu_ops and modify default booting method Atish Patra 2020-02-12 1:48 ` Atish Patra 2020-02-12 4:28 ` Anup Patel 2020-02-12 4:28 ` Anup Patel 2020-02-12 18:57 ` Atish Patra 2020-02-12 18:57 ` Atish Patra 2020-02-12 1:48 ` [PATCH v8 08/11] RISC-V: Add SBI HSM extension Atish Patra 2020-02-12 1:48 ` Atish Patra 2020-02-12 4:53 ` Anup Patel 2020-02-12 4:53 ` Anup Patel 2020-02-12 19:54 ` Atish Patra 2020-02-12 19:54 ` Atish Patra 2020-02-12 1:48 ` [PATCH v8 09/11] RISC-V: Add supported for ordered booting method using HSM Atish Patra 2020-02-12 1:48 ` Atish Patra 2020-02-12 4:57 ` Anup Patel 2020-02-12 4:57 ` Anup Patel 2020-02-12 1:48 ` [PATCH v8 10/11] irqchip/sifive-plic: Initialize the plic handler when cpu comes online Atish Patra 2020-02-12 1:48 ` Atish Patra 2020-02-12 5:10 ` Anup Patel 2020-02-12 5:10 ` Anup Patel 2020-02-13 11:01 ` Thomas Gleixner 2020-02-13 11:01 ` Thomas Gleixner 2020-02-13 19:01 ` Atish Patra 2020-02-13 19:01 ` Atish Patra 2020-02-12 1:48 ` [PATCH v8 11/11] RISC-V: Support cpu hotplug Atish Patra 2020-02-12 1:48 ` Atish Patra 2020-02-12 5:13 ` Anup Patel 2020-02-12 5:13 ` Anup Patel 2020-02-19 21:48 ` [PATCH v8 00/11] Add support for SBI v0.2 and CPU hotplug Palmer Dabbelt 2020-02-19 21:48 ` Palmer Dabbelt 2020-02-20 1:16 ` Atish Patra 2020-02-20 1:16 ` Atish Patra
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20200212014822.28684-1-atish.patra@wdc.com \ --to=atish.patra@wdc.com \ --cc=allison@lohutok.net \ --cc=anup@brainfault.org \ --cc=aou@eecs.berkeley.edu \ --cc=bp@suse.de \ --cc=daniel.lezcano@linaro.org \ --cc=ebiederm@xmission.com \ --cc=geert@linux-m68k.org \ --cc=han_mao@c-sky.com \ --cc=heiko.carstens@de.ibm.com \ --cc=jason@lakedaemon.net \ --cc=keescook@chromium.org \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-riscv@lists.infradead.org \ --cc=m.szyprowski@samsung.com \ --cc=maz@kernel.org \ --cc=mpe@ellerman.id.au \ --cc=palmer@dabbelt.com \ --cc=paul.walmsley@sifive.com \ --cc=rppt@linux.ibm.com \ --cc=tglx@linutronix.de \ --cc=vincent.chen@sifive.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.