From: Atish Patra <atish.patra@wdc.com> To: linux-kernel@vger.kernel.org Cc: Atish Patra <atish.patra@wdc.com>, Anup Patel <anup@brainfault.org>, Albert Ou <aou@eecs.berkeley.edu>, Allison Randal <allison@lohutok.net>, Borislav Petkov <bp@suse.de>, Daniel Lezcano <daniel.lezcano@linaro.org>, "Eric W. Biederman" <ebiederm@xmission.com>, Geert Uytterhoeven <geert@linux-m68k.org>, Heiko Carstens <heiko.carstens@de.ibm.com>, Jason Cooper <jason@lakedaemon.net>, Kees Cook <keescook@chromium.org>, linux-riscv@lists.infradead.org, Mao Han <han_mao@c-sky.com>, Marc Zyngier <maz@kernel.org>, Marek Szyprowski <m.szyprowski@samsung.com>, Michael Ellerman <mpe@ellerman.id.au>, Mike Rapoport <rppt@linux.ibm.com>, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Thomas Gleixner <tglx@linutronix.de>, Vincent Chen <vincent.chen@sifive.com> Subject: [PATCH v8 04/11] RISC-V: Introduce a new config for SBI v0.1 Date: Tue, 11 Feb 2020 17:48:15 -0800 [thread overview] Message-ID: <20200212014822.28684-5-atish.patra@wdc.com> (raw) In-Reply-To: <20200212014822.28684-1-atish.patra@wdc.com> We now have SBI v0.2 which is more scalable and extendable to handle future needs for RISC-V supervisor interfaces. Introduce a new config and move all SBI v0.1 code under that config. This allows to implement the new replacement SBI extensions cleanly and remove v0.1 extensions easily in future. Currently, the config is enabled by default. Once all M-mode software, with v0.1, is no longer in use, this config option and all relevant code can be easily removed. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Anup Patel <anup@brainfault.org> --- arch/riscv/Kconfig | 7 ++ arch/riscv/include/asm/sbi.h | 2 + arch/riscv/kernel/sbi.c | 137 +++++++++++++++++++++++++++++------ 3 files changed, 122 insertions(+), 24 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index fa7dc03459e7..2afe1382dc36 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -307,6 +307,13 @@ config SECCOMP and the task is only allowed to execute a few safe syscalls defined by each seccomp mode. +config RISCV_SBI_V01 + bool "SBI v0.1 support" + default y + depends on RISCV_SBI + help + This config allows kernel to use SBI v0.1 APIs. This will be + deprecated in future once legacy M-mode software are no longer in use. endmenu menu "Boot options" diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index e478368a47f3..4d67bef8f894 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -11,6 +11,7 @@ #ifdef CONFIG_RISCV_SBI enum sbi_ext_id { +#ifdef CONFIG_RISCV_SBI_V01 SBI_EXT_0_1_SET_TIMER = 0x0, SBI_EXT_0_1_CONSOLE_PUTCHAR = 0x1, SBI_EXT_0_1_CONSOLE_GETCHAR = 0x2, @@ -20,6 +21,7 @@ enum sbi_ext_id { SBI_EXT_0_1_REMOTE_SFENCE_VMA = 0x6, SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7, SBI_EXT_0_1_SHUTDOWN = 0x8, +#endif SBI_EXT_BASE = 0x10, SBI_EXT_TIME = 0x54494D45, SBI_EXT_IPI = 0x735049, diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c index 33632e7f91da..265637cb5eb0 100644 --- a/arch/riscv/kernel/sbi.c +++ b/arch/riscv/kernel/sbi.c @@ -13,6 +13,13 @@ unsigned long sbi_spec_version = SBI_SPEC_VERSION_DEFAULT; EXPORT_SYMBOL(sbi_spec_version); +static void (*__sbi_set_timer)(uint64_t stime); +static int (*__sbi_send_ipi)(const unsigned long *hart_mask); +static int (*__sbi_rfence)(int fid, const unsigned long *hart_mask, + unsigned long hbase, unsigned long start, + unsigned long size, unsigned long arg4, + unsigned long arg5); + struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0, unsigned long arg1, unsigned long arg2, unsigned long arg3, unsigned long arg4, @@ -57,6 +64,7 @@ static int sbi_err_map_linux_errno(int err) }; } +#ifdef CONFIG_RISCV_SBI_V01 /** * sbi_console_putchar() - Writes given character to the console device. * @ch: The data to be written to the console. @@ -85,41 +93,115 @@ int sbi_console_getchar(void) EXPORT_SYMBOL(sbi_console_getchar); /** - * sbi_set_timer() - Program the timer for next timer event. - * @stime_value: The value after which next timer event should fire. + * sbi_shutdown() - Remove all the harts from executing supervisor code. * * Return: None */ -void sbi_set_timer(uint64_t stime_value) +void sbi_shutdown(void) { -#if __riscv_xlen == 32 - sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value, - stime_value >> 32, 0, 0, 0, 0); -#else - sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value, 0, 0, 0, 0, 0); -#endif + sbi_ecall(SBI_EXT_0_1_SHUTDOWN, 0, 0, 0, 0, 0, 0, 0); } EXPORT_SYMBOL(sbi_set_timer); /** - * sbi_shutdown() - Remove all the harts from executing supervisor code. + * sbi_clear_ipi() - Clear any pending IPIs for the calling hart. * * Return: None */ -void sbi_shutdown(void) +void sbi_clear_ipi(void) { - sbi_ecall(SBI_EXT_0_1_SHUTDOWN, 0, 0, 0, 0, 0, 0, 0); + sbi_ecall(SBI_EXT_0_1_CLEAR_IPI, 0, 0, 0, 0, 0, 0, 0); } EXPORT_SYMBOL(sbi_shutdown); /** - * sbi_clear_ipi() - Clear any pending IPIs for the calling hart. + * sbi_set_timer_v01() - Program the timer for next timer event. + * @stime_value: The value after which next timer event should fire. * * Return: None */ -void sbi_clear_ipi(void) +static void __sbi_set_timer_v01(uint64_t stime_value) { - sbi_ecall(SBI_EXT_0_1_CLEAR_IPI, 0, 0, 0, 0, 0, 0, 0); +#if __riscv_xlen == 32 + sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value, + stime_value >> 32, 0, 0, 0, 0); +#else + sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value, 0, 0, 0, 0, 0); +#endif +} + +static int __sbi_send_ipi_v01(const unsigned long *hart_mask) +{ + sbi_ecall(SBI_EXT_0_1_SEND_IPI, 0, (unsigned long)hart_mask, + 0, 0, 0, 0, 0); + return 0; +} + +static int __sbi_rfence_v01(int fid, const unsigned long *hart_mask, + unsigned long hbase, unsigned long start, + unsigned long size, unsigned long arg4, + unsigned long arg5) +{ + int result = 0; + + /* v0.2 function IDs are equivalent to v0.1 extension IDs */ + switch (fid) { + case SBI_EXT_RFENCE_REMOTE_FENCE_I: + sbi_ecall(SBI_EXT_0_1_REMOTE_FENCE_I, 0, + (unsigned long)hart_mask, 0, 0, 0, 0, 0); + break; + case SBI_EXT_RFENCE_REMOTE_SFENCE_VMA: + sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA, 0, + (unsigned long)hart_mask, start, size, + 0, 0, 0); + break; + case SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID: + sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, 0, + (unsigned long)hart_mask, start, size, + arg4, 0, 0); + break; + default: + pr_err("SBI call [%d]not supported in SBI v0.1\n", fid); + result = -EINVAL; + } + + return result; +} +#else +static void __sbi_set_timer_v01(uint64_t stime_value) +{ + pr_warn("Timer extension is not available in SBI v%lu.%lu\n", + sbi_major_version(), sbi_minor_version()); +} +static int __sbi_send_ipi_v01(const unsigned long *hart_mask) +{ + pr_warn("IPI extension is not available in SBI v%lu.%lu\n", + sbi_major_version(), sbi_minor_version()); + + return 0; +} +static int __sbi_rfence_v01(int fid, + const unsigned long *hart_mask, + unsigned long hbase, unsigned long start, + unsigned long size, unsigned long arg4, + unsigned long arg5) +{ + pr_warn("remote fence extension is not available in SBI v%lu.%lu\n", + sbi_major_version(), sbi_minor_version()); + + return 0; +} +#endif /* CONFIG_RISCV_SBI_V01 */ + +/** + * sbi_set_timer() - Program the timer for next timer event. + * @stime_value: The value after which next timer event should fire. + * + * Return: None + */ +void sbi_set_timer(uint64_t stime_value) +{ + __sbi_set_timer(stime_value); } /** @@ -130,11 +212,11 @@ void sbi_clear_ipi(void) */ void sbi_send_ipi(const unsigned long *hart_mask) { - sbi_ecall(SBI_EXT_0_1_SEND_IPI, 0, (unsigned long)hart_mask, - 0, 0, 0, 0, 0); + __sbi_send_ipi(hart_mask); } EXPORT_SYMBOL(sbi_send_ipi); + /** * sbi_remote_fence_i() - Execute FENCE.I instruction on given remote harts. * @hart_mask: A cpu mask containing all the target harts. @@ -143,8 +225,8 @@ EXPORT_SYMBOL(sbi_send_ipi); */ void sbi_remote_fence_i(const unsigned long *hart_mask) { - sbi_ecall(SBI_EXT_0_1_REMOTE_FENCE_I, 0, (unsigned long)hart_mask, - 0, 0, 0, 0, 0); + __sbi_rfence(SBI_EXT_RFENCE_REMOTE_FENCE_I, + hart_mask, 0, 0, 0, 0, 0); } EXPORT_SYMBOL(sbi_remote_fence_i); @@ -161,8 +243,8 @@ void sbi_remote_sfence_vma(const unsigned long *hart_mask, unsigned long start, unsigned long size) { - sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA, 0, - (unsigned long)hart_mask, start, size, 0, 0, 0); + __sbi_rfence(SBI_EXT_RFENCE_REMOTE_SFENCE_VMA, + hart_mask, 0, start, size, 0, 0); } EXPORT_SYMBOL(sbi_remote_sfence_vma); @@ -182,8 +264,8 @@ void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask, unsigned long size, unsigned long asid) { - sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, 0, - (unsigned long)hart_mask, start, size, asid, 0, 0); + __sbi_rfence(SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID, + hart_mask, 0, start, size, asid, 0); } EXPORT_SYMBOL(sbi_remote_sfence_vma_asid); @@ -249,8 +331,15 @@ int __init sbi_init(void) pr_info("SBI specification v%lu.%lu detected\n", sbi_major_version(), sbi_minor_version()); - if (!sbi_spec_is_0_1()) + + if (!sbi_spec_is_0_1()) { pr_info("SBI implementation ID=0x%lx Version=0x%lx\n", sbi_get_firmware_id(), sbi_get_firmware_version()); + } + + __sbi_set_timer = __sbi_set_timer_v01; + __sbi_send_ipi = __sbi_send_ipi_v01; + __sbi_rfence = __sbi_rfence_v01; + return 0; } -- 2.24.0
WARNING: multiple messages have this Message-ID (diff)
From: Atish Patra <atish.patra@wdc.com> To: linux-kernel@vger.kernel.org Cc: Albert Ou <aou@eecs.berkeley.edu>, Jason Cooper <jason@lakedaemon.net>, Vincent Chen <vincent.chen@sifive.com>, Michael Ellerman <mpe@ellerman.id.au>, Anup Patel <anup@brainfault.org>, Daniel Lezcano <daniel.lezcano@linaro.org>, Heiko Carstens <heiko.carstens@de.ibm.com>, Mike Rapoport <rppt@linux.ibm.com>, Atish Patra <atish.patra@wdc.com>, Mao Han <han_mao@c-sky.com>, Geert Uytterhoeven <geert@linux-m68k.org>, "Eric W. Biederman" <ebiederm@xmission.com>, Paul Walmsley <paul.walmsley@sifive.com>, Marc Zyngier <maz@kernel.org>, Marek Szyprowski <m.szyprowski@samsung.com>, Palmer Dabbelt <palmer@dabbelt.com>, linux-riscv@lists.infradead.org, Borislav Petkov <bp@suse.de>, Thomas Gleixner <tglx@linutronix.de>, Allison Randal <allison@lohutok.net>, Kees Cook <keescook@chromium.org> Subject: [PATCH v8 04/11] RISC-V: Introduce a new config for SBI v0.1 Date: Tue, 11 Feb 2020 17:48:15 -0800 [thread overview] Message-ID: <20200212014822.28684-5-atish.patra@wdc.com> (raw) In-Reply-To: <20200212014822.28684-1-atish.patra@wdc.com> We now have SBI v0.2 which is more scalable and extendable to handle future needs for RISC-V supervisor interfaces. Introduce a new config and move all SBI v0.1 code under that config. This allows to implement the new replacement SBI extensions cleanly and remove v0.1 extensions easily in future. Currently, the config is enabled by default. Once all M-mode software, with v0.1, is no longer in use, this config option and all relevant code can be easily removed. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Anup Patel <anup@brainfault.org> --- arch/riscv/Kconfig | 7 ++ arch/riscv/include/asm/sbi.h | 2 + arch/riscv/kernel/sbi.c | 137 +++++++++++++++++++++++++++++------ 3 files changed, 122 insertions(+), 24 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index fa7dc03459e7..2afe1382dc36 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -307,6 +307,13 @@ config SECCOMP and the task is only allowed to execute a few safe syscalls defined by each seccomp mode. +config RISCV_SBI_V01 + bool "SBI v0.1 support" + default y + depends on RISCV_SBI + help + This config allows kernel to use SBI v0.1 APIs. This will be + deprecated in future once legacy M-mode software are no longer in use. endmenu menu "Boot options" diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index e478368a47f3..4d67bef8f894 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -11,6 +11,7 @@ #ifdef CONFIG_RISCV_SBI enum sbi_ext_id { +#ifdef CONFIG_RISCV_SBI_V01 SBI_EXT_0_1_SET_TIMER = 0x0, SBI_EXT_0_1_CONSOLE_PUTCHAR = 0x1, SBI_EXT_0_1_CONSOLE_GETCHAR = 0x2, @@ -20,6 +21,7 @@ enum sbi_ext_id { SBI_EXT_0_1_REMOTE_SFENCE_VMA = 0x6, SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7, SBI_EXT_0_1_SHUTDOWN = 0x8, +#endif SBI_EXT_BASE = 0x10, SBI_EXT_TIME = 0x54494D45, SBI_EXT_IPI = 0x735049, diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c index 33632e7f91da..265637cb5eb0 100644 --- a/arch/riscv/kernel/sbi.c +++ b/arch/riscv/kernel/sbi.c @@ -13,6 +13,13 @@ unsigned long sbi_spec_version = SBI_SPEC_VERSION_DEFAULT; EXPORT_SYMBOL(sbi_spec_version); +static void (*__sbi_set_timer)(uint64_t stime); +static int (*__sbi_send_ipi)(const unsigned long *hart_mask); +static int (*__sbi_rfence)(int fid, const unsigned long *hart_mask, + unsigned long hbase, unsigned long start, + unsigned long size, unsigned long arg4, + unsigned long arg5); + struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0, unsigned long arg1, unsigned long arg2, unsigned long arg3, unsigned long arg4, @@ -57,6 +64,7 @@ static int sbi_err_map_linux_errno(int err) }; } +#ifdef CONFIG_RISCV_SBI_V01 /** * sbi_console_putchar() - Writes given character to the console device. * @ch: The data to be written to the console. @@ -85,41 +93,115 @@ int sbi_console_getchar(void) EXPORT_SYMBOL(sbi_console_getchar); /** - * sbi_set_timer() - Program the timer for next timer event. - * @stime_value: The value after which next timer event should fire. + * sbi_shutdown() - Remove all the harts from executing supervisor code. * * Return: None */ -void sbi_set_timer(uint64_t stime_value) +void sbi_shutdown(void) { -#if __riscv_xlen == 32 - sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value, - stime_value >> 32, 0, 0, 0, 0); -#else - sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value, 0, 0, 0, 0, 0); -#endif + sbi_ecall(SBI_EXT_0_1_SHUTDOWN, 0, 0, 0, 0, 0, 0, 0); } EXPORT_SYMBOL(sbi_set_timer); /** - * sbi_shutdown() - Remove all the harts from executing supervisor code. + * sbi_clear_ipi() - Clear any pending IPIs for the calling hart. * * Return: None */ -void sbi_shutdown(void) +void sbi_clear_ipi(void) { - sbi_ecall(SBI_EXT_0_1_SHUTDOWN, 0, 0, 0, 0, 0, 0, 0); + sbi_ecall(SBI_EXT_0_1_CLEAR_IPI, 0, 0, 0, 0, 0, 0, 0); } EXPORT_SYMBOL(sbi_shutdown); /** - * sbi_clear_ipi() - Clear any pending IPIs for the calling hart. + * sbi_set_timer_v01() - Program the timer for next timer event. + * @stime_value: The value after which next timer event should fire. * * Return: None */ -void sbi_clear_ipi(void) +static void __sbi_set_timer_v01(uint64_t stime_value) { - sbi_ecall(SBI_EXT_0_1_CLEAR_IPI, 0, 0, 0, 0, 0, 0, 0); +#if __riscv_xlen == 32 + sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value, + stime_value >> 32, 0, 0, 0, 0); +#else + sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value, 0, 0, 0, 0, 0); +#endif +} + +static int __sbi_send_ipi_v01(const unsigned long *hart_mask) +{ + sbi_ecall(SBI_EXT_0_1_SEND_IPI, 0, (unsigned long)hart_mask, + 0, 0, 0, 0, 0); + return 0; +} + +static int __sbi_rfence_v01(int fid, const unsigned long *hart_mask, + unsigned long hbase, unsigned long start, + unsigned long size, unsigned long arg4, + unsigned long arg5) +{ + int result = 0; + + /* v0.2 function IDs are equivalent to v0.1 extension IDs */ + switch (fid) { + case SBI_EXT_RFENCE_REMOTE_FENCE_I: + sbi_ecall(SBI_EXT_0_1_REMOTE_FENCE_I, 0, + (unsigned long)hart_mask, 0, 0, 0, 0, 0); + break; + case SBI_EXT_RFENCE_REMOTE_SFENCE_VMA: + sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA, 0, + (unsigned long)hart_mask, start, size, + 0, 0, 0); + break; + case SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID: + sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, 0, + (unsigned long)hart_mask, start, size, + arg4, 0, 0); + break; + default: + pr_err("SBI call [%d]not supported in SBI v0.1\n", fid); + result = -EINVAL; + } + + return result; +} +#else +static void __sbi_set_timer_v01(uint64_t stime_value) +{ + pr_warn("Timer extension is not available in SBI v%lu.%lu\n", + sbi_major_version(), sbi_minor_version()); +} +static int __sbi_send_ipi_v01(const unsigned long *hart_mask) +{ + pr_warn("IPI extension is not available in SBI v%lu.%lu\n", + sbi_major_version(), sbi_minor_version()); + + return 0; +} +static int __sbi_rfence_v01(int fid, + const unsigned long *hart_mask, + unsigned long hbase, unsigned long start, + unsigned long size, unsigned long arg4, + unsigned long arg5) +{ + pr_warn("remote fence extension is not available in SBI v%lu.%lu\n", + sbi_major_version(), sbi_minor_version()); + + return 0; +} +#endif /* CONFIG_RISCV_SBI_V01 */ + +/** + * sbi_set_timer() - Program the timer for next timer event. + * @stime_value: The value after which next timer event should fire. + * + * Return: None + */ +void sbi_set_timer(uint64_t stime_value) +{ + __sbi_set_timer(stime_value); } /** @@ -130,11 +212,11 @@ void sbi_clear_ipi(void) */ void sbi_send_ipi(const unsigned long *hart_mask) { - sbi_ecall(SBI_EXT_0_1_SEND_IPI, 0, (unsigned long)hart_mask, - 0, 0, 0, 0, 0); + __sbi_send_ipi(hart_mask); } EXPORT_SYMBOL(sbi_send_ipi); + /** * sbi_remote_fence_i() - Execute FENCE.I instruction on given remote harts. * @hart_mask: A cpu mask containing all the target harts. @@ -143,8 +225,8 @@ EXPORT_SYMBOL(sbi_send_ipi); */ void sbi_remote_fence_i(const unsigned long *hart_mask) { - sbi_ecall(SBI_EXT_0_1_REMOTE_FENCE_I, 0, (unsigned long)hart_mask, - 0, 0, 0, 0, 0); + __sbi_rfence(SBI_EXT_RFENCE_REMOTE_FENCE_I, + hart_mask, 0, 0, 0, 0, 0); } EXPORT_SYMBOL(sbi_remote_fence_i); @@ -161,8 +243,8 @@ void sbi_remote_sfence_vma(const unsigned long *hart_mask, unsigned long start, unsigned long size) { - sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA, 0, - (unsigned long)hart_mask, start, size, 0, 0, 0); + __sbi_rfence(SBI_EXT_RFENCE_REMOTE_SFENCE_VMA, + hart_mask, 0, start, size, 0, 0); } EXPORT_SYMBOL(sbi_remote_sfence_vma); @@ -182,8 +264,8 @@ void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask, unsigned long size, unsigned long asid) { - sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, 0, - (unsigned long)hart_mask, start, size, asid, 0, 0); + __sbi_rfence(SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID, + hart_mask, 0, start, size, asid, 0); } EXPORT_SYMBOL(sbi_remote_sfence_vma_asid); @@ -249,8 +331,15 @@ int __init sbi_init(void) pr_info("SBI specification v%lu.%lu detected\n", sbi_major_version(), sbi_minor_version()); - if (!sbi_spec_is_0_1()) + + if (!sbi_spec_is_0_1()) { pr_info("SBI implementation ID=0x%lx Version=0x%lx\n", sbi_get_firmware_id(), sbi_get_firmware_version()); + } + + __sbi_set_timer = __sbi_set_timer_v01; + __sbi_send_ipi = __sbi_send_ipi_v01; + __sbi_rfence = __sbi_rfence_v01; + return 0; } -- 2.24.0
next prev parent reply other threads:[~2020-02-12 1:52 UTC|newest] Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-02-12 1:48 [PATCH v8 00/11] Add support for SBI v0.2 and CPU hotplug Atish Patra 2020-02-12 1:48 ` Atish Patra 2020-02-12 1:48 ` [PATCH v8 01/11] RISC-V: Mark existing SBI as 0.1 SBI Atish Patra 2020-02-12 1:48 ` Atish Patra 2020-02-12 1:48 ` [PATCH v8 02/11] RISC-V: Add basic support for SBI v0.2 Atish Patra 2020-02-12 1:48 ` Atish Patra 2020-02-12 1:48 ` [PATCH v8 03/11] RISC-V: Add SBI v0.2 extension definitions Atish Patra 2020-02-12 1:48 ` Atish Patra 2020-02-12 1:48 ` Atish Patra [this message] 2020-02-12 1:48 ` [PATCH v8 04/11] RISC-V: Introduce a new config for SBI v0.1 Atish Patra 2020-02-12 1:48 ` [PATCH v8 05/11] RISC-V: Implement new SBI v0.2 extensions Atish Patra 2020-02-12 1:48 ` Atish Patra 2020-02-12 1:48 ` [PATCH v8 06/11] RISC-V: Move relocate and few other functions out of __init Atish Patra 2020-02-12 1:48 ` Atish Patra 2020-02-12 4:18 ` Anup Patel 2020-02-12 4:18 ` Anup Patel 2020-02-12 18:58 ` Atish Patra 2020-02-12 18:58 ` Atish Patra 2020-02-12 1:48 ` [PATCH v8 07/11] RISC-V: Add cpu_ops and modify default booting method Atish Patra 2020-02-12 1:48 ` Atish Patra 2020-02-12 4:28 ` Anup Patel 2020-02-12 4:28 ` Anup Patel 2020-02-12 18:57 ` Atish Patra 2020-02-12 18:57 ` Atish Patra 2020-02-12 1:48 ` [PATCH v8 08/11] RISC-V: Add SBI HSM extension Atish Patra 2020-02-12 1:48 ` Atish Patra 2020-02-12 4:53 ` Anup Patel 2020-02-12 4:53 ` Anup Patel 2020-02-12 19:54 ` Atish Patra 2020-02-12 19:54 ` Atish Patra 2020-02-12 1:48 ` [PATCH v8 09/11] RISC-V: Add supported for ordered booting method using HSM Atish Patra 2020-02-12 1:48 ` Atish Patra 2020-02-12 4:57 ` Anup Patel 2020-02-12 4:57 ` Anup Patel 2020-02-12 1:48 ` [PATCH v8 10/11] irqchip/sifive-plic: Initialize the plic handler when cpu comes online Atish Patra 2020-02-12 1:48 ` Atish Patra 2020-02-12 5:10 ` Anup Patel 2020-02-12 5:10 ` Anup Patel 2020-02-13 11:01 ` Thomas Gleixner 2020-02-13 11:01 ` Thomas Gleixner 2020-02-13 19:01 ` Atish Patra 2020-02-13 19:01 ` Atish Patra 2020-02-12 1:48 ` [PATCH v8 11/11] RISC-V: Support cpu hotplug Atish Patra 2020-02-12 1:48 ` Atish Patra 2020-02-12 5:13 ` Anup Patel 2020-02-12 5:13 ` Anup Patel 2020-02-19 21:48 ` [PATCH v8 00/11] Add support for SBI v0.2 and CPU hotplug Palmer Dabbelt 2020-02-19 21:48 ` Palmer Dabbelt 2020-02-20 1:16 ` Atish Patra 2020-02-20 1:16 ` Atish Patra
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