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From: Thomas Gleixner <tglx@linutronix.de>
To: Atish Patra <atish.patra@wdc.com>, linux-kernel@vger.kernel.org
Cc: Atish Patra <atish.patra@wdc.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Allison Randal <allison@lohutok.net>,
	Anup Patel <anup@brainfault.org>, Borislav Petkov <bp@suse.de>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	"Eric W. Biederman" <ebiederm@xmission.com>,
	Geert Uytterhoeven <geert@linux-m68k.org>,
	Heiko Carstens <heiko.carstens@de.ibm.com>,
	Jason Cooper <jason@lakedaemon.net>,
	Kees Cook <keescook@chromium.org>,
	linux-riscv@lists.infradead.org, Mao Han <han_mao@c-sky.com>,
	Marc Zyngier <maz@kernel.org>,
	Marek Szyprowski <m.szyprowski@samsung.com>,
	Michael Ellerman <mpe@ellerman.id.au>,
	Mike Rapoport <rppt@linux.ibm.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Vincent Chen <vincent.chen@sifive.com>
Subject: Re: [PATCH v8 10/11] irqchip/sifive-plic: Initialize the plic handler when cpu comes online
Date: Thu, 13 Feb 2020 12:01:37 +0100	[thread overview]
Message-ID: <87ftfe3g4u.fsf@nanos.tec.linutronix.de> (raw)
In-Reply-To: <20200212014822.28684-11-atish.patra@wdc.com>

Atish Patra <atish.patra@wdc.com> writes:
  
> +static void plic_handler_init(struct plic_handler *handler, u32 threshold)
> +{
> +	irq_hw_number_t hwirq;
> +
> +	/* priority must be > threshold to trigger an interrupt */
> +	writel(threshold, handler->hart_base + CONTEXT_THRESHOLD);
> +	for (hwirq = 1; hwirq < plic_irqdomain->hwirq_max; hwirq++)
> +		plic_toggle(handler, hwirq, 0);
> +}

> +
> +static int plic_starting_cpu(unsigned int cpu)
> +{
> +	u32 threshold = 0;

Pointless variable. Also you use PLIC_DISABLE_THRESHOLD down below, so
please add a proper define for enable as well.

> +	struct plic_handler *handler = per_cpu_ptr(&plic_handlers, cpu);

        this_cpu_ptr*&...)

The callback is guaranteed to run on the plugged in CPU.

> -			threshold = 0xffffffff;
> +			plic_handler_init(handler, PLIC_DISABLE_THRESHOLD);

Thanks,

        tglx

WARNING: multiple messages have this Message-ID (diff)
From: Thomas Gleixner <tglx@linutronix.de>
To: Atish Patra <atish.patra@wdc.com>, linux-kernel@vger.kernel.org
Cc: Albert Ou <aou@eecs.berkeley.edu>,
	Jason Cooper <jason@lakedaemon.net>,
	Vincent Chen <vincent.chen@sifive.com>,
	Michael Ellerman <mpe@ellerman.id.au>,
	Anup Patel <anup@brainfault.org>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	Heiko Carstens <heiko.carstens@de.ibm.com>,
	Mike Rapoport <rppt@linux.ibm.com>,
	Atish Patra <atish.patra@wdc.com>, Mao Han <han_mao@c-sky.com>,
	Geert Uytterhoeven <geert@linux-m68k.org>,
	"Eric W. Biederman" <ebiederm@xmission.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Marc Zyngier <maz@kernel.org>,
	Marek Szyprowski <m.szyprowski@samsung.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	linux-riscv@lists.infradead.org, Borislav Petkov <bp@suse.de>,
	Allison Randal <allison@lohutok.net>,
	Kees Cook <keescook@chromium.org>
Subject: Re: [PATCH v8 10/11] irqchip/sifive-plic: Initialize the plic handler when cpu comes online
Date: Thu, 13 Feb 2020 12:01:37 +0100	[thread overview]
Message-ID: <87ftfe3g4u.fsf@nanos.tec.linutronix.de> (raw)
In-Reply-To: <20200212014822.28684-11-atish.patra@wdc.com>

Atish Patra <atish.patra@wdc.com> writes:
  
> +static void plic_handler_init(struct plic_handler *handler, u32 threshold)
> +{
> +	irq_hw_number_t hwirq;
> +
> +	/* priority must be > threshold to trigger an interrupt */
> +	writel(threshold, handler->hart_base + CONTEXT_THRESHOLD);
> +	for (hwirq = 1; hwirq < plic_irqdomain->hwirq_max; hwirq++)
> +		plic_toggle(handler, hwirq, 0);
> +}

> +
> +static int plic_starting_cpu(unsigned int cpu)
> +{
> +	u32 threshold = 0;

Pointless variable. Also you use PLIC_DISABLE_THRESHOLD down below, so
please add a proper define for enable as well.

> +	struct plic_handler *handler = per_cpu_ptr(&plic_handlers, cpu);

        this_cpu_ptr*&...)

The callback is guaranteed to run on the plugged in CPU.

> -			threshold = 0xffffffff;
> +			plic_handler_init(handler, PLIC_DISABLE_THRESHOLD);

Thanks,

        tglx


  parent reply	other threads:[~2020-02-13 11:02 UTC|newest]

Thread overview: 50+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-12  1:48 [PATCH v8 00/11] Add support for SBI v0.2 and CPU hotplug Atish Patra
2020-02-12  1:48 ` Atish Patra
2020-02-12  1:48 ` [PATCH v8 01/11] RISC-V: Mark existing SBI as 0.1 SBI Atish Patra
2020-02-12  1:48   ` Atish Patra
2020-02-12  1:48 ` [PATCH v8 02/11] RISC-V: Add basic support for SBI v0.2 Atish Patra
2020-02-12  1:48   ` Atish Patra
2020-02-12  1:48 ` [PATCH v8 03/11] RISC-V: Add SBI v0.2 extension definitions Atish Patra
2020-02-12  1:48   ` Atish Patra
2020-02-12  1:48 ` [PATCH v8 04/11] RISC-V: Introduce a new config for SBI v0.1 Atish Patra
2020-02-12  1:48   ` Atish Patra
2020-02-12  1:48 ` [PATCH v8 05/11] RISC-V: Implement new SBI v0.2 extensions Atish Patra
2020-02-12  1:48   ` Atish Patra
2020-02-12  1:48 ` [PATCH v8 06/11] RISC-V: Move relocate and few other functions out of __init Atish Patra
2020-02-12  1:48   ` Atish Patra
2020-02-12  4:18   ` Anup Patel
2020-02-12  4:18     ` Anup Patel
2020-02-12 18:58     ` Atish Patra
2020-02-12 18:58       ` Atish Patra
2020-02-12  1:48 ` [PATCH v8 07/11] RISC-V: Add cpu_ops and modify default booting method Atish Patra
2020-02-12  1:48   ` Atish Patra
2020-02-12  4:28   ` Anup Patel
2020-02-12  4:28     ` Anup Patel
2020-02-12 18:57     ` Atish Patra
2020-02-12 18:57       ` Atish Patra
2020-02-12  1:48 ` [PATCH v8 08/11] RISC-V: Add SBI HSM extension Atish Patra
2020-02-12  1:48   ` Atish Patra
2020-02-12  4:53   ` Anup Patel
2020-02-12  4:53     ` Anup Patel
2020-02-12 19:54     ` Atish Patra
2020-02-12 19:54       ` Atish Patra
2020-02-12  1:48 ` [PATCH v8 09/11] RISC-V: Add supported for ordered booting method using HSM Atish Patra
2020-02-12  1:48   ` Atish Patra
2020-02-12  4:57   ` Anup Patel
2020-02-12  4:57     ` Anup Patel
2020-02-12  1:48 ` [PATCH v8 10/11] irqchip/sifive-plic: Initialize the plic handler when cpu comes online Atish Patra
2020-02-12  1:48   ` Atish Patra
2020-02-12  5:10   ` Anup Patel
2020-02-12  5:10     ` Anup Patel
2020-02-13 11:01   ` Thomas Gleixner [this message]
2020-02-13 11:01     ` Thomas Gleixner
2020-02-13 19:01     ` Atish Patra
2020-02-13 19:01       ` Atish Patra
2020-02-12  1:48 ` [PATCH v8 11/11] RISC-V: Support cpu hotplug Atish Patra
2020-02-12  1:48   ` Atish Patra
2020-02-12  5:13   ` Anup Patel
2020-02-12  5:13     ` Anup Patel
2020-02-19 21:48 ` [PATCH v8 00/11] Add support for SBI v0.2 and CPU hotplug Palmer Dabbelt
2020-02-19 21:48   ` Palmer Dabbelt
2020-02-20  1:16   ` Atish Patra
2020-02-20  1:16     ` Atish Patra

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