* [igt-dev] [PATCH i-g-t] i915/gem_exec_schedule: Exercise implicit ordering between engines
@ 2020-02-18 12:26 Chris Wilson
2020-02-18 17:42 ` [igt-dev] " Chris Wilson
0 siblings, 1 reply; 7+ messages in thread
From: Chris Wilson @ 2020-02-18 12:26 UTC (permalink / raw)
To: intel-gfx; +Cc: igt-dev
Check that reads are serialised after a write, and that a subsequent
write is after all reads.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Antonio Argenziano <antonio.argenziano@intel.com>
Cc: Sravan Kumar Nedunoori <sravan.kumar.nedunoori@intel.com>
---
tests/i915/gem_exec_schedule.c | 67 ++++++++++++++++++++++++++++++++++
1 file changed, 67 insertions(+)
diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c
index a20985864..ff41551d0 100644
--- a/tests/i915/gem_exec_schedule.c
+++ b/tests/i915/gem_exec_schedule.c
@@ -241,6 +241,55 @@ static void fifo(int fd, unsigned ring)
igt_assert_eq_u32(result, 2);
}
+enum implicit_dir {
+ READ_WRITE = 0x1,
+ WRITE_READ = 0x2,
+};
+
+static void implicit_rw(int i915, unsigned ring, enum implicit_dir dir)
+{
+ IGT_CORK_FENCE(cork);
+ unsigned int count;
+ uint32_t scratch;
+ uint32_t result;
+ int fence;
+
+ count = 0;
+ for_each_physical_engine(other, i915) {
+ if (eb_ring(other) == ring)
+ continue;
+
+ count++;
+ }
+ igt_require(count);
+
+ scratch = gem_create(i915, 4096);
+ fence = igt_cork_plug(&cork, i915);
+
+ if (dir & WRITE_READ)
+ store_dword_fenced(i915, 0, ring, scratch, 0, -ring, fence, I915_GEM_DOMAIN_RENDER);
+
+ for_each_physical_engine(other, i915) {
+ if (eb_ring(other) == ring)
+ continue;
+
+ store_dword_fenced(i915, 0, ring, scratch, 0, eb_ring(other), fence, 0);
+ }
+
+ if (dir & READ_WRITE)
+ store_dword_fenced(i915, 0, ring, scratch, 0, ring, fence, I915_GEM_DOMAIN_RENDER);
+
+ unplug_show_queue(i915, &cork, ring);
+ close(fence);
+
+ result = __sync_read_u32(i915, scratch, 0);
+ gem_close(i915, scratch);
+
+ igt_assert_neq_u32(result, -ring);
+ if (dir & READ_WRITE)
+ igt_assert_eq_u32(result, ring);
+}
+
static void independent(int fd, unsigned int engine)
{
IGT_CORK_FENCE(cork);
@@ -2042,6 +2091,24 @@ igt_main
fifo(fd, eb_ring(e));
}
+ igt_subtest_f("implicit-read-write-%s", e->name) {
+ igt_require(gem_ring_has_physical_engine(fd, eb_ring(e)));
+ igt_require(gem_can_store_dword(fd, eb_ring(e)));
+ implicit_rw(fd, eb_ring(e), READ_WRITE);
+ }
+
+ igt_subtest_f("implicit-write-read-%s", e->name) {
+ igt_require(gem_ring_has_physical_engine(fd, eb_ring(e)));
+ igt_require(gem_can_store_dword(fd, eb_ring(e)));
+ implicit_rw(fd, eb_ring(e), WRITE_READ);
+ }
+
+ igt_subtest_f("implicit-both-%s", e->name) {
+ igt_require(gem_ring_has_physical_engine(fd, eb_ring(e)));
+ igt_require(gem_can_store_dword(fd, eb_ring(e)));
+ implicit_rw(fd, eb_ring(e), READ_WRITE | WRITE_READ);
+ }
+
igt_subtest_f("independent-%s", e->name) {
igt_require(gem_ring_has_physical_engine(fd, eb_ring(e)));
igt_require(gem_can_store_dword(fd, eb_ring(e)));
--
2.25.0
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [Intel-gfx] [PATCH i-g-t] i915/gem_exec_schedule: Exercise implicit ordering between engines
2020-02-18 12:26 [igt-dev] [PATCH i-g-t] i915/gem_exec_schedule: Exercise implicit ordering between engines Chris Wilson
@ 2020-02-18 17:42 ` Chris Wilson
0 siblings, 0 replies; 7+ messages in thread
From: Chris Wilson @ 2020-02-18 17:42 UTC (permalink / raw)
To: intel-gfx; +Cc: igt-dev, Sravan Kumar Nedunoori
Check that reads are serialised after a write, and that a subsequent
write is after all reads.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Antonio Argenziano <antonio.argenziano@intel.com>
Cc: Sravan Kumar Nedunoori <sravan.kumar.nedunoori@intel.com>
---
tests/i915/gem_exec_schedule.c | 73 ++++++++++++++++++++++++++++++++++
1 file changed, 73 insertions(+)
diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c
index a20985864..cfd06aa55 100644
--- a/tests/i915/gem_exec_schedule.c
+++ b/tests/i915/gem_exec_schedule.c
@@ -241,6 +241,61 @@ static void fifo(int fd, unsigned ring)
igt_assert_eq_u32(result, 2);
}
+enum implicit_dir {
+ READ_WRITE = 0x1,
+ WRITE_READ = 0x2,
+};
+
+static void implicit_rw(int i915, unsigned ring, enum implicit_dir dir)
+{
+ IGT_CORK_FENCE(cork);
+ unsigned int count;
+ uint32_t scratch;
+ uint32_t result;
+ int fence;
+
+ count = 0;
+ for_each_physical_engine(other, i915) {
+ if (eb_ring(other) == ring)
+ continue;
+
+ count++;
+ }
+ igt_require(count);
+
+ scratch = gem_create(i915, 4096);
+ fence = igt_cork_plug(&cork, i915);
+
+ if (dir & WRITE_READ)
+ store_dword_fenced(i915, 0,
+ ring, scratch, 0, -ring,
+ fence, I915_GEM_DOMAIN_RENDER);
+
+ for_each_physical_engine(other, i915) {
+ if (eb_ring(other) == ring)
+ continue;
+
+ store_dword_fenced(i915, 0,
+ eb_ring(other), scratch, 0, eb_ring(other),
+ fence, 0);
+ }
+
+ if (dir & READ_WRITE)
+ store_dword_fenced(i915, 0,
+ ring, scratch, 0, ring,
+ fence, I915_GEM_DOMAIN_RENDER);
+
+ unplug_show_queue(i915, &cork, ring);
+ close(fence);
+
+ result = __sync_read_u32(i915, scratch, 0);
+ gem_close(i915, scratch);
+
+ igt_assert_neq_u32(result, -ring);
+ if (dir & READ_WRITE)
+ igt_assert_eq_u32(result, ring);
+}
+
static void independent(int fd, unsigned int engine)
{
IGT_CORK_FENCE(cork);
@@ -2042,6 +2097,24 @@ igt_main
fifo(fd, eb_ring(e));
}
+ igt_subtest_f("implicit-read-write-%s", e->name) {
+ igt_require(gem_ring_has_physical_engine(fd, eb_ring(e)));
+ igt_require(gem_can_store_dword(fd, eb_ring(e)));
+ implicit_rw(fd, eb_ring(e), READ_WRITE);
+ }
+
+ igt_subtest_f("implicit-write-read-%s", e->name) {
+ igt_require(gem_ring_has_physical_engine(fd, eb_ring(e)));
+ igt_require(gem_can_store_dword(fd, eb_ring(e)));
+ implicit_rw(fd, eb_ring(e), WRITE_READ);
+ }
+
+ igt_subtest_f("implicit-both-%s", e->name) {
+ igt_require(gem_ring_has_physical_engine(fd, eb_ring(e)));
+ igt_require(gem_can_store_dword(fd, eb_ring(e)));
+ implicit_rw(fd, eb_ring(e), READ_WRITE | WRITE_READ);
+ }
+
igt_subtest_f("independent-%s", e->name) {
igt_require(gem_ring_has_physical_engine(fd, eb_ring(e)));
igt_require(gem_can_store_dword(fd, eb_ring(e)));
--
2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [igt-dev] [PATCH i-g-t] i915/gem_exec_schedule: Exercise implicit ordering between engines
@ 2020-02-18 17:42 ` Chris Wilson
0 siblings, 0 replies; 7+ messages in thread
From: Chris Wilson @ 2020-02-18 17:42 UTC (permalink / raw)
To: intel-gfx; +Cc: igt-dev
Check that reads are serialised after a write, and that a subsequent
write is after all reads.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Antonio Argenziano <antonio.argenziano@intel.com>
Cc: Sravan Kumar Nedunoori <sravan.kumar.nedunoori@intel.com>
---
tests/i915/gem_exec_schedule.c | 73 ++++++++++++++++++++++++++++++++++
1 file changed, 73 insertions(+)
diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c
index a20985864..cfd06aa55 100644
--- a/tests/i915/gem_exec_schedule.c
+++ b/tests/i915/gem_exec_schedule.c
@@ -241,6 +241,61 @@ static void fifo(int fd, unsigned ring)
igt_assert_eq_u32(result, 2);
}
+enum implicit_dir {
+ READ_WRITE = 0x1,
+ WRITE_READ = 0x2,
+};
+
+static void implicit_rw(int i915, unsigned ring, enum implicit_dir dir)
+{
+ IGT_CORK_FENCE(cork);
+ unsigned int count;
+ uint32_t scratch;
+ uint32_t result;
+ int fence;
+
+ count = 0;
+ for_each_physical_engine(other, i915) {
+ if (eb_ring(other) == ring)
+ continue;
+
+ count++;
+ }
+ igt_require(count);
+
+ scratch = gem_create(i915, 4096);
+ fence = igt_cork_plug(&cork, i915);
+
+ if (dir & WRITE_READ)
+ store_dword_fenced(i915, 0,
+ ring, scratch, 0, -ring,
+ fence, I915_GEM_DOMAIN_RENDER);
+
+ for_each_physical_engine(other, i915) {
+ if (eb_ring(other) == ring)
+ continue;
+
+ store_dword_fenced(i915, 0,
+ eb_ring(other), scratch, 0, eb_ring(other),
+ fence, 0);
+ }
+
+ if (dir & READ_WRITE)
+ store_dword_fenced(i915, 0,
+ ring, scratch, 0, ring,
+ fence, I915_GEM_DOMAIN_RENDER);
+
+ unplug_show_queue(i915, &cork, ring);
+ close(fence);
+
+ result = __sync_read_u32(i915, scratch, 0);
+ gem_close(i915, scratch);
+
+ igt_assert_neq_u32(result, -ring);
+ if (dir & READ_WRITE)
+ igt_assert_eq_u32(result, ring);
+}
+
static void independent(int fd, unsigned int engine)
{
IGT_CORK_FENCE(cork);
@@ -2042,6 +2097,24 @@ igt_main
fifo(fd, eb_ring(e));
}
+ igt_subtest_f("implicit-read-write-%s", e->name) {
+ igt_require(gem_ring_has_physical_engine(fd, eb_ring(e)));
+ igt_require(gem_can_store_dword(fd, eb_ring(e)));
+ implicit_rw(fd, eb_ring(e), READ_WRITE);
+ }
+
+ igt_subtest_f("implicit-write-read-%s", e->name) {
+ igt_require(gem_ring_has_physical_engine(fd, eb_ring(e)));
+ igt_require(gem_can_store_dword(fd, eb_ring(e)));
+ implicit_rw(fd, eb_ring(e), WRITE_READ);
+ }
+
+ igt_subtest_f("implicit-both-%s", e->name) {
+ igt_require(gem_ring_has_physical_engine(fd, eb_ring(e)));
+ igt_require(gem_can_store_dword(fd, eb_ring(e)));
+ implicit_rw(fd, eb_ring(e), READ_WRITE | WRITE_READ);
+ }
+
igt_subtest_f("independent-%s", e->name) {
igt_require(gem_ring_has_physical_engine(fd, eb_ring(e)));
igt_require(gem_can_store_dword(fd, eb_ring(e)));
--
2.25.0
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [Intel-gfx] [PATCH i-g-t] i915/gem_exec_schedule: Exercise implicit ordering between engines
2020-02-18 17:42 ` [igt-dev] " Chris Wilson
@ 2020-02-18 17:56 ` Antonio Argenziano
-1 siblings, 0 replies; 7+ messages in thread
From: Antonio Argenziano @ 2020-02-18 17:56 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: igt-dev, Sravan Kumar Nedunoori
On 18/02/20 09:42, Chris Wilson wrote:
> Check that reads are serialised after a write, and that a subsequent
> write is after all reads.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Antonio Argenziano <antonio.argenziano@intel.com>
> Cc: Sravan Kumar Nedunoori <sravan.kumar.nedunoori@intel.com>
> ---
> tests/i915/gem_exec_schedule.c | 73 ++++++++++++++++++++++++++++++++++
> 1 file changed, 73 insertions(+)
>
> diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c
> index a20985864..cfd06aa55 100644
> --- a/tests/i915/gem_exec_schedule.c
> +++ b/tests/i915/gem_exec_schedule.c
> @@ -241,6 +241,61 @@ static void fifo(int fd, unsigned ring)
> igt_assert_eq_u32(result, 2);
> }
>
> +enum implicit_dir {
> + READ_WRITE = 0x1,
> + WRITE_READ = 0x2,
> +};
> +
> +static void implicit_rw(int i915, unsigned ring, enum implicit_dir dir)
> +{
> + IGT_CORK_FENCE(cork);
> + unsigned int count;
> + uint32_t scratch;
> + uint32_t result;
> + int fence;
> +
> + count = 0;
> + for_each_physical_engine(other, i915) {
> + if (eb_ring(other) == ring)
> + continue;
> +
> + count++;
> + }
> + igt_require(count);
> +
> + scratch = gem_create(i915, 4096);
> + fence = igt_cork_plug(&cork, i915);
> +
> + if (dir & WRITE_READ)
> + store_dword_fenced(i915, 0,
> + ring, scratch, 0, -ring,
> + fence, I915_GEM_DOMAIN_RENDER);
> +
> + for_each_physical_engine(other, i915) {
> + if (eb_ring(other) == ring)
> + continue;
> +
> + store_dword_fenced(i915, 0,
> + eb_ring(other), scratch, 0, eb_ring(other),
> + fence, 0);
> + }
> +
> + if (dir & READ_WRITE)
> + store_dword_fenced(i915, 0,
> + ring, scratch, 0, ring,
> + fence, I915_GEM_DOMAIN_RENDER);
> +
> + unplug_show_queue(i915, &cork, ring);
> + close(fence);
> +
> + result = __sync_read_u32(i915, scratch, 0);
> + gem_close(i915, scratch);
> +
> + igt_assert_neq_u32(result, -ring);
if (dir & WRITE_READ) ?
Other that that LGTM.
Reviewed-by: Antonio Argenziano <antonio.argenziano@intel.com>
> + if (dir & READ_WRITE)
> + igt_assert_eq_u32(result, ring);
> +}
> +
> static void independent(int fd, unsigned int engine)
> {
> IGT_CORK_FENCE(cork);
> @@ -2042,6 +2097,24 @@ igt_main
> fifo(fd, eb_ring(e));
> }
>
> + igt_subtest_f("implicit-read-write-%s", e->name) {
> + igt_require(gem_ring_has_physical_engine(fd, eb_ring(e)));
> + igt_require(gem_can_store_dword(fd, eb_ring(e)));
> + implicit_rw(fd, eb_ring(e), READ_WRITE);
> + }
> +
> + igt_subtest_f("implicit-write-read-%s", e->name) {
> + igt_require(gem_ring_has_physical_engine(fd, eb_ring(e)));
> + igt_require(gem_can_store_dword(fd, eb_ring(e)));
> + implicit_rw(fd, eb_ring(e), WRITE_READ);
> + }
> +
> + igt_subtest_f("implicit-both-%s", e->name) {
> + igt_require(gem_ring_has_physical_engine(fd, eb_ring(e)));
> + igt_require(gem_can_store_dword(fd, eb_ring(e)));
> + implicit_rw(fd, eb_ring(e), READ_WRITE | WRITE_READ);
> + }
> +
> igt_subtest_f("independent-%s", e->name) {
> igt_require(gem_ring_has_physical_engine(fd, eb_ring(e)));
> igt_require(gem_can_store_dword(fd, eb_ring(e)));
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [igt-dev] [PATCH i-g-t] i915/gem_exec_schedule: Exercise implicit ordering between engines
@ 2020-02-18 17:56 ` Antonio Argenziano
0 siblings, 0 replies; 7+ messages in thread
From: Antonio Argenziano @ 2020-02-18 17:56 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: igt-dev
On 18/02/20 09:42, Chris Wilson wrote:
> Check that reads are serialised after a write, and that a subsequent
> write is after all reads.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Antonio Argenziano <antonio.argenziano@intel.com>
> Cc: Sravan Kumar Nedunoori <sravan.kumar.nedunoori@intel.com>
> ---
> tests/i915/gem_exec_schedule.c | 73 ++++++++++++++++++++++++++++++++++
> 1 file changed, 73 insertions(+)
>
> diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c
> index a20985864..cfd06aa55 100644
> --- a/tests/i915/gem_exec_schedule.c
> +++ b/tests/i915/gem_exec_schedule.c
> @@ -241,6 +241,61 @@ static void fifo(int fd, unsigned ring)
> igt_assert_eq_u32(result, 2);
> }
>
> +enum implicit_dir {
> + READ_WRITE = 0x1,
> + WRITE_READ = 0x2,
> +};
> +
> +static void implicit_rw(int i915, unsigned ring, enum implicit_dir dir)
> +{
> + IGT_CORK_FENCE(cork);
> + unsigned int count;
> + uint32_t scratch;
> + uint32_t result;
> + int fence;
> +
> + count = 0;
> + for_each_physical_engine(other, i915) {
> + if (eb_ring(other) == ring)
> + continue;
> +
> + count++;
> + }
> + igt_require(count);
> +
> + scratch = gem_create(i915, 4096);
> + fence = igt_cork_plug(&cork, i915);
> +
> + if (dir & WRITE_READ)
> + store_dword_fenced(i915, 0,
> + ring, scratch, 0, -ring,
> + fence, I915_GEM_DOMAIN_RENDER);
> +
> + for_each_physical_engine(other, i915) {
> + if (eb_ring(other) == ring)
> + continue;
> +
> + store_dword_fenced(i915, 0,
> + eb_ring(other), scratch, 0, eb_ring(other),
> + fence, 0);
> + }
> +
> + if (dir & READ_WRITE)
> + store_dword_fenced(i915, 0,
> + ring, scratch, 0, ring,
> + fence, I915_GEM_DOMAIN_RENDER);
> +
> + unplug_show_queue(i915, &cork, ring);
> + close(fence);
> +
> + result = __sync_read_u32(i915, scratch, 0);
> + gem_close(i915, scratch);
> +
> + igt_assert_neq_u32(result, -ring);
if (dir & WRITE_READ) ?
Other that that LGTM.
Reviewed-by: Antonio Argenziano <antonio.argenziano@intel.com>
> + if (dir & READ_WRITE)
> + igt_assert_eq_u32(result, ring);
> +}
> +
> static void independent(int fd, unsigned int engine)
> {
> IGT_CORK_FENCE(cork);
> @@ -2042,6 +2097,24 @@ igt_main
> fifo(fd, eb_ring(e));
> }
>
> + igt_subtest_f("implicit-read-write-%s", e->name) {
> + igt_require(gem_ring_has_physical_engine(fd, eb_ring(e)));
> + igt_require(gem_can_store_dword(fd, eb_ring(e)));
> + implicit_rw(fd, eb_ring(e), READ_WRITE);
> + }
> +
> + igt_subtest_f("implicit-write-read-%s", e->name) {
> + igt_require(gem_ring_has_physical_engine(fd, eb_ring(e)));
> + igt_require(gem_can_store_dword(fd, eb_ring(e)));
> + implicit_rw(fd, eb_ring(e), WRITE_READ);
> + }
> +
> + igt_subtest_f("implicit-both-%s", e->name) {
> + igt_require(gem_ring_has_physical_engine(fd, eb_ring(e)));
> + igt_require(gem_can_store_dword(fd, eb_ring(e)));
> + implicit_rw(fd, eb_ring(e), READ_WRITE | WRITE_READ);
> + }
> +
> igt_subtest_f("independent-%s", e->name) {
> igt_require(gem_ring_has_physical_engine(fd, eb_ring(e)));
> igt_require(gem_can_store_dword(fd, eb_ring(e)));
>
_______________________________________________
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igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Intel-gfx] [PATCH i-g-t] i915/gem_exec_schedule: Exercise implicit ordering between engines
2020-02-18 17:56 ` [igt-dev] " Antonio Argenziano
@ 2020-02-18 18:00 ` Chris Wilson
-1 siblings, 0 replies; 7+ messages in thread
From: Chris Wilson @ 2020-02-18 18:00 UTC (permalink / raw)
To: Antonio Argenziano, intel-gfx; +Cc: igt-dev, Sravan Kumar Nedunoori
Quoting Antonio Argenziano (2020-02-18 17:56:10)
>
>
> On 18/02/20 09:42, Chris Wilson wrote:
> > Check that reads are serialised after a write, and that a subsequent
> > write is after all reads.
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Antonio Argenziano <antonio.argenziano@intel.com>
> > Cc: Sravan Kumar Nedunoori <sravan.kumar.nedunoori@intel.com>
> > ---
> > tests/i915/gem_exec_schedule.c | 73 ++++++++++++++++++++++++++++++++++
> > 1 file changed, 73 insertions(+)
> >
> > diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c
> > index a20985864..cfd06aa55 100644
> > --- a/tests/i915/gem_exec_schedule.c
> > +++ b/tests/i915/gem_exec_schedule.c
> > @@ -241,6 +241,61 @@ static void fifo(int fd, unsigned ring)
> > igt_assert_eq_u32(result, 2);
> > }
> >
> > +enum implicit_dir {
> > + READ_WRITE = 0x1,
> > + WRITE_READ = 0x2,
> > +};
> > +
> > +static void implicit_rw(int i915, unsigned ring, enum implicit_dir dir)
> > +{
> > + IGT_CORK_FENCE(cork);
> > + unsigned int count;
> > + uint32_t scratch;
> > + uint32_t result;
> > + int fence;
> > +
> > + count = 0;
> > + for_each_physical_engine(other, i915) {
> > + if (eb_ring(other) == ring)
> > + continue;
> > +
> > + count++;
> > + }
> > + igt_require(count);
> > +
> > + scratch = gem_create(i915, 4096);
> > + fence = igt_cork_plug(&cork, i915);
> > +
> > + if (dir & WRITE_READ)
> > + store_dword_fenced(i915, 0,
> > + ring, scratch, 0, -ring,
> > + fence, I915_GEM_DOMAIN_RENDER);
> > +
> > + for_each_physical_engine(other, i915) {
> > + if (eb_ring(other) == ring)
> > + continue;
> > +
> > + store_dword_fenced(i915, 0,
> > + eb_ring(other), scratch, 0, eb_ring(other),
> > + fence, 0);
> > + }
> > +
> > + if (dir & READ_WRITE)
> > + store_dword_fenced(i915, 0,
> > + ring, scratch, 0, ring,
> > + fence, I915_GEM_DOMAIN_RENDER);
> > +
> > + unplug_show_queue(i915, &cork, ring);
> > + close(fence);
> > +
> > + result = __sync_read_u32(i915, scratch, 0);
> > + gem_close(i915, scratch);
> > +
> > + igt_assert_neq_u32(result, -ring);
>
> if (dir & WRITE_READ) ?
We should never have -ring in there. If we have 2 billion engines, CI
will timeout first. And ring should always be !0.
Although the symmetry is pleasing.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [igt-dev] [PATCH i-g-t] i915/gem_exec_schedule: Exercise implicit ordering between engines
@ 2020-02-18 18:00 ` Chris Wilson
0 siblings, 0 replies; 7+ messages in thread
From: Chris Wilson @ 2020-02-18 18:00 UTC (permalink / raw)
To: Antonio Argenziano, intel-gfx; +Cc: igt-dev
Quoting Antonio Argenziano (2020-02-18 17:56:10)
>
>
> On 18/02/20 09:42, Chris Wilson wrote:
> > Check that reads are serialised after a write, and that a subsequent
> > write is after all reads.
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Antonio Argenziano <antonio.argenziano@intel.com>
> > Cc: Sravan Kumar Nedunoori <sravan.kumar.nedunoori@intel.com>
> > ---
> > tests/i915/gem_exec_schedule.c | 73 ++++++++++++++++++++++++++++++++++
> > 1 file changed, 73 insertions(+)
> >
> > diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c
> > index a20985864..cfd06aa55 100644
> > --- a/tests/i915/gem_exec_schedule.c
> > +++ b/tests/i915/gem_exec_schedule.c
> > @@ -241,6 +241,61 @@ static void fifo(int fd, unsigned ring)
> > igt_assert_eq_u32(result, 2);
> > }
> >
> > +enum implicit_dir {
> > + READ_WRITE = 0x1,
> > + WRITE_READ = 0x2,
> > +};
> > +
> > +static void implicit_rw(int i915, unsigned ring, enum implicit_dir dir)
> > +{
> > + IGT_CORK_FENCE(cork);
> > + unsigned int count;
> > + uint32_t scratch;
> > + uint32_t result;
> > + int fence;
> > +
> > + count = 0;
> > + for_each_physical_engine(other, i915) {
> > + if (eb_ring(other) == ring)
> > + continue;
> > +
> > + count++;
> > + }
> > + igt_require(count);
> > +
> > + scratch = gem_create(i915, 4096);
> > + fence = igt_cork_plug(&cork, i915);
> > +
> > + if (dir & WRITE_READ)
> > + store_dword_fenced(i915, 0,
> > + ring, scratch, 0, -ring,
> > + fence, I915_GEM_DOMAIN_RENDER);
> > +
> > + for_each_physical_engine(other, i915) {
> > + if (eb_ring(other) == ring)
> > + continue;
> > +
> > + store_dword_fenced(i915, 0,
> > + eb_ring(other), scratch, 0, eb_ring(other),
> > + fence, 0);
> > + }
> > +
> > + if (dir & READ_WRITE)
> > + store_dword_fenced(i915, 0,
> > + ring, scratch, 0, ring,
> > + fence, I915_GEM_DOMAIN_RENDER);
> > +
> > + unplug_show_queue(i915, &cork, ring);
> > + close(fence);
> > +
> > + result = __sync_read_u32(i915, scratch, 0);
> > + gem_close(i915, scratch);
> > +
> > + igt_assert_neq_u32(result, -ring);
>
> if (dir & WRITE_READ) ?
We should never have -ring in there. If we have 2 billion engines, CI
will timeout first. And ring should always be !0.
Although the symmetry is pleasing.
-Chris
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2020-02-18 18:00 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-02-18 12:26 [igt-dev] [PATCH i-g-t] i915/gem_exec_schedule: Exercise implicit ordering between engines Chris Wilson
2020-02-18 17:42 ` [Intel-gfx] " Chris Wilson
2020-02-18 17:42 ` [igt-dev] " Chris Wilson
2020-02-18 17:56 ` [Intel-gfx] " Antonio Argenziano
2020-02-18 17:56 ` [igt-dev] " Antonio Argenziano
2020-02-18 18:00 ` [Intel-gfx] " Chris Wilson
2020-02-18 18:00 ` [igt-dev] " Chris Wilson
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