[Intel-gfx] [PATCH v3 01/11] drm/i915/tgl: Implement Wa_1409804808

[Intel-gfx] [PATCH v3 01/11] drm/i915/tgl: Implement Wa_1409804808

[José Roberto de Souza]

This workaround the CS not done issue on PIPE_CONTROL.

v2:
- replaced BIT() by REG_BIT() in all GEN7_ROW_CHICKEN2() bits
- shortened the name of the new bit

BSpec: 52890
BSpec: 46218
Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++
 drivers/gpu/drm/i915/i915_reg.h             | 5 +++--
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 06cef3c18f26..d402b8ebc780 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1362,6 +1362,12 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 			     GEN12_DISABLE_EARLY_READ);
 	}
 
+	if (IS_TIGERLAKE(i915)) {
+		/* Wa_1409804808:tgl */
+		wa_masked_en(wal, GEN7_ROW_CHICKEN2,
+			     GEN12_PUSH_CONST_DEREF_HOLD_DIS);
+	}
+
 	if (IS_GEN(i915, 11)) {
 		/* This is not an Wa. Enable for better image quality */
 		wa_masked_en(wal,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 72de9591f77f..acace016d46c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9140,8 +9140,9 @@ enum {
 #define   THROTTLE_12_5				(7 << 2)
 #define   DISABLE_EARLY_EOT			(1 << 1)
 
-#define GEN7_ROW_CHICKEN2		_MMIO(0xe4f4)
-#define GEN12_DISABLE_EARLY_READ	BIT(14)
+#define GEN7_ROW_CHICKEN2			_MMIO(0xe4f4)
+#define   GEN12_DISABLE_EARLY_READ		REG_BIT(14)
+#define   GEN12_PUSH_CONST_DEREF_HOLD_DIS	REG_BIT(8)
 
 #define GEN7_ROW_CHICKEN2_GT2		_MMIO(0xf4f4)
 #define   DOP_CLOCK_GATING_DISABLE	(1 << 0)
-- 
2.25.1

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[Intel-gfx] [PATCH v3 02/11] drm/i915/tgl: Implement Wa_1806527549

[José Roberto de Souza]

This will whitelist the HIZ_CHICKEN register so mesa can disable the
optimizations and avoid hang when using D16_UNORM.

v2: moved to the right place and used the right function() (Chris)

Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Rafael Antognolli <rafael.antognolli@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index d402b8ebc780..5d85b7531f76 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1259,6 +1259,9 @@ static void tgl_whitelist_build(struct intel_engine_cs *engine)
 
 		/* Wa_1808121037:tgl */
 		whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1);
+
+		/* Wa_1806527549:tgl */
+		whitelist_reg(w, HIZ_CHICKEN);
 		break;
 	default:
 		break;
-- 
2.25.1

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Re: [Intel-gfx] [PATCH v3 02/11] drm/i915/tgl: Implement Wa_1806527549

[Matt Roper]

On Thu, Feb 27, 2020 at 02:00:52PM -0800, José Roberto de Souza wrote:
> This will whitelist the HIZ_CHICKEN register so mesa can disable the
> optimizations and avoid hang when using D16_UNORM.
> 
> v2: moved to the right place and used the right function() (Chris)
> 
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index d402b8ebc780..5d85b7531f76 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1259,6 +1259,9 @@ static void tgl_whitelist_build(struct intel_engine_cs *engine)
>  
>  		/* Wa_1808121037:tgl */
>  		whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1);
> +
> +		/* Wa_1806527549:tgl */
> +		whitelist_reg(w, HIZ_CHICKEN);
>  		break;
>  	default:
>  		break;
> -- 
> 2.25.1
> 

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[Intel-gfx] [PATCH v3 03/11] drm/i915/tgl: Add Wa_1409085225, Wa_14010229206

[José Roberto de Souza]

From: Matt Atwood <matthew.s.atwood@intel.com>

Disable Push Constant buffer addition for TGL.

v2: typos, add additional Wa reference
v3: use REG_BIT macro, move to rcs_engine_wa_init, clean up commit
message.

Bspec: 52890
Cc: Rafael Antognolli <rafael.antognolli@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++
 drivers/gpu/drm/i915/i915_reg.h             | 3 +++
 2 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 5d85b7531f76..927cf2bc9d15 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1363,6 +1363,12 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 		wa_masked_en(wal,
 			     GEN7_ROW_CHICKEN2,
 			     GEN12_DISABLE_EARLY_READ);
+
+		/*
+		 * Wa_1409085225:tgl
+		 * Wa_14010229206:tgl
+		 */
+		wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH);
 	}
 
 	if (IS_TIGERLAKE(i915)) {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index acace016d46c..80cf02a6eec1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9149,6 +9149,9 @@ enum {
 #define   PUSH_CONSTANT_DEREF_DISABLE	(1 << 8)
 #define   GEN11_TDL_CLOCK_GATING_FIX_DISABLE	(1 << 1)
 
+#define GEN9_ROW_CHICKEN4		_MMIO(0xe48c)
+#define   GEN12_DISABLE_TDL_PUSH	REG_BIT(9)
+
 #define HSW_ROW_CHICKEN3		_MMIO(0xe49c)
 #define  HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE    (1 << 6)
 
-- 
2.25.1

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[Intel-gfx] [PATCH v3 04/11] drm/i915/tgl: Extend Wa_1606931601 for all steppings

[José Roberto de Souza]

From: Anusha Srivatsa <anusha.srivatsa@intel.com>

According to BSpec. Wa_1606931601 applies for all TGL steppings.
This patch moves the WA implementation out of A0 only block of
rcs_engine_wa_init().

The WA is has also been referred to by an alternate name
Wa_1607090982.

Bspec: 46045, 52890

Fixes: 3873fd1a43c7 ("drm/i915: Use engine wa list for Wa_1607090982")
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 927cf2bc9d15..3021cc127403 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1359,11 +1359,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 			    GEN7_FF_THREAD_MODE,
 			    GEN12_FF_TESSELATION_DOP_GATE_DISABLE);
 
-		/* Wa_1606931601:tgl */
-		wa_masked_en(wal,
-			     GEN7_ROW_CHICKEN2,
-			     GEN12_DISABLE_EARLY_READ);
-
 		/*
 		 * Wa_1409085225:tgl
 		 * Wa_14010229206:tgl
@@ -1372,6 +1367,9 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 	}
 
 	if (IS_TIGERLAKE(i915)) {
+		/* Wa_1606931601:tgl */
+		wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ);
+
 		/* Wa_1409804808:tgl */
 		wa_masked_en(wal, GEN7_ROW_CHICKEN2,
 			     GEN12_PUSH_CONST_DEREF_HOLD_DIS);
-- 
2.25.1

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[Intel-gfx] [PATCH v3 05/11] drm/i915/tgl: Add note to Wa_1607297627

[José Roberto de Souza]

Add note about the confliting information in BSpec about this WA.

BSpec: 52890
Acked-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 3021cc127403..5f5eab7eb300 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1338,9 +1338,13 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 			    GEN9_CTX_PREEMPT_REG,
 			    GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
 
-		/* Wa_1607030317:tgl */
-		/* Wa_1607186500:tgl */
-		/* Wa_1607297627:tgl */
+		/*
+		 * Wa_1607030317:tgl
+		 * Wa_1607186500:tgl
+		 * Wa_1607297627:tgl there is 3 entries for this WA on BSpec, 2
+		 * of then says it is fixed on B0 the other one says it is
+		 * permanent
+		 */
 		wa_masked_en(wal,
 			     GEN6_RC_SLEEP_PSMI_CONTROL,
 			     GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
-- 
2.25.1

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[Intel-gfx] [PATCH v3 06/11] drm/i915/tgl: Add note about Wa_1607063988

[José Roberto de Souza]

This issue workaround in Wa_1607063988 has the same fix as
Wa_1607138336, so just adding a note in the code.

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 5f5eab7eb300..80411e408039 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1333,7 +1333,10 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 			     GEN9_CS_DEBUG_MODE1,
 			     FF_DOP_CLOCK_GATE_DISABLE);
 
-		/* Wa_1607138336:tgl */
+		/*
+		 * Wa_1607138336:tgl
+		 * Wa_1607063988:tgl
+		 */
 		wa_write_or(wal,
 			    GEN9_CTX_PREEMPT_REG,
 			    GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
-- 
2.25.1

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[Intel-gfx] [PATCH v3 07/11] drm/i915/tgl: Fix the Wa number of a fix

[José Roberto de Souza]

The Wa number for this fix is Wa_1607087056 the BSpec bug id is
1607087056, just updating to match BSpec.

BSpec: 52890
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 80411e408039..0cdd3c50e0ae 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -931,7 +931,7 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 			    SUBSLICE_UNIT_LEVEL_CLKGATE2,
 			    CPSSUNIT_CLKGATE_DIS);
 
-	/* Wa_1409180338:tgl */
+	/* Wa_1607087056:tgl also know as BUG:1409180338 */
 	if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
 		wa_write_or(wal,
 			    SLICE_UNIT_LEVEL_CLKGATE,
-- 
2.25.1

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Re: [Intel-gfx] [PATCH v3 07/11] drm/i915/tgl: Fix the Wa number of a fix

[Matt Roper]

On Thu, Feb 27, 2020 at 02:00:57PM -0800, José Roberto de Souza wrote:
> The Wa number for this fix is Wa_1607087056 the BSpec bug id is
> 1607087056, just updating to match BSpec.
> 
> BSpec: 52890
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 80411e408039..0cdd3c50e0ae 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -931,7 +931,7 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
>  			    SUBSLICE_UNIT_LEVEL_CLKGATE2,
>  			    CPSSUNIT_CLKGATE_DIS);
>  
> -	/* Wa_1409180338:tgl */
> +	/* Wa_1607087056:tgl also know as BUG:1409180338 */
>  	if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
>  		wa_write_or(wal,
>  			    SLICE_UNIT_LEVEL_CLKGATE,
> -- 
> 2.25.1
> 
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[Intel-gfx] [PATCH v3 08/11] drm/i915/tgl: Add note about Wa_1409142259

[José Roberto de Souza]

Different issues with the same fix, so justing adding
Wa_1409142259, Wa_1409252684, Wa_1409217633, Wa_1409207793,
Wa_1409178076 and 1408979724 to the comment so other devs can check if
this Was were implemetend with a simple grep.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 0cdd3c50e0ae..ba0265763484 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -580,7 +580,15 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
 static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
 				     struct i915_wa_list *wal)
 {
-	/* Wa_1409142259:tgl */
+	/*
+	 * Wa_1409142259:tgl
+	 * Wa_1409347922:tgl
+	 * Wa_1409252684:tgl
+	 * Wa_1409217633:tgl
+	 * Wa_1409207793:tgl
+	 * Wa_1409178076:tgl
+	 * Wa_1408979724:tgl
+	 */
 	WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
 			  GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
 
-- 
2.25.1

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Re: [Intel-gfx] [PATCH v3 08/11] drm/i915/tgl: Add note about Wa_1409142259

[Matt Roper]

On Thu, Feb 27, 2020 at 02:00:58PM -0800, José Roberto de Souza wrote:
> Different issues with the same fix, so justing adding
> Wa_1409142259, Wa_1409252684, Wa_1409217633, Wa_1409207793,
> Wa_1409178076 and 1408979724 to the comment so other devs can check if
> this Was were implemetend with a simple grep.
> 
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 10 +++++++++-
>  1 file changed, 9 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 0cdd3c50e0ae..ba0265763484 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -580,7 +580,15 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
>  static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
>  				     struct i915_wa_list *wal)
>  {
> -	/* Wa_1409142259:tgl */
> +	/*
> +	 * Wa_1409142259:tgl
> +	 * Wa_1409347922:tgl
> +	 * Wa_1409252684:tgl
> +	 * Wa_1409217633:tgl
> +	 * Wa_1409207793:tgl
> +	 * Wa_1409178076:tgl
> +	 * Wa_1408979724:tgl
> +	 */
>  	WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
>  			  GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
>  
> -- 
> 2.25.1
> 
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[Intel-gfx] [PATCH v3 09/11] drm/i915/tgl: Restrict Wa_1408615072 to A0 stepping

[José Roberto de Souza]

It is fixed in B0 stepping.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 22aa205793e5..a101d8072b5b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6838,8 +6838,9 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
 	unsigned int i;
 
 	/* Wa_1408615072:tgl */
-	intel_uncore_rmw(&dev_priv->uncore, UNSLICE_UNIT_LEVEL_CLKGATE2,
-			 0, VSUNIT_CLKGATE_DIS_TGL);
+	if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0))
+		intel_uncore_rmw(&dev_priv->uncore, UNSLICE_UNIT_LEVEL_CLKGATE2,
+				 0, VSUNIT_CLKGATE_DIS_TGL);
 
 	/* This is not a WA. Enable VD HCP & MFX_ENC powergate */
 	for (i = 0; i < I915_MAX_VCS; i++) {
-- 
2.25.1

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Re: [Intel-gfx] [PATCH v3 09/11] drm/i915/tgl: Restrict Wa_1408615072 to A0 stepping

[Matt Roper]

On Thu, Feb 27, 2020 at 02:00:59PM -0800, José Roberto de Souza wrote:
> It is fixed in B0 stepping.
> 
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 22aa205793e5..a101d8072b5b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6838,8 +6838,9 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
>  	unsigned int i;
>  
>  	/* Wa_1408615072:tgl */
> -	intel_uncore_rmw(&dev_priv->uncore, UNSLICE_UNIT_LEVEL_CLKGATE2,
> -			 0, VSUNIT_CLKGATE_DIS_TGL);
> +	if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0))
> +		intel_uncore_rmw(&dev_priv->uncore, UNSLICE_UNIT_LEVEL_CLKGATE2,
> +				 0, VSUNIT_CLKGATE_DIS_TGL);

I think this workaround is also implemented in the wrong location.  This
is a render engine register (part of the 94D0-951C render forcewake
range on bspec 52078) and part of the MCR range (bspec 52079), so we
should program this in the engine_wa_init rather than the clock gating
function.

The ICL/EHL version (which we based the TGL WA on) is also in the wrong
place for the same reasons.

At some point we should probably audit all the other GT/engine/MCR
registers we're dealing with in the init_clock_gating functions and move
them out to more appropriate places.


Matt

>  
>  	/* This is not a WA. Enable VD HCP & MFX_ENC powergate */
>  	for (i = 0; i < I915_MAX_VCS; i++) {
> -- 
> 2.25.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH v3 09/11] drm/i915/tgl: Restrict Wa_1408615072 to A0 stepping

[Souza, Jose]

On Fri, 2020-02-28 at 13:25 -0800, Matt Roper wrote:
> On Thu, Feb 27, 2020 at 02:00:59PM -0800, José Roberto de Souza
> wrote:
> > It is fixed in B0 stepping.
> > 
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c | 5 +++--
> >  1 file changed, 3 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index 22aa205793e5..a101d8072b5b 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -6838,8 +6838,9 @@ static void tgl_init_clock_gating(struct
> > drm_i915_private *dev_priv)
> >  	unsigned int i;
> >  
> >  	/* Wa_1408615072:tgl */
> > -	intel_uncore_rmw(&dev_priv->uncore,
> > UNSLICE_UNIT_LEVEL_CLKGATE2,
> > -			 0, VSUNIT_CLKGATE_DIS_TGL);
> > +	if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0))
> > +		intel_uncore_rmw(&dev_priv->uncore,
> > UNSLICE_UNIT_LEVEL_CLKGATE2,
> > +				 0, VSUNIT_CLKGATE_DIS_TGL);
> 
> I think this workaround is also implemented in the wrong
> location.  This
> is a render engine register (part of the 94D0-951C render forcewake
> range on bspec 52078) and part of the MCR range (bspec 52079), so we
> should program this in the engine_wa_init rather than the clock
> gating
> function.
> 
> The ICL/EHL version (which we based the TGL WA on) is also in the
> wrong
> place for the same reasons.
> 
> At some point we should probably audit all the other GT/engine/MCR
> registers we're dealing with in the init_clock_gating functions and
> move
> them out to more appropriate places.

What about this note in BSpec 52078:
* Note: Some CP registers (0x9400-0x97FF) are replicated in all
domains, thus both render and media domains must be awake.

Otherwise we have a huge problem, doing just a quick search I found
this 2 registers bellow that we are programing from init_clock_gating()
in the same range.

#define GEN8_UCGCTL6				_MMIO(0x9430)
#define GEN7_MISCCPCTL				_MMIO(0x9424)

> 
> 
> Matt
> 
> >  
> >  	/* This is not a WA. Enable VD HCP & MFX_ENC powergate */
> >  	for (i = 0; i < I915_MAX_VCS; i++) {
> > -- 
> > 2.25.1
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Re: [Intel-gfx] [PATCH v3 09/11] drm/i915/tgl: Restrict Wa_1408615072 to A0 stepping

[Matt Roper]

On Fri, Feb 28, 2020 at 04:04:17PM -0800, Souza, Jose wrote:
> On Fri, 2020-02-28 at 13:25 -0800, Matt Roper wrote:
> > On Thu, Feb 27, 2020 at 02:00:59PM -0800, José Roberto de Souza
> > wrote:
> > > It is fixed in B0 stepping.
> > > 
> > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/intel_pm.c | 5 +++--
> > >  1 file changed, 3 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > > b/drivers/gpu/drm/i915/intel_pm.c
> > > index 22aa205793e5..a101d8072b5b 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -6838,8 +6838,9 @@ static void tgl_init_clock_gating(struct
> > > drm_i915_private *dev_priv)
> > >  	unsigned int i;
> > >  
> > >  	/* Wa_1408615072:tgl */
> > > -	intel_uncore_rmw(&dev_priv->uncore,
> > > UNSLICE_UNIT_LEVEL_CLKGATE2,
> > > -			 0, VSUNIT_CLKGATE_DIS_TGL);
> > > +	if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0))
> > > +		intel_uncore_rmw(&dev_priv->uncore,
> > > UNSLICE_UNIT_LEVEL_CLKGATE2,
> > > +				 0, VSUNIT_CLKGATE_DIS_TGL);
> > 
> > I think this workaround is also implemented in the wrong
> > location.  This
> > is a render engine register (part of the 94D0-951C render forcewake
> > range on bspec 52078) and part of the MCR range (bspec 52079), so we
> > should program this in the engine_wa_init rather than the clock
> > gating
> > function.
> > 
> > The ICL/EHL version (which we based the TGL WA on) is also in the
> > wrong
> > place for the same reasons.
> > 
> > At some point we should probably audit all the other GT/engine/MCR
> > registers we're dealing with in the init_clock_gating functions and
> > move
> > them out to more appropriate places.
> 
> What about this note in BSpec 52078:
> * Note: Some CP registers (0x9400-0x97FF) are replicated in all
> domains, thus both render and media domains must be awake.

Well, the uncore functions will still take care of grabbing both
forcewakes for registers like these (so that the register writes are
applied to all the multicast register instances that live behind that
register offset), so everything that needs to be will be powered up.
Based on the information about the workaround, it sounds like it's only
actually the render engine it really matters for though.

If we do this change in init_clock_gating, I don't believe it gets
re-applied on single-engine resets, so we lose the workaround.  If we do
this in the rcs engine's WA function, then those will be re-applied

> 
> Otherwise we have a huge problem, doing just a quick search I found
> this 2 registers bellow that we are programing from init_clock_gating()
> in the same range.
> 
> #define GEN8_UCGCTL6				_MMIO(0x9430)
> #define GEN7_MISCCPCTL				_MMIO(0x9424)

Yeah, I suspect there are multiple workarounds we're not actually
handling properly today (but as long as you don't suffer an engine hang
& reset, you'll probably never notice).

IIRC, there's a fixme comment somewhere in the code saying we should move all
the non-display stuff our of init_clock_gating to move appropriate
locations too.



Matt

> 
> > 
> > 
> > Matt
> > 
> > >  
> > >  	/* This is not a WA. Enable VD HCP & MFX_ENC powergate */
> > >  	for (i = 0; i < I915_MAX_VCS; i++) {
> > > -- 
> > > 2.25.1
> > > 
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH v3 09/11] drm/i915/tgl: Restrict Wa_1408615072 to A0 stepping

[Souza, Jose]

On Fri, 2020-02-28 at 16:29 -0800, Matt Roper wrote:
> On Fri, Feb 28, 2020 at 04:04:17PM -0800, Souza, Jose wrote:
> > On Fri, 2020-02-28 at 13:25 -0800, Matt Roper wrote:
> > > On Thu, Feb 27, 2020 at 02:00:59PM -0800, José Roberto de Souza
> > > wrote:
> > > > It is fixed in B0 stepping.
> > > > 
> > > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/intel_pm.c | 5 +++--
> > > >  1 file changed, 3 insertions(+), 2 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > > > b/drivers/gpu/drm/i915/intel_pm.c
> > > > index 22aa205793e5..a101d8072b5b 100644
> > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > @@ -6838,8 +6838,9 @@ static void tgl_init_clock_gating(struct
> > > > drm_i915_private *dev_priv)
> > > >  	unsigned int i;
> > > >  
> > > >  	/* Wa_1408615072:tgl */
> > > > -	intel_uncore_rmw(&dev_priv->uncore,
> > > > UNSLICE_UNIT_LEVEL_CLKGATE2,
> > > > -			 0, VSUNIT_CLKGATE_DIS_TGL);
> > > > +	if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0))
> > > > +		intel_uncore_rmw(&dev_priv->uncore,
> > > > UNSLICE_UNIT_LEVEL_CLKGATE2,
> > > > +				 0, VSUNIT_CLKGATE_DIS_TGL);
> > > 
> > > I think this workaround is also implemented in the wrong
> > > location.  This
> > > is a render engine register (part of the 94D0-951C render
> > > forcewake
> > > range on bspec 52078) and part of the MCR range (bspec 52079), so
> > > we
> > > should program this in the engine_wa_init rather than the clock
> > > gating
> > > function.
> > > 
> > > The ICL/EHL version (which we based the TGL WA on) is also in the
> > > wrong
> > > place for the same reasons.
> > > 
> > > At some point we should probably audit all the other
> > > GT/engine/MCR
> > > registers we're dealing with in the init_clock_gating functions
> > > and
> > > move
> > > them out to more appropriate places.
> > 
> > What about this note in BSpec 52078:
> > * Note: Some CP registers (0x9400-0x97FF) are replicated in all
> > domains, thus both render and media domains must be awake.
> 
> Well, the uncore functions will still take care of grabbing both
> forcewakes for registers like these (so that the register writes are
> applied to all the multicast register instances that live behind that
> register offset), so everything that needs to be will be powered up.
> Based on the information about the workaround, it sounds like it's
> only
> actually the render engine it really matters for though.

The WA explicity says to set 0x94E4 so other engines would need it too.

> 
> If we do this change in init_clock_gating, I don't believe it gets
> re-applied on single-engine resets, so we lose the workaround.  If we
> do
> this in the rcs engine's WA function, then those will be re-applied

For what I checked if display is not involved in the reset it would not
be applied, so a better and easier sollution would be make it be
executed when display is not involved.

CCing some GT folks.

> 
> > Otherwise we have a huge problem, doing just a quick search I found
> > this 2 registers bellow that we are programing from
> > init_clock_gating()
> > in the same range.
> > 
> > #define GEN8_UCGCTL6				_MMIO(0x9430)
> > #define GEN7_MISCCPCTL				_MMIO(0x9424)
> 
> Yeah, I suspect there are multiple workarounds we're not actually
> handling properly today (but as long as you don't suffer an engine
> hang
> & reset, you'll probably never notice).
> 
> IIRC, there's a fixme comment somewhere in the code saying we should
> move all
> the non-display stuff our of init_clock_gating to move appropriate
> locations too.
> 
> 
> 
> Matt
> 
> > > 
> > > Matt
> > > 
> > > >  
> > > >  	/* This is not a WA. Enable VD HCP & MFX_ENC powergate
> > > > */
> > > >  	for (i = 0; i < I915_MAX_VCS; i++) {
> > > > -- 
> > > > 2.25.1
> > > > 
> > > > _______________________________________________
> > > > Intel-gfx mailing list
> > > > Intel-gfx@lists.freedesktop.org
> > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Re: [Intel-gfx] [PATCH v3 09/11] drm/i915/tgl: Restrict Wa_1408615072 to A0 stepping

[Matt Roper]

On Fri, Feb 28, 2020 at 04:45:43PM -0800, Souza, Jose wrote:
> On Fri, 2020-02-28 at 16:29 -0800, Matt Roper wrote:
> > On Fri, Feb 28, 2020 at 04:04:17PM -0800, Souza, Jose wrote:
> > > On Fri, 2020-02-28 at 13:25 -0800, Matt Roper wrote:
> > > > On Thu, Feb 27, 2020 at 02:00:59PM -0800, José Roberto de Souza
> > > > wrote:
> > > > > It is fixed in B0 stepping.
> > > > > 
> > > > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > > > ---
> > > > >  drivers/gpu/drm/i915/intel_pm.c | 5 +++--
> > > > >  1 file changed, 3 insertions(+), 2 deletions(-)
> > > > > 
> > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > > > > b/drivers/gpu/drm/i915/intel_pm.c
> > > > > index 22aa205793e5..a101d8072b5b 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > > @@ -6838,8 +6838,9 @@ static void tgl_init_clock_gating(struct
> > > > > drm_i915_private *dev_priv)
> > > > >  	unsigned int i;
> > > > >  
> > > > >  	/* Wa_1408615072:tgl */
> > > > > -	intel_uncore_rmw(&dev_priv->uncore,
> > > > > UNSLICE_UNIT_LEVEL_CLKGATE2,
> > > > > -			 0, VSUNIT_CLKGATE_DIS_TGL);
> > > > > +	if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0))
> > > > > +		intel_uncore_rmw(&dev_priv->uncore,
> > > > > UNSLICE_UNIT_LEVEL_CLKGATE2,
> > > > > +				 0, VSUNIT_CLKGATE_DIS_TGL);
> > > > 
> > > > I think this workaround is also implemented in the wrong
> > > > location.  This
> > > > is a render engine register (part of the 94D0-951C render
> > > > forcewake
> > > > range on bspec 52078) and part of the MCR range (bspec 52079), so
> > > > we
> > > > should program this in the engine_wa_init rather than the clock
> > > > gating
> > > > function.
> > > > 
> > > > The ICL/EHL version (which we based the TGL WA on) is also in the
> > > > wrong
> > > > place for the same reasons.
> > > > 
> > > > At some point we should probably audit all the other
> > > > GT/engine/MCR
> > > > registers we're dealing with in the init_clock_gating functions
> > > > and
> > > > move
> > > > them out to more appropriate places.
> > > 
> > > What about this note in BSpec 52078:
> > > * Note: Some CP registers (0x9400-0x97FF) are replicated in all
> > > domains, thus both render and media domains must be awake.
> > 
> > Well, the uncore functions will still take care of grabbing both
> > forcewakes for registers like these (so that the register writes are
> > applied to all the multicast register instances that live behind that
> > register offset), so everything that needs to be will be powered up.
> > Based on the information about the workaround, it sounds like it's
> > only
> > actually the render engine it really matters for though.
> 
> The WA explicity says to set 0x94E4 so other engines would need it too.

xcs_engine_wa_init() is the equivalent for other engines if we want to
make sure the multicast register is also re-written when we do a
single-engine reset on the media engines.

Although I see that just yesterday one of the architects filed bspec
issue 23662 which also relates to this register range...we may want to
wait and see how the bspec winds up getting clarified there before
moving this workaround around.

> 
> > 
> > If we do this change in init_clock_gating, I don't believe it gets
> > re-applied on single-engine resets, so we lose the workaround.  If we
> > do
> > this in the rcs engine's WA function, then those will be re-applied
> 
> For what I checked if display is not involved in the reset it would not
> be applied, so a better and easier sollution would be make it be
> executed when display is not involved.
> 
> CCing some GT folks.

Although init_clock_gating is part of the display vtable, it has a mix
of GT and display stuff today.  It's not really the right place to be
doing GT stuff, but since we haven't moved various workarounds out to
more correct places, we have a somewhat hacky workaround today of also
calling intel_init_clock_gating() in:

 * intel_finish_reset()
 * i915_drm_resume()
 * i915_gem_init()  (comment here admits we need to fix this)

to try to make sure that the GT-related stuff gets re-applied at some of
the points where it would otherwise be lost (GPU resets and system power
management).  But the intel_finish_reset() in the list above is dealing
with full GPU resets, not single-engine resets.

intel_engine_apply_workarounds() on the other hand gets called from
intel_engine_resume(), and that's called during intel_engine_reset() so
the workarounds applied by it (i.e., the stuff in rcs_engine_wa_init
and xcs_engine_wa_init) will be re-applied when you just reset a single
engine in isolation.


Matt

> 
> > 
> > > Otherwise we have a huge problem, doing just a quick search I found
> > > this 2 registers bellow that we are programing from
> > > init_clock_gating()
> > > in the same range.
> > > 
> > > #define GEN8_UCGCTL6				_MMIO(0x9430)
> > > #define GEN7_MISCCPCTL				_MMIO(0x9424)
> > 
> > Yeah, I suspect there are multiple workarounds we're not actually
> > handling properly today (but as long as you don't suffer an engine
> > hang
> > & reset, you'll probably never notice).
> > 
> > IIRC, there's a fixme comment somewhere in the code saying we should
> > move all
> > the non-display stuff our of init_clock_gating to move appropriate
> > locations too.
> > 
> > 
> > 
> > Matt
> > 
> > > > 
> > > > Matt
> > > > 
> > > > >  
> > > > >  	/* This is not a WA. Enable VD HCP & MFX_ENC powergate
> > > > > */
> > > > >  	for (i = 0; i < I915_MAX_VCS; i++) {
> > > > > -- 
> > > > > 2.25.1
> > > > > 
> > > > > _______________________________________________
> > > > > Intel-gfx mailing list
> > > > > Intel-gfx@lists.freedesktop.org
> > > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v3 10/11] drm/i915/tgl: Add Wa number to WaAllowPMDepthAndInvocationCountAccessFromUMD

[José Roberto de Souza]

Just to make easier to check that the Wa was implemetend when
comparing to the number in BSpec.

BSpec: 52890
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index ba0265763484..3e375a3b7714 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1254,6 +1254,7 @@ static void tgl_whitelist_build(struct intel_engine_cs *engine)
 	case RENDER_CLASS:
 		/*
 		 * WaAllowPMDepthAndInvocationCountAccessFromUMD:tgl
+		 * Wa_1408556865:tgl
 		 *
 		 * This covers 4 registers which are next to one another :
 		 *   - PS_INVOCATION_COUNT
-- 
2.25.1

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Re: [Intel-gfx] [PATCH v3 10/11] drm/i915/tgl: Add Wa number to WaAllowPMDepthAndInvocationCountAccessFromUMD

[Lionel Landwerlin]

On 28/02/2020 00:01, José Roberto de Souza wrote:
> Just to make easier to check that the Wa was implemetend when
> comparing to the number in BSpec.
>
> BSpec: 52890
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> ---
>   drivers/gpu/drm/i915/gt/intel_workarounds.c | 1 +
>   1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index ba0265763484..3e375a3b7714 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1254,6 +1254,7 @@ static void tgl_whitelist_build(struct intel_engine_cs *engine)
>   	case RENDER_CLASS:
>   		/*
>   		 * WaAllowPMDepthAndInvocationCountAccessFromUMD:tgl
> +		 * Wa_1408556865:tgl
>   		 *
>   		 * This covers 4 registers which are next to one another :
>   		 *   - PS_INVOCATION_COUNT


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[Intel-gfx] [PATCH v3 11/11] drm/i915/tgl: Implement Wa_1407901919

[José Roberto de Souza]

This will fix a memory coherence issue.

v3: using whitespace to make easy to read WA (Chris)

BSpec: 52890
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c |  8 ++++++++
 drivers/gpu/drm/i915/i915_reg.h             | 20 +++++++++++---------
 2 files changed, 19 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 3e375a3b7714..c59e1a604ab8 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -601,6 +601,14 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
 	 */
 	wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK,
 	       FF_MODE2_TDS_TIMER_128, 0);
+
+	/* Wa_1407901919:tgl */
+	wa_add(wal, ICL_HDC_MODE,
+	       HDC_COHERENT_ACCESS_L1_CACHE_DIS |
+	       HDC_DIS_L1_INVAL_FOR_NON_L1_CACHEABLE_W,
+	       0,
+	       HDC_COHERENT_ACCESS_L1_CACHE_DIS |
+	       HDC_DIS_L1_INVAL_FOR_NON_L1_CACHEABLE_W);
 }
 
 static void
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 80cf02a6eec1..28822585537b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7883,15 +7883,17 @@ enum {
 #define  GEN8_LQSC_FLUSH_COHERENT_LINES		(1 << 21)
 
 /* GEN8 chicken */
-#define HDC_CHICKEN0				_MMIO(0x7300)
-#define CNL_HDC_CHICKEN0			_MMIO(0xE5F0)
-#define ICL_HDC_MODE				_MMIO(0xE5F4)
-#define  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE	(1 << 15)
-#define  HDC_FENCE_DEST_SLM_DISABLE		(1 << 14)
-#define  HDC_DONOT_FETCH_MEM_WHEN_MASKED	(1 << 11)
-#define  HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT	(1 << 5)
-#define  HDC_FORCE_NON_COHERENT			(1 << 4)
-#define  HDC_BARRIER_PERFORMANCE_DISABLE	(1 << 10)
+#define HDC_CHICKEN0					_MMIO(0x7300)
+#define CNL_HDC_CHICKEN0				_MMIO(0xE5F0)
+#define ICL_HDC_MODE					_MMIO(0xE5F4)
+#define  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE		REG_BIT(15)
+#define  HDC_FENCE_DEST_SLM_DISABLE			REG_BIT(14)
+#define  HDC_DIS_L1_INVAL_FOR_NON_L1_CACHEABLE_W	REG_BIT(13)
+#define  HDC_COHERENT_ACCESS_L1_CACHE_DIS		REG_BIT(12)
+#define  HDC_DONOT_FETCH_MEM_WHEN_MASKED		REG_BIT(11)
+#define  HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT	REG_BIT(5)
+#define  HDC_FORCE_NON_COHERENT				REG_BIT(4)
+#define  HDC_BARRIER_PERFORMANCE_DISABLE		REG_BIT(10)
 
 #define GEN8_HDC_CHICKEN1			_MMIO(0x7304)
 
-- 
2.25.1

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Re: [Intel-gfx] [PATCH v3 11/11] drm/i915/tgl: Implement Wa_1407901919

[Matt Roper]

On Thu, Feb 27, 2020 at 02:01:01PM -0800, José Roberto de Souza wrote:
> This will fix a memory coherence issue.
> 
> v3: using whitespace to make easy to read WA (Chris)
> 
> BSpec: 52890
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c |  8 ++++++++
>  drivers/gpu/drm/i915/i915_reg.h             | 20 +++++++++++---------
>  2 files changed, 19 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 3e375a3b7714..c59e1a604ab8 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -601,6 +601,14 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
>  	 */
>  	wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK,
>  	       FF_MODE2_TDS_TIMER_128, 0);
> +
> +	/* Wa_1407901919:tgl */
> +	wa_add(wal, ICL_HDC_MODE,
> +	       HDC_COHERENT_ACCESS_L1_CACHE_DIS |
> +	       HDC_DIS_L1_INVAL_FOR_NON_L1_CACHEABLE_W,

I'm not sure if this is what the workaround is asking for.  The way I
understood the workaround, the 2-dword STATE_COMPUTE_MODE instruction
has a couple bits that must be left at 0.  STATE_COMPUTE_MODE is
basically how we ultimately load the HDC_MODE registers (rather than
using a simple LRI like we do for a bunch of other registers), but the
workaround isn't asking us to worry about bits 13+14 in the HDC_MODE
register itself, but rather those flags bits on the instruction that
manipulates the register.

Every time there's a context switch, the hardware will generate a copy
of this instruction as part of the context image in writes to RAM; I'm
assuming these bits aren't set on those hardware-created instructions?
Assuming that's true, then I think this workaround would just be
userspace's responsibility --- if they submit an explicit
STATE_COMPUTE_MODE instruction that isn't just part of the context
image, they need to follow the workaround guidance here and leave two of
those bits set to 0.


Matt

> +	       0,
> +	       HDC_COHERENT_ACCESS_L1_CACHE_DIS |
> +	       HDC_DIS_L1_INVAL_FOR_NON_L1_CACHEABLE_W);
>  }
>  
>  static void
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 80cf02a6eec1..28822585537b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7883,15 +7883,17 @@ enum {
>  #define  GEN8_LQSC_FLUSH_COHERENT_LINES		(1 << 21)
>  
>  /* GEN8 chicken */
> -#define HDC_CHICKEN0				_MMIO(0x7300)
> -#define CNL_HDC_CHICKEN0			_MMIO(0xE5F0)
> -#define ICL_HDC_MODE				_MMIO(0xE5F4)
> -#define  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE	(1 << 15)
> -#define  HDC_FENCE_DEST_SLM_DISABLE		(1 << 14)
> -#define  HDC_DONOT_FETCH_MEM_WHEN_MASKED	(1 << 11)
> -#define  HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT	(1 << 5)
> -#define  HDC_FORCE_NON_COHERENT			(1 << 4)
> -#define  HDC_BARRIER_PERFORMANCE_DISABLE	(1 << 10)
> +#define HDC_CHICKEN0					_MMIO(0x7300)
> +#define CNL_HDC_CHICKEN0				_MMIO(0xE5F0)
> +#define ICL_HDC_MODE					_MMIO(0xE5F4)
> +#define  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE		REG_BIT(15)
> +#define  HDC_FENCE_DEST_SLM_DISABLE			REG_BIT(14)
> +#define  HDC_DIS_L1_INVAL_FOR_NON_L1_CACHEABLE_W	REG_BIT(13)
> +#define  HDC_COHERENT_ACCESS_L1_CACHE_DIS		REG_BIT(12)
> +#define  HDC_DONOT_FETCH_MEM_WHEN_MASKED		REG_BIT(11)
> +#define  HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT	REG_BIT(5)
> +#define  HDC_FORCE_NON_COHERENT				REG_BIT(4)
> +#define  HDC_BARRIER_PERFORMANCE_DISABLE		REG_BIT(10)
>  
>  #define GEN8_HDC_CHICKEN1			_MMIO(0x7304)
>  
> -- 
> 2.25.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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Re: [Intel-gfx] [PATCH v3 11/11] drm/i915/tgl: Implement Wa_1407901919

[Souza, Jose]

Can you guys help in this one? Check Matt comment bellow.

On Fri, 2020-02-28 at 14:07 -0800, Matt Roper wrote:
> On Thu, Feb 27, 2020 at 02:01:01PM -0800, José Roberto de Souza
> wrote:
> > This will fix a memory coherence issue.
> > 
> > v3: using whitespace to make easy to read WA (Chris)
> > 
> > BSpec: 52890
> > Cc: Chris Wilson <chris@chris-wilson.co.uk>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> >  drivers/gpu/drm/i915/gt/intel_workarounds.c |  8 ++++++++
> >  drivers/gpu/drm/i915/i915_reg.h             | 20 +++++++++++----
> > -----
> >  2 files changed, 19 insertions(+), 9 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index 3e375a3b7714..c59e1a604ab8 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -601,6 +601,14 @@ static void tgl_ctx_workarounds_init(struct
> > intel_engine_cs *engine,
> >  	 */
> >  	wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK,
> >  	       FF_MODE2_TDS_TIMER_128, 0);
> > +
> > +	/* Wa_1407901919:tgl */
> > +	wa_add(wal, ICL_HDC_MODE,
> > +	       HDC_COHERENT_ACCESS_L1_CACHE_DIS |
> > +	       HDC_DIS_L1_INVAL_FOR_NON_L1_CACHEABLE_W,
> 
> I'm not sure if this is what the workaround is asking for.  The way I
> understood the workaround, the 2-dword STATE_COMPUTE_MODE instruction
> has a couple bits that must be left at 0.  STATE_COMPUTE_MODE is
> basically how we ultimately load the HDC_MODE registers (rather than
> using a simple LRI like we do for a bunch of other registers), but
> the
> workaround isn't asking us to worry about bits 13+14 in the HDC_MODE
> register itself, but rather those flags bits on the instruction that
> manipulates the register.
> 
> Every time there's a context switch, the hardware will generate a
> copy
> of this instruction as part of the context image in writes to RAM;
> I'm
> assuming these bits aren't set on those hardware-created
> instructions?
> Assuming that's true, then I think this workaround would just be
> userspace's responsibility --- if they submit an explicit
> STATE_COMPUTE_MODE instruction that isn't just part of the context
> image, they need to follow the workaround guidance here and leave two
> of
> those bits set to 0.
> 
> 
> Matt
> 
> > +	       0,
> > +	       HDC_COHERENT_ACCESS_L1_CACHE_DIS |
> > +	       HDC_DIS_L1_INVAL_FOR_NON_L1_CACHEABLE_W);
> >  }
> >  
> >  static void
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 80cf02a6eec1..28822585537b 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7883,15 +7883,17 @@ enum {
> >  #define  GEN8_LQSC_FLUSH_COHERENT_LINES		(1 << 21)
> >  
> >  /* GEN8 chicken */
> > -#define HDC_CHICKEN0				_MMIO(0x7300)
> > -#define CNL_HDC_CHICKEN0			_MMIO(0xE5F0)
> > -#define ICL_HDC_MODE				_MMIO(0xE5F4)
> > -#define  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE	(1 << 15)
> > -#define  HDC_FENCE_DEST_SLM_DISABLE		(1 << 14)
> > -#define  HDC_DONOT_FETCH_MEM_WHEN_MASKED	(1 << 11)
> > -#define  HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT	(1 <<
> > 5)
> > -#define  HDC_FORCE_NON_COHERENT			(1 << 4)
> > -#define  HDC_BARRIER_PERFORMANCE_DISABLE	(1 << 10)
> > +#define HDC_CHICKEN0					_MMIO(0
> > x7300)
> > +#define CNL_HDC_CHICKEN0				_MMIO(0xE5F0)
> > +#define ICL_HDC_MODE					_MMIO(0
> > xE5F4)
> > +#define  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE		REG_BIT
> > (15)
> > +#define  HDC_FENCE_DEST_SLM_DISABLE			REG_BIT
> > (14)
> > +#define  HDC_DIS_L1_INVAL_FOR_NON_L1_CACHEABLE_W	REG_BIT(13)
> > +#define  HDC_COHERENT_ACCESS_L1_CACHE_DIS		REG_BIT(12)
> > +#define  HDC_DONOT_FETCH_MEM_WHEN_MASKED		REG_BIT(11)
> > +#define  HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT	REG_BIT
> > (5)
> > +#define  HDC_FORCE_NON_COHERENT				REG_BIT
> > (4)
> > +#define  HDC_BARRIER_PERFORMANCE_DISABLE		REG_BIT(10)
> >  
> >  #define GEN8_HDC_CHICKEN1			_MMIO(0x7304)
> >  
> > -- 
> > 2.25.1
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [PATCH v3 11/11] drm/i915/tgl: Implement Wa_1407901919

[Rafael Antognolli]

On Fri, Feb 28, 2020 at 02:10:50PM -0800, Souza, Jose wrote:
> Can you guys help in this one? Check Matt comment bellow.
> 
> On Fri, 2020-02-28 at 14:07 -0800, Matt Roper wrote:
> > On Thu, Feb 27, 2020 at 02:01:01PM -0800, José Roberto de Souza
> > wrote:
> > > This will fix a memory coherence issue.
> > > 
> > > v3: using whitespace to make easy to read WA (Chris)
> > > 
> > > BSpec: 52890
> > > Cc: Chris Wilson <chris@chris-wilson.co.uk>
> > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/gt/intel_workarounds.c |  8 ++++++++
> > >  drivers/gpu/drm/i915/i915_reg.h             | 20 +++++++++++----
> > > -----
> > >  2 files changed, 19 insertions(+), 9 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > index 3e375a3b7714..c59e1a604ab8 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > @@ -601,6 +601,14 @@ static void tgl_ctx_workarounds_init(struct
> > > intel_engine_cs *engine,
> > >  	 */
> > >  	wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK,
> > >  	       FF_MODE2_TDS_TIMER_128, 0);
> > > +
> > > +	/* Wa_1407901919:tgl */
> > > +	wa_add(wal, ICL_HDC_MODE,
> > > +	       HDC_COHERENT_ACCESS_L1_CACHE_DIS |
> > > +	       HDC_DIS_L1_INVAL_FOR_NON_L1_CACHEABLE_W,
> > 
> > I'm not sure if this is what the workaround is asking for.  The way I
> > understood the workaround, the 2-dword STATE_COMPUTE_MODE instruction
> > has a couple bits that must be left at 0.  STATE_COMPUTE_MODE is
> > basically how we ultimately load the HDC_MODE registers (rather than
> > using a simple LRI like we do for a bunch of other registers), but
> > the
> > workaround isn't asking us to worry about bits 13+14 in the HDC_MODE
> > register itself, but rather those flags bits on the instruction that
> > manipulates the register.
> > 
> > Every time there's a context switch, the hardware will generate a
> > copy
> > of this instruction as part of the context image in writes to RAM;
> > I'm
> > assuming these bits aren't set on those hardware-created
> > instructions?
> > Assuming that's true, then I think this workaround would just be
> > userspace's responsibility --- if they submit an explicit
> > STATE_COMPUTE_MODE instruction that isn't just part of the context
> > image, they need to follow the workaround guidance here and leave two
> > of
> > those bits set to 0.

Hmmm... IMHO the workaround description doesn't make it very clear if
it's talking about the register itself, or the STATE_COMPUTE_MODE
instruction to set it. But the comment in the bug about it seems to
suggest what Matt described.

In any case, it should just be left as 0, and as Matt said, userspace
shouldn't set it to 1. So I agree, there's nothing to be done in the
kernel.

--
Rafael

> > 
> > Matt
> > 
> > > +	       0,
> > > +	       HDC_COHERENT_ACCESS_L1_CACHE_DIS |
> > > +	       HDC_DIS_L1_INVAL_FOR_NON_L1_CACHEABLE_W);
> > >  }
> > >  
> > >  static void
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > b/drivers/gpu/drm/i915/i915_reg.h
> > > index 80cf02a6eec1..28822585537b 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -7883,15 +7883,17 @@ enum {
> > >  #define  GEN8_LQSC_FLUSH_COHERENT_LINES		(1 << 21)
> > >  
> > >  /* GEN8 chicken */
> > > -#define HDC_CHICKEN0				_MMIO(0x7300)
> > > -#define CNL_HDC_CHICKEN0			_MMIO(0xE5F0)
> > > -#define ICL_HDC_MODE				_MMIO(0xE5F4)
> > > -#define  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE	(1 << 15)
> > > -#define  HDC_FENCE_DEST_SLM_DISABLE		(1 << 14)
> > > -#define  HDC_DONOT_FETCH_MEM_WHEN_MASKED	(1 << 11)
> > > -#define  HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT	(1 <<
> > > 5)
> > > -#define  HDC_FORCE_NON_COHERENT			(1 << 4)
> > > -#define  HDC_BARRIER_PERFORMANCE_DISABLE	(1 << 10)
> > > +#define HDC_CHICKEN0					_MMIO(0
> > > x7300)
> > > +#define CNL_HDC_CHICKEN0				_MMIO(0xE5F0)
> > > +#define ICL_HDC_MODE					_MMIO(0
> > > xE5F4)
> > > +#define  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE		REG_BIT
> > > (15)
> > > +#define  HDC_FENCE_DEST_SLM_DISABLE			REG_BIT
> > > (14)
> > > +#define  HDC_DIS_L1_INVAL_FOR_NON_L1_CACHEABLE_W	REG_BIT(13)
> > > +#define  HDC_COHERENT_ACCESS_L1_CACHE_DIS		REG_BIT(12)
> > > +#define  HDC_DONOT_FETCH_MEM_WHEN_MASKED		REG_BIT(11)
> > > +#define  HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT	REG_BIT
> > > (5)
> > > +#define  HDC_FORCE_NON_COHERENT				REG_BIT
> > > (4)
> > > +#define  HDC_BARRIER_PERFORMANCE_DISABLE		REG_BIT(10)
> > >  
> > >  #define GEN8_HDC_CHICKEN1			_MMIO(0x7304)
> > >  
> > > -- 
> > > 2.25.1
> > > 
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v3,01/11] drm/i915/tgl: Implement Wa_1409804808

[Patchwork]

== Series Details ==

Series: series starting with [v3,01/11] drm/i915/tgl: Implement Wa_1409804808
URL   : https://patchwork.freedesktop.org/series/74044/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_8023 -> Patchwork_16748
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/index.html

Known issues
------------

  Here are the changes found in Patchwork_16748 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live@execlists:
    - fi-icl-y:           [PASS][1] -> [DMESG-FAIL][2] ([fdo#108569])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/fi-icl-y/igt@i915_selftest@live@execlists.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/fi-icl-y/igt@i915_selftest@live@execlists.html

  * igt@i915_selftest@live@gem_contexts:
    - fi-cml-s:           [PASS][3] -> [DMESG-FAIL][4] ([i915#877])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/fi-cml-s/igt@i915_selftest@live@gem_contexts.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/fi-cml-s/igt@i915_selftest@live@gem_contexts.html

  
#### Possible fixes ####

  * igt@kms_chamelium@dp-edid-read:
    - fi-cml-u2:          [FAIL][5] ([i915#217] / [i915#976]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/fi-cml-u2/igt@kms_chamelium@dp-edid-read.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/fi-cml-u2/igt@kms_chamelium@dp-edid-read.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [FAIL][7] ([fdo#111096] / [i915#323]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  
  [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
  [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
  [i915#217]: https://gitlab.freedesktop.org/drm/intel/issues/217
  [i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323
  [i915#877]: https://gitlab.freedesktop.org/drm/intel/issues/877
  [i915#976]: https://gitlab.freedesktop.org/drm/intel/issues/976


Participating hosts (46 -> 44)
------------------------------

  Additional (4): fi-blb-e6850 fi-bdw-5557u fi-ivb-3770 fi-snb-2600 
  Missing    (6): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_8023 -> Patchwork_16748

  CI-20190529: 20190529
  CI_DRM_8023: fa9a02bbdfd6553ee633171f23183a115d0da577 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5474: 1be610f852de155cd915e7cda65cb2737adf04d4 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_16748: 3f9899a578a87f633e207f2c7fa80bdc04309132 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

3f9899a578a8 drm/i915/tgl: Implement Wa_1407901919
e5a4d51c5ebf drm/i915/tgl: Add Wa number to WaAllowPMDepthAndInvocationCountAccessFromUMD
84bd1383141d drm/i915/tgl: Restrict Wa_1408615072 to A0 stepping
46cf911d9366 drm/i915/tgl: Add note about Wa_1409142259
915fab948609 drm/i915/tgl: Fix the Wa number of a fix
6a0c4bdfb024 drm/i915/tgl: Add note about Wa_1607063988
7d1dc53cd0c8 drm/i915/tgl: Add note to Wa_1607297627
989dada4baef drm/i915/tgl: Extend Wa_1606931601 for all steppings
af32679a4a7a drm/i915/tgl: Add Wa_1409085225, Wa_14010229206
cdbe2acc573b drm/i915/tgl: Implement Wa_1806527549
c11d2385411c drm/i915/tgl: Implement Wa_1409804808

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v3,01/11] drm/i915/tgl: Implement Wa_1409804808

[Patchwork]

== Series Details ==

Series: series starting with [v3,01/11] drm/i915/tgl: Implement Wa_1409804808
URL   : https://patchwork.freedesktop.org/series/74044/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_8023_full -> Patchwork_16748_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_16748_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_16748_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_16748_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_exec_whisper@basic-contexts-forked:
    - shard-iclb:         [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-iclb4/igt@gem_exec_whisper@basic-contexts-forked.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-iclb4/igt@gem_exec_whisper@basic-contexts-forked.html

  
#### Warnings ####

  * igt@gem_tiled_wc:
    - shard-skl:          [TIMEOUT][3] ([i915#1286]) -> [INCOMPLETE][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-skl6/igt@gem_tiled_wc.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-skl2/igt@gem_tiled_wc.html

  
New tests
---------

  New tests have been introduced between CI_DRM_8023_full and Patchwork_16748_full:

### New IGT tests (1) ###

  * igt@kms_selftest@all:
    - Statuses :
    - Exec time: [None] s

  

Known issues
------------

  Here are the changes found in Patchwork_16748_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_schedule@implicit-both-bsd:
    - shard-iclb:         [PASS][5] -> [SKIP][6] ([i915#677]) +1 similar issue
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-iclb3/igt@gem_exec_schedule@implicit-both-bsd.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-iclb1/igt@gem_exec_schedule@implicit-both-bsd.html

  * igt@gem_exec_schedule@implicit-both-bsd1:
    - shard-iclb:         [PASS][7] -> [SKIP][8] ([fdo#109276] / [i915#677])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-iclb4/igt@gem_exec_schedule@implicit-both-bsd1.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-iclb5/igt@gem_exec_schedule@implicit-both-bsd1.html

  * igt@gem_exec_schedule@preempt-other-chain-bsd:
    - shard-iclb:         [PASS][9] -> [SKIP][10] ([fdo#112146]) +5 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-iclb7/igt@gem_exec_schedule@preempt-other-chain-bsd.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-iclb1/igt@gem_exec_schedule@preempt-other-chain-bsd.html

  * igt@gem_exec_whisper@basic-fds-forked:
    - shard-glk:          [PASS][11] -> [INCOMPLETE][12] ([i915#58] / [k.org#198133])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-glk8/igt@gem_exec_whisper@basic-fds-forked.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-glk4/igt@gem_exec_whisper@basic-fds-forked.html

  * igt@gem_exec_whisper@basic-queues-forked:
    - shard-apl:          [PASS][13] -> [INCOMPLETE][14] ([fdo#103927])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-apl3/igt@gem_exec_whisper@basic-queues-forked.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-apl4/igt@gem_exec_whisper@basic-queues-forked.html

  * igt@gem_ppgtt@flink-and-close-vma-leak:
    - shard-glk:          [PASS][15] -> [FAIL][16] ([i915#644])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-glk1/igt@gem_ppgtt@flink-and-close-vma-leak.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-glk5/igt@gem_ppgtt@flink-and-close-vma-leak.html

  * igt@i915_pm_dc@dc5-dpms:
    - shard-iclb:         [PASS][17] -> [FAIL][18] ([i915#447])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-iclb8/igt@i915_pm_dc@dc5-dpms.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-iclb3/igt@i915_pm_dc@dc5-dpms.html

  * igt@i915_pm_rps@reset:
    - shard-glk:          [PASS][19] -> [FAIL][20] ([i915#39])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-glk3/igt@i915_pm_rps@reset.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-glk3/igt@i915_pm_rps@reset.html

  * igt@kms_cursor_crc@pipe-a-cursor-suspend:
    - shard-kbl:          [PASS][21] -> [DMESG-WARN][22] ([i915#180]) +3 similar issues
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-kbl4/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-kbl7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-skl:          [PASS][23] -> [FAIL][24] ([i915#79])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-skl6/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-pwrite:
    - shard-tglb:         [PASS][25] -> [SKIP][26] ([i915#668]) +4 similar issues
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-tglb5/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-pwrite.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-tglb5/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-pwrite.html

  * igt@kms_hdr@bpc-switch-suspend:
    - shard-apl:          [PASS][27] -> [DMESG-WARN][28] ([i915#180]) +2 similar issues
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-apl3/igt@kms_hdr@bpc-switch-suspend.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-apl4/igt@kms_hdr@bpc-switch-suspend.html
    - shard-skl:          [PASS][29] -> [FAIL][30] ([i915#1188]) +1 similar issue
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-skl7/igt@kms_hdr@bpc-switch-suspend.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-skl9/igt@kms_hdr@bpc-switch-suspend.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [PASS][31] -> [FAIL][32] ([fdo#108145] / [i915#265])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@perf_pmu@busy-vcs1:
    - shard-iclb:         [PASS][33] -> [SKIP][34] ([fdo#112080]) +13 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-iclb1/igt@perf_pmu@busy-vcs1.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-iclb5/igt@perf_pmu@busy-vcs1.html

  * igt@prime_vgem@fence-wait-bsd2:
    - shard-iclb:         [PASS][35] -> [SKIP][36] ([fdo#109276]) +22 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-iclb1/igt@prime_vgem@fence-wait-bsd2.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-iclb5/igt@prime_vgem@fence-wait-bsd2.html

  
#### Possible fixes ####

  * igt@gem_ctx_persistence@legacy-engines-mixed-process@blt:
    - shard-skl:          [INCOMPLETE][37] ([i915#1197] / [i915#1239]) -> [PASS][38]
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-skl5/igt@gem_ctx_persistence@legacy-engines-mixed-process@blt.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-skl9/igt@gem_ctx_persistence@legacy-engines-mixed-process@blt.html

  * igt@gem_ctx_persistence@legacy-engines-mixed-process@bsd1:
    - shard-skl:          [FAIL][39] ([i915#679]) -> [PASS][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-skl5/igt@gem_ctx_persistence@legacy-engines-mixed-process@bsd1.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-skl9/igt@gem_ctx_persistence@legacy-engines-mixed-process@bsd1.html

  * {igt@gem_ctx_ringsize@active@bcs0}:
    - shard-iclb:         [INCOMPLETE][41] ([i915#1333]) -> [PASS][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-iclb1/igt@gem_ctx_ringsize@active@bcs0.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-iclb5/igt@gem_ctx_ringsize@active@bcs0.html

  * igt@gem_exec_schedule@implicit-read-write-bsd1:
    - shard-iclb:         [SKIP][43] ([fdo#109276] / [i915#677]) -> [PASS][44] +2 similar issues
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-iclb6/igt@gem_exec_schedule@implicit-read-write-bsd1.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-iclb4/igt@gem_exec_schedule@implicit-read-write-bsd1.html

  * igt@gem_exec_schedule@preempt-queue-bsd:
    - shard-iclb:         [SKIP][45] ([fdo#112146]) -> [PASS][46] +4 similar issues
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-iclb2/igt@gem_exec_schedule@preempt-queue-bsd.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-iclb6/igt@gem_exec_schedule@preempt-queue-bsd.html

  * igt@gem_exec_whisper@basic-contexts-forked:
    - shard-apl:          [INCOMPLETE][47] ([fdo#103927]) -> [PASS][48] +1 similar issue
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-apl2/igt@gem_exec_whisper@basic-contexts-forked.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-apl3/igt@gem_exec_whisper@basic-contexts-forked.html

  * igt@gem_userptr_blits@sync-unmap-after-close:
    - shard-glk:          [DMESG-WARN][49] ([fdo#111870] / [i915#836]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-glk1/igt@gem_userptr_blits@sync-unmap-after-close.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-glk5/igt@gem_userptr_blits@sync-unmap-after-close.html

  * igt@gem_workarounds@suspend-resume-context:
    - shard-apl:          [DMESG-WARN][51] ([i915#180]) -> [PASS][52] +3 similar issues
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-apl6/igt@gem_workarounds@suspend-resume-context.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-apl7/igt@gem_workarounds@suspend-resume-context.html

  * igt@i915_pm_dc@dc6-dpms:
    - shard-iclb:         [INCOMPLETE][53] -> [PASS][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-iclb2/igt@i915_pm_dc@dc6-dpms.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-iclb6/igt@i915_pm_dc@dc6-dpms.html

  * igt@i915_pm_dc@dc6-psr:
    - shard-iclb:         [FAIL][55] ([i915#454]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-iclb6/igt@i915_pm_dc@dc6-psr.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-iclb2/igt@i915_pm_dc@dc6-psr.html

  * igt@i915_pm_rps@waitboost:
    - shard-tglb:         [FAIL][57] ([i915#413]) -> [PASS][58]
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-tglb6/igt@i915_pm_rps@waitboost.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-tglb8/igt@i915_pm_rps@waitboost.html

  * igt@kms_cursor_crc@pipe-b-cursor-256x85-onscreen:
    - shard-skl:          [FAIL][59] ([i915#54]) -> [PASS][60]
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-skl1/igt@kms_cursor_crc@pipe-b-cursor-256x85-onscreen.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-skl1/igt@kms_cursor_crc@pipe-b-cursor-256x85-onscreen.html

  * igt@kms_cursor_crc@pipe-c-cursor-256x256-sliding:
    - shard-apl:          [FAIL][61] ([i915#54]) -> [PASS][62]
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-apl2/igt@kms_cursor_crc@pipe-c-cursor-256x256-sliding.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-apl3/igt@kms_cursor_crc@pipe-c-cursor-256x256-sliding.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - shard-skl:          [FAIL][63] ([IGT#5]) -> [PASS][64]
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-skl5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-skl9/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-kbl:          [DMESG-WARN][65] ([i915#180]) -> [PASS][66] +2 similar issues
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-kbl6/igt@kms_frontbuffer_tracking@fbc-suspend.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-kbl6/igt@kms_frontbuffer_tracking@fbc-suspend.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-render:
    - shard-skl:          [FAIL][67] ([i915#49]) -> [PASS][68]
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-skl1/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-render.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-skl1/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-render.html

  * igt@kms_psr@psr2_cursor_mmap_gtt:
    - shard-iclb:         [SKIP][69] ([fdo#109441]) -> [PASS][70]
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-iclb4/igt@kms_psr@psr2_cursor_mmap_gtt.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_gtt.html

  * igt@perf_pmu@busy-accuracy-2-vcs1:
    - shard-iclb:         [SKIP][71] ([fdo#112080]) -> [PASS][72] +14 similar issues
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-iclb3/igt@perf_pmu@busy-accuracy-2-vcs1.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-iclb1/igt@perf_pmu@busy-accuracy-2-vcs1.html

  * igt@prime_busy@hang-bsd2:
    - shard-iclb:         [SKIP][73] ([fdo#109276]) -> [PASS][74] +14 similar issues
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-iclb6/igt@prime_busy@hang-bsd2.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-iclb2/igt@prime_busy@hang-bsd2.html

  
#### Warnings ####

  * igt@gem_ctx_isolation@vcs1-nonpriv:
    - shard-iclb:         [SKIP][75] ([fdo#112080]) -> [FAIL][76] ([IGT#28])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-iclb8/igt@gem_ctx_isolation@vcs1-nonpriv.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-iclb1/igt@gem_ctx_isolation@vcs1-nonpriv.html

  * igt@i915_pm_dc@dc6-psr:
    - shard-tglb:         [SKIP][77] ([i915#468]) -> [FAIL][78] ([i915#454])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-tglb2/igt@i915_pm_dc@dc6-psr.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-tglb1/igt@i915_pm_dc@dc6-psr.html

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-skl:          [FAIL][79] ([i915#46]) -> [FAIL][80] ([i915#79])
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-skl10/igt@kms_flip@flip-vs-expired-vblank.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-skl2/igt@kms_flip@flip-vs-expired-vblank.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [IGT#28]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/28
  [IGT#5]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/5
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870
  [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
  [fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
  [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
  [i915#1197]: https://gitlab.freedesktop.org/drm/intel/issues/1197
  [i915#1239]: https://gitlab.freedesktop.org/drm/intel/issues/1239
  [i915#1286]: https://gitlab.freedesktop.org/drm/intel/issues/1286
  [i915#1333]: https://gitlab.freedesktop.org/drm/intel/issues/1333
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
  [i915#39]: https://gitlab.freedesktop.org/drm/intel/issues/39
  [i915#413]: https://gitlab.freedesktop.org/drm/intel/issues/413
  [i915#447]: https://gitlab.freedesktop.org/drm/intel/issues/447
  [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
  [i915#46]: https://gitlab.freedesktop.org/drm/intel/issues/46
  [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468
  [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
  [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
  [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58
  [i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644
  [i915#668]: https://gitlab.freedesktop.org/drm/intel/issues/668
  [i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677
  [i915#679]: https://gitlab.freedesktop.org/drm/intel/issues/679
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
  [i915#836]: https://gitlab.freedesktop.org/drm/intel/issues/836
  [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133


Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_8023 -> Patchwork_16748

  CI-20190529: 20190529
  CI_DRM_8023: fa9a02bbdfd6553ee633171f23183a115d0da577 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5474: 1be610f852de155cd915e7cda65cb2737adf04d4 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_16748: 3f9899a578a87f633e207f2c7fa80bdc04309132 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v3,01/11] drm/i915/tgl: Implement Wa_1409804808

[Souza, Jose]

On Sat, 2020-02-29 at 12:07 +0000, Patchwork wrote:
> == Series Details ==
> 
> Series: series starting with [v3,01/11] drm/i915/tgl: Implement
> Wa_1409804808
> URL   : https://patchwork.freedesktop.org/series/74044/
> State : failure
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_8023_full -> Patchwork_16748_full
> ====================================================
> 
> Summary
> -------
> 
>   **FAILURE**
> 
>   Serious unknown changes coming with Patchwork_16748_full absolutely
> need to be
>   verified manually.
>   
>   If you think the reported changes have nothing to do with the
> changes
>   introduced in Patchwork_16748_full, please notify your bug team to
> allow them
>   to document this new failure mode, which will reduce false
> positives in CI.
> 
>   
> 
> Possible new issues
> -------------------
> 
>   Here are the unknown changes that may have been introduced in
> Patchwork_16748_full:
> 
> ### IGT changes ###
> 
> #### Possible regressions ####
> 
>   * igt@gem_exec_whisper@basic-contexts-forked:
>     - shard-iclb:         [PASS][1] -> [INCOMPLETE][2]
>    [1]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-iclb4/igt@gem_exec_whisper@basic-contexts-forked.html
>    [2]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-iclb4/igt@gem_exec_whisper@basic-contexts-forked.html
> 

This patches only apply to TGL so this regression is not related.

Patches reviewed pushed to dinq, thanks for the reviews Matt and
Lionel.


>   
> #### Warnings ####
> 
>   * igt@gem_tiled_wc:
>     - shard-skl:          [TIMEOUT][3] ([i915#1286]) ->
> [INCOMPLETE][4]
>    [3]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-skl6/igt@gem_tiled_wc.html
>    [4]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-skl2/igt@gem_tiled_wc.html
> 
>   
> New tests
> ---------
> 
>   New tests have been introduced between CI_DRM_8023_full and
> Patchwork_16748_full:
> 
> ### New IGT tests (1) ###
> 
>   * igt@kms_selftest@all:
>     - Statuses :
>     - Exec time: [None] s
> 
>   
> 
> Known issues
> ------------
> 
>   Here are the changes found in Patchwork_16748_full that come from
> known issues:
> 
> ### IGT changes ###
> 
> #### Issues hit ####
> 
>   * igt@gem_exec_schedule@implicit-both-bsd:
>     - shard-iclb:         [PASS][5] -> [SKIP][6] ([i915#677]) +1
> similar issue
>    [5]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-iclb3/igt@gem_exec_schedule@implicit-both-bsd.html
>    [6]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-iclb1/igt@gem_exec_schedule@implicit-both-bsd.html
> 
>   * igt@gem_exec_schedule@implicit-both-bsd1:
>     - shard-iclb:         [PASS][7] -> [SKIP][8] ([fdo#109276] /
> [i915#677])
>    [7]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-iclb4/igt@gem_exec_schedule@implicit-both-bsd1.html
>    [8]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-iclb5/igt@gem_exec_schedule@implicit-both-bsd1.html
> 
>   * igt@gem_exec_schedule@preempt-other-chain-bsd:
>     - shard-iclb:         [PASS][9] -> [SKIP][10] ([fdo#112146]) +5
> similar issues
>    [9]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-iclb7/igt@gem_exec_schedule@preempt-other-chain-bsd.html
>    [10]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-iclb1/igt@gem_exec_schedule@preempt-other-chain-bsd.html
> 
>   * igt@gem_exec_whisper@basic-fds-forked:
>     - shard-glk:          [PASS][11] -> [INCOMPLETE][12] ([i915#58] /
> [k.org#198133])
>    [11]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-glk8/igt@gem_exec_whisper@basic-fds-forked.html
>    [12]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-glk4/igt@gem_exec_whisper@basic-fds-forked.html
> 
>   * igt@gem_exec_whisper@basic-queues-forked:
>     - shard-apl:          [PASS][13] -> [INCOMPLETE][14]
> ([fdo#103927])
>    [13]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-apl3/igt@gem_exec_whisper@basic-queues-forked.html
>    [14]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-apl4/igt@gem_exec_whisper@basic-queues-forked.html
> 
>   * igt@gem_ppgtt@flink-and-close-vma-leak:
>     - shard-glk:          [PASS][15] -> [FAIL][16] ([i915#644])
>    [15]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-glk1/igt@gem_ppgtt@flink-and-close-vma-leak.html
>    [16]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-glk5/igt@gem_ppgtt@flink-and-close-vma-leak.html
> 
>   * igt@i915_pm_dc@dc5-dpms:
>     - shard-iclb:         [PASS][17] -> [FAIL][18] ([i915#447])
>    [17]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-iclb8/igt@i915_pm_dc@dc5-dpms.html
>    [18]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-iclb3/igt@i915_pm_dc@dc5-dpms.html
> 
>   * igt@i915_pm_rps@reset:
>     - shard-glk:          [PASS][19] -> [FAIL][20] ([i915#39])
>    [19]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-glk3/igt@i915_pm_rps@reset.html
>    [20]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-glk3/igt@i915_pm_rps@reset.html
> 
>   * igt@kms_cursor_crc@pipe-a-cursor-suspend:
>     - shard-kbl:          [PASS][21] -> [DMESG-WARN][22] ([i915#180])
> +3 similar issues
>    [21]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-kbl4/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
>    [22]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-kbl7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
> 
>   * igt@kms_flip@flip-vs-expired-vblank-interruptible:
>     - shard-skl:          [PASS][23] -> [FAIL][24] ([i915#79])
>    [23]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
>    [24]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-skl6/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
> 
>   * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-pwrite:
>     - shard-tglb:         [PASS][25] -> [SKIP][26] ([i915#668]) +4
> similar issues
>    [25]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-tglb5/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-pwrite.html
>    [26]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-tglb5/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-pwrite.html
> 
>   * igt@kms_hdr@bpc-switch-suspend:
>     - shard-apl:          [PASS][27] -> [DMESG-WARN][28] ([i915#180])
> +2 similar issues
>    [27]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-apl3/igt@kms_hdr@bpc-switch-suspend.html
>    [28]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-apl4/igt@kms_hdr@bpc-switch-suspend.html
>     - shard-skl:          [PASS][29] -> [FAIL][30] ([i915#1188]) +1
> similar issue
>    [29]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-skl7/igt@kms_hdr@bpc-switch-suspend.html
>    [30]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-skl9/igt@kms_hdr@bpc-switch-suspend.html
> 
>   * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
>     - shard-skl:          [PASS][31] -> [FAIL][32] ([fdo#108145] /
> [i915#265])
>    [31]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
>    [32]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
> 
>   * igt@perf_pmu@busy-vcs1:
>     - shard-iclb:         [PASS][33] -> [SKIP][34] ([fdo#112080]) +13
> similar issues
>    [33]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-iclb1/igt@perf_pmu@busy-vcs1.html
>    [34]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-iclb5/igt@perf_pmu@busy-vcs1.html
> 
>   * igt@prime_vgem@fence-wait-bsd2:
>     - shard-iclb:         [PASS][35] -> [SKIP][36] ([fdo#109276]) +22
> similar issues
>    [35]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-iclb1/igt@prime_vgem@fence-wait-bsd2.html
>    [36]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-iclb5/igt@prime_vgem@fence-wait-bsd2.html
> 
>   
> #### Possible fixes ####
> 
>   * igt@gem_ctx_persistence@legacy-engines-mixed-process@blt:
>     - shard-skl:          [INCOMPLETE][37] ([i915#1197] /
> [i915#1239]) -> [PASS][38]
>    [37]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-skl5/igt@gem_ctx_persistence@legacy-engines-mixed-process@blt.html
>    [38]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-skl9/igt@gem_ctx_persistence@legacy-engines-mixed-process@blt.html
> 
>   * igt@gem_ctx_persistence@legacy-engines-mixed-process@bsd1:
>     - shard-skl:          [FAIL][39] ([i915#679]) -> [PASS][40]
>    [39]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-skl5/igt@gem_ctx_persistence@legacy-engines-mixed-process@bsd1.html
>    [40]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-skl9/igt@gem_ctx_persistence@legacy-engines-mixed-process@bsd1.html
> 
>   * {igt@gem_ctx_ringsize@active@bcs0}:
>     - shard-iclb:         [INCOMPLETE][41] ([i915#1333]) ->
> [PASS][42]
>    [41]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-iclb1/igt@gem_ctx_ringsize@active@bcs0.html
>    [42]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-iclb5/igt@gem_ctx_ringsize@active@bcs0.html
> 
>   * igt@gem_exec_schedule@implicit-read-write-bsd1:
>     - shard-iclb:         [SKIP][43] ([fdo#109276] / [i915#677]) ->
> [PASS][44] +2 similar issues
>    [43]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-iclb6/igt@gem_exec_schedule@implicit-read-write-bsd1.html
>    [44]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-iclb4/igt@gem_exec_schedule@implicit-read-write-bsd1.html
> 
>   * igt@gem_exec_schedule@preempt-queue-bsd:
>     - shard-iclb:         [SKIP][45] ([fdo#112146]) -> [PASS][46] +4
> similar issues
>    [45]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-iclb2/igt@gem_exec_schedule@preempt-queue-bsd.html
>    [46]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-iclb6/igt@gem_exec_schedule@preempt-queue-bsd.html
> 
>   * igt@gem_exec_whisper@basic-contexts-forked:
>     - shard-apl:          [INCOMPLETE][47] ([fdo#103927]) ->
> [PASS][48] +1 similar issue
>    [47]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-apl2/igt@gem_exec_whisper@basic-contexts-forked.html
>    [48]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-apl3/igt@gem_exec_whisper@basic-contexts-forked.html
> 
>   * igt@gem_userptr_blits@sync-unmap-after-close:
>     - shard-glk:          [DMESG-WARN][49] ([fdo#111870] /
> [i915#836]) -> [PASS][50]
>    [49]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-glk1/igt@gem_userptr_blits@sync-unmap-after-close.html
>    [50]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-glk5/igt@gem_userptr_blits@sync-unmap-after-close.html
> 
>   * igt@gem_workarounds@suspend-resume-context:
>     - shard-apl:          [DMESG-WARN][51] ([i915#180]) -> [PASS][52]
> +3 similar issues
>    [51]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-apl6/igt@gem_workarounds@suspend-resume-context.html
>    [52]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-apl7/igt@gem_workarounds@suspend-resume-context.html
> 
>   * igt@i915_pm_dc@dc6-dpms:
>     - shard-iclb:         [INCOMPLETE][53] -> [PASS][54]
>    [53]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-iclb2/igt@i915_pm_dc@dc6-dpms.html
>    [54]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-iclb6/igt@i915_pm_dc@dc6-dpms.html
> 
>   * igt@i915_pm_dc@dc6-psr:
>     - shard-iclb:         [FAIL][55] ([i915#454]) -> [PASS][56]
>    [55]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-iclb6/igt@i915_pm_dc@dc6-psr.html
>    [56]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-iclb2/igt@i915_pm_dc@dc6-psr.html
> 
>   * igt@i915_pm_rps@waitboost:
>     - shard-tglb:         [FAIL][57] ([i915#413]) -> [PASS][58]
>    [57]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-tglb6/igt@i915_pm_rps@waitboost.html
>    [58]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-tglb8/igt@i915_pm_rps@waitboost.html
> 
>   * igt@kms_cursor_crc@pipe-b-cursor-256x85-onscreen:
>     - shard-skl:          [FAIL][59] ([i915#54]) -> [PASS][60]
>    [59]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-skl1/igt@kms_cursor_crc@pipe-b-cursor-256x85-onscreen.html
>    [60]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-skl1/igt@kms_cursor_crc@pipe-b-cursor-256x85-onscreen.html
> 
>   * igt@kms_cursor_crc@pipe-c-cursor-256x256-sliding:
>     - shard-apl:          [FAIL][61] ([i915#54]) -> [PASS][62]
>    [61]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-apl2/igt@kms_cursor_crc@pipe-c-cursor-256x256-sliding.html
>    [62]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-apl3/igt@kms_cursor_crc@pipe-c-cursor-256x256-sliding.html
> 
>   * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
>     - shard-skl:          [FAIL][63] ([IGT#5]) -> [PASS][64]
>    [63]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-skl5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
>    [64]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-skl9/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
> 
>   * igt@kms_frontbuffer_tracking@fbc-suspend:
>     - shard-kbl:          [DMESG-WARN][65] ([i915#180]) -> [PASS][66]
> +2 similar issues
>    [65]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-kbl6/igt@kms_frontbuffer_tracking@fbc-suspend.html
>    [66]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-kbl6/igt@kms_frontbuffer_tracking@fbc-suspend.html
> 
>   * igt@kms
> _frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-render:
>     - shard-skl:          [FAIL][67] ([i915#49]) -> [PASS][68]
>    [67]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-skl1/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-render.html
>    [68]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-skl1/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-render.html
> 
>   * igt@kms_psr@psr2_cursor_mmap_gtt:
>     - shard-iclb:         [SKIP][69] ([fdo#109441]) -> [PASS][70]
>    [69]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-iclb4/igt@kms_psr@psr2_cursor_mmap_gtt.html
>    [70]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_gtt.html
> 
>   * igt@perf_pmu@busy-accuracy-2-vcs1:
>     - shard-iclb:         [SKIP][71] ([fdo#112080]) -> [PASS][72] +14
> similar issues
>    [71]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-iclb3/igt@perf_pmu@busy-accuracy-2-vcs1.html
>    [72]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-iclb1/igt@perf_pmu@busy-accuracy-2-vcs1.html
> 
>   * igt@prime_busy@hang-bsd2:
>     - shard-iclb:         [SKIP][73] ([fdo#109276]) -> [PASS][74] +14
> similar issues
>    [73]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-iclb6/igt@prime_busy@hang-bsd2.html
>    [74]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-iclb2/igt@prime_busy@hang-bsd2.html
> 
>   
> #### Warnings ####
> 
>   * igt@gem_ctx_isolation@vcs1-nonpriv:
>     - shard-iclb:         [SKIP][75] ([fdo#112080]) -> [FAIL][76]
> ([IGT#28])
>    [75]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-iclb8/igt@gem_ctx_isolation@vcs1-nonpriv.html
>    [76]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-iclb1/igt@gem_ctx_isolation@vcs1-nonpriv.html
> 
>   * igt@i915_pm_dc@dc6-psr:
>     - shard-tglb:         [SKIP][77] ([i915#468]) -> [FAIL][78]
> ([i915#454])
>    [77]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-tglb2/igt@i915_pm_dc@dc6-psr.html
>    [78]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-tglb1/igt@i915_pm_dc@dc6-psr.html
> 
>   * igt@kms_flip@flip-vs-expired-vblank:
>     - shard-skl:          [FAIL][79] ([i915#46]) -> [FAIL][80]
> ([i915#79])
>    [79]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-skl10/igt@kms_flip@flip-vs-expired-vblank.html
>    [80]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/shard-skl2/igt@kms_flip@flip-vs-expired-vblank.html
> 
>   
>   {name}: This element is suppressed. This means it is ignored when
> computing
>           the status of the difference (SUCCESS, WARNING, or
> FAILURE).
> 
>   [IGT#28]: 
> https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/28
>   [IGT#5]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/5
>   [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
>   [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
>   [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
>   [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
>   [fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870
>   [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
>   [fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
>   [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
>   [i915#1197]: https://gitlab.freedesktop.org/drm/intel/issues/1197
>   [i915#1239]: https://gitlab.freedesktop.org/drm/intel/issues/1239
>   [i915#1286]: https://gitlab.freedesktop.org/drm/intel/issues/1286
>   [i915#1333]: https://gitlab.freedesktop.org/drm/intel/issues/1333
>   [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
>   [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
>   [i915#39]: https://gitlab.freedesktop.org/drm/intel/issues/39
>   [i915#413]: https://gitlab.freedesktop.org/drm/intel/issues/413
>   [i915#447]: https://gitlab.freedesktop.org/drm/intel/issues/447
>   [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
>   [i915#46]: https://gitlab.freedesktop.org/drm/intel/issues/46
>   [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468
>   [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
>   [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
>   [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58
>   [i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644
>   [i915#668]: https://gitlab.freedesktop.org/drm/intel/issues/668
>   [i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677
>   [i915#679]: https://gitlab.freedesktop.org/drm/intel/issues/679
>   [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
>   [i915#836]: https://gitlab.freedesktop.org/drm/intel/issues/836
>   [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
> 
> 
> Participating hosts (10 -> 10)
> ------------------------------
> 
>   No changes in participating hosts
> 
> 
> Build changes
> -------------
> 
>   * CI: CI-20190529 -> None
>   * Linux: CI_DRM_8023 -> Patchwork_16748
> 
>   CI-20190529: 20190529
>   CI_DRM_8023: fa9a02bbdfd6553ee633171f23183a115d0da577 @
> git://anongit.freedesktop.org/gfx-ci/linux
>   IGT_5474: 1be610f852de155cd915e7cda65cb2737adf04d4 @
> git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
>   Patchwork_16748: 3f9899a578a87f633e207f2c7fa80bdc04309132 @
> git://anongit.freedesktop.org/gfx-ci/linux
>   piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
> git://anongit.freedesktop.org/piglit
> 
> == Logs ==
> 
> For more details see: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16748/index.html
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