* [PATCH v2 0/2] Support different CPU types for the sifive_e machine @ 2020-03-13 19:34 ` Corey Wharton 0 siblings, 0 replies; 21+ messages in thread From: Corey Wharton @ 2020-03-13 19:34 UTC (permalink / raw) To: qemu-devel, qemu-riscv Cc: Sagar Karandikar, Corey Wharton, Bastian Koppelmann, Alistair Francis, Palmer Dabbelt, Bin Meng The purpose of this patch set is to allow the sifive_e machine to run with different CPU targets to enable different ISA entensions. To that end it also introduces a new sifive-e34 CPU type which provides the same ISA as sifive-e31, with the addition of the single precision floating-point extension (f). The default CPU for the sifive_e machine is unchanged. v2: Added missing RVU flag Corey Wharton (2): riscv: sifive_e: Support changing CPU type target/riscv: Add a sifive-e34 cpu type hw/riscv/sifive_e.c | 3 ++- target/riscv/cpu.c | 10 ++++++++++ target/riscv/cpu.h | 1 + 3 files changed, 13 insertions(+), 1 deletion(-) -- 2.21.1 ^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v2 0/2] Support different CPU types for the sifive_e machine @ 2020-03-13 19:34 ` Corey Wharton 0 siblings, 0 replies; 21+ messages in thread From: Corey Wharton @ 2020-03-13 19:34 UTC (permalink / raw) To: qemu-devel, qemu-riscv Cc: Palmer Dabbelt, Alistair Francis, Sagar Karandikar, Bastian Koppelmann, Bin Meng, Corey Wharton The purpose of this patch set is to allow the sifive_e machine to run with different CPU targets to enable different ISA entensions. To that end it also introduces a new sifive-e34 CPU type which provides the same ISA as sifive-e31, with the addition of the single precision floating-point extension (f). The default CPU for the sifive_e machine is unchanged. v2: Added missing RVU flag Corey Wharton (2): riscv: sifive_e: Support changing CPU type target/riscv: Add a sifive-e34 cpu type hw/riscv/sifive_e.c | 3 ++- target/riscv/cpu.c | 10 ++++++++++ target/riscv/cpu.h | 1 + 3 files changed, 13 insertions(+), 1 deletion(-) -- 2.21.1 ^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v2 1/2] riscv: sifive_e: Support changing CPU type 2020-03-13 19:34 ` Corey Wharton @ 2020-03-13 19:34 ` Corey Wharton -1 siblings, 0 replies; 21+ messages in thread From: Corey Wharton @ 2020-03-13 19:34 UTC (permalink / raw) To: qemu-devel, qemu-riscv Cc: Sagar Karandikar, Corey Wharton, Bastian Koppelmann, Alistair Francis, Palmer Dabbelt, Bin Meng Allows the CPU to be changed from the default via the -cpu command line option. Signed-off-by: Corey Wharton <coreyw7@fb.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> --- hw/riscv/sifive_e.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index a254cad489..b0a611adb9 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -123,7 +123,7 @@ static void riscv_sifive_e_soc_init(Object *obj) object_initialize_child(obj, "cpus", &s->cpus, sizeof(s->cpus), TYPE_RISCV_HART_ARRAY, &error_abort, NULL); - object_property_set_str(OBJECT(&s->cpus), SIFIVE_E_CPU, "cpu-type", + object_property_set_str(OBJECT(&s->cpus), ms->cpu_type, "cpu-type", &error_abort); object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts", &error_abort); @@ -220,6 +220,7 @@ static void riscv_sifive_e_machine_init(MachineClass *mc) mc->desc = "RISC-V Board compatible with SiFive E SDK"; mc->init = riscv_sifive_e_init; mc->max_cpus = 1; + mc->default_cpu_type = SIFIVE_E_CPU; } DEFINE_MACHINE("sifive_e", riscv_sifive_e_machine_init) -- 2.21.1 ^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v2 1/2] riscv: sifive_e: Support changing CPU type @ 2020-03-13 19:34 ` Corey Wharton 0 siblings, 0 replies; 21+ messages in thread From: Corey Wharton @ 2020-03-13 19:34 UTC (permalink / raw) To: qemu-devel, qemu-riscv Cc: Palmer Dabbelt, Alistair Francis, Sagar Karandikar, Bastian Koppelmann, Bin Meng, Corey Wharton, Alistair Francis Allows the CPU to be changed from the default via the -cpu command line option. Signed-off-by: Corey Wharton <coreyw7@fb.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> --- hw/riscv/sifive_e.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index a254cad489..b0a611adb9 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -123,7 +123,7 @@ static void riscv_sifive_e_soc_init(Object *obj) object_initialize_child(obj, "cpus", &s->cpus, sizeof(s->cpus), TYPE_RISCV_HART_ARRAY, &error_abort, NULL); - object_property_set_str(OBJECT(&s->cpus), SIFIVE_E_CPU, "cpu-type", + object_property_set_str(OBJECT(&s->cpus), ms->cpu_type, "cpu-type", &error_abort); object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts", &error_abort); @@ -220,6 +220,7 @@ static void riscv_sifive_e_machine_init(MachineClass *mc) mc->desc = "RISC-V Board compatible with SiFive E SDK"; mc->init = riscv_sifive_e_init; mc->max_cpus = 1; + mc->default_cpu_type = SIFIVE_E_CPU; } DEFINE_MACHINE("sifive_e", riscv_sifive_e_machine_init) -- 2.21.1 ^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH v2 1/2] riscv: sifive_e: Support changing CPU type 2020-03-13 19:34 ` Corey Wharton @ 2020-03-13 19:46 ` Philippe Mathieu-Daudé -1 siblings, 0 replies; 21+ messages in thread From: Philippe Mathieu-Daudé @ 2020-03-13 19:46 UTC (permalink / raw) To: Corey Wharton, qemu-devel, qemu-riscv Cc: Bastian Koppelmann, Bin Meng, Alistair Francis, Palmer Dabbelt, Sagar Karandikar On 3/13/20 8:34 PM, Corey Wharton wrote: > Allows the CPU to be changed from the default via the -cpu command > line option. > > Signed-off-by: Corey Wharton <coreyw7@fb.com> > Reviewed-by: Bin Meng <bmeng.cn@gmail.com> > Reviewed-by: Alistair Francis <alistair.francis@wdc.com> > --- > hw/riscv/sifive_e.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c > index a254cad489..b0a611adb9 100644 > --- a/hw/riscv/sifive_e.c > +++ b/hw/riscv/sifive_e.c > @@ -123,7 +123,7 @@ static void riscv_sifive_e_soc_init(Object *obj) > object_initialize_child(obj, "cpus", &s->cpus, > sizeof(s->cpus), TYPE_RISCV_HART_ARRAY, > &error_abort, NULL); > - object_property_set_str(OBJECT(&s->cpus), SIFIVE_E_CPU, "cpu-type", > + object_property_set_str(OBJECT(&s->cpus), ms->cpu_type, "cpu-type", > &error_abort); > object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts", > &error_abort); > @@ -220,6 +220,7 @@ static void riscv_sifive_e_machine_init(MachineClass *mc) > mc->desc = "RISC-V Board compatible with SiFive E SDK"; > mc->init = riscv_sifive_e_init; > mc->max_cpus = 1; > + mc->default_cpu_type = SIFIVE_E_CPU; > } > > DEFINE_MACHINE("sifive_e", riscv_sifive_e_machine_init) > Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v2 1/2] riscv: sifive_e: Support changing CPU type @ 2020-03-13 19:46 ` Philippe Mathieu-Daudé 0 siblings, 0 replies; 21+ messages in thread From: Philippe Mathieu-Daudé @ 2020-03-13 19:46 UTC (permalink / raw) To: Corey Wharton, qemu-devel, qemu-riscv Cc: Sagar Karandikar, Bastian Koppelmann, Alistair Francis, Palmer Dabbelt, Bin Meng On 3/13/20 8:34 PM, Corey Wharton wrote: > Allows the CPU to be changed from the default via the -cpu command > line option. > > Signed-off-by: Corey Wharton <coreyw7@fb.com> > Reviewed-by: Bin Meng <bmeng.cn@gmail.com> > Reviewed-by: Alistair Francis <alistair.francis@wdc.com> > --- > hw/riscv/sifive_e.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c > index a254cad489..b0a611adb9 100644 > --- a/hw/riscv/sifive_e.c > +++ b/hw/riscv/sifive_e.c > @@ -123,7 +123,7 @@ static void riscv_sifive_e_soc_init(Object *obj) > object_initialize_child(obj, "cpus", &s->cpus, > sizeof(s->cpus), TYPE_RISCV_HART_ARRAY, > &error_abort, NULL); > - object_property_set_str(OBJECT(&s->cpus), SIFIVE_E_CPU, "cpu-type", > + object_property_set_str(OBJECT(&s->cpus), ms->cpu_type, "cpu-type", > &error_abort); > object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts", > &error_abort); > @@ -220,6 +220,7 @@ static void riscv_sifive_e_machine_init(MachineClass *mc) > mc->desc = "RISC-V Board compatible with SiFive E SDK"; > mc->init = riscv_sifive_e_init; > mc->max_cpus = 1; > + mc->default_cpu_type = SIFIVE_E_CPU; > } > > DEFINE_MACHINE("sifive_e", riscv_sifive_e_machine_init) > Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v2 1/2] riscv: sifive_e: Support changing CPU type 2020-03-13 19:34 ` Corey Wharton @ 2020-04-24 16:03 ` Alistair Francis -1 siblings, 0 replies; 21+ messages in thread From: Alistair Francis @ 2020-04-24 16:03 UTC (permalink / raw) To: Corey Wharton Cc: open list:RISC-V, Sagar Karandikar, Bastian Koppelmann, qemu-devel@nongnu.org Developers, Alistair Francis, Palmer Dabbelt, Bin Meng On Fri, Mar 13, 2020 at 12:35 PM Corey Wharton <coreyw7@fb.com> wrote: > > Allows the CPU to be changed from the default via the -cpu command > line option. > > Signed-off-by: Corey Wharton <coreyw7@fb.com> > Reviewed-by: Bin Meng <bmeng.cn@gmail.com> > Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Thanks for the patch. Unfortunately this fails `make check`. The problem is that the machine has the `default_cpu_type` set but then you set "cpu-type" from the SoC. This diff fixes the make check failure for me: diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 1fd08f325c..b53109521e 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -123,8 +123,6 @@ static void riscv_sifive_e_soc_init(Object *obj) object_initialize_child(obj, "cpus", &s->cpus, sizeof(s->cpus), TYPE_RISCV_HART_ARRAY, &error_abort, NULL); - object_property_set_str(OBJECT(&s->cpus), ms->cpu_type, "cpu-type", - &error_abort); object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts", &error_abort); sysbus_init_child_obj(obj, "riscv.sifive.e.gpio0", @@ -141,6 +139,8 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp) SiFiveESoCState *s = RISCV_E_SOC(dev); MemoryRegion *sys_mem = get_system_memory(); + object_property_set_str(OBJECT(&s->cpus), ms->cpu_type, "cpu-type", + &error_abort); object_property_set_bool(OBJECT(&s->cpus), true, "realized", &error_abort); I'm happy to just squash that into the patch. Let me know if you don't want me to do that and I'll drop these patches and let you re-send them. Alistair > --- > hw/riscv/sifive_e.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c > index a254cad489..b0a611adb9 100644 > --- a/hw/riscv/sifive_e.c > +++ b/hw/riscv/sifive_e.c > @@ -123,7 +123,7 @@ static void riscv_sifive_e_soc_init(Object *obj) > object_initialize_child(obj, "cpus", &s->cpus, > sizeof(s->cpus), TYPE_RISCV_HART_ARRAY, > &error_abort, NULL); > - object_property_set_str(OBJECT(&s->cpus), SIFIVE_E_CPU, "cpu-type", > + object_property_set_str(OBJECT(&s->cpus), ms->cpu_type, "cpu-type", > &error_abort); > object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts", > &error_abort); > @@ -220,6 +220,7 @@ static void riscv_sifive_e_machine_init(MachineClass *mc) > mc->desc = "RISC-V Board compatible with SiFive E SDK"; > mc->init = riscv_sifive_e_init; > mc->max_cpus = 1; > + mc->default_cpu_type = SIFIVE_E_CPU; > } > > DEFINE_MACHINE("sifive_e", riscv_sifive_e_machine_init) > -- > 2.21.1 > > ^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH v2 1/2] riscv: sifive_e: Support changing CPU type @ 2020-04-24 16:03 ` Alistair Francis 0 siblings, 0 replies; 21+ messages in thread From: Alistair Francis @ 2020-04-24 16:03 UTC (permalink / raw) To: Corey Wharton Cc: qemu-devel@nongnu.org Developers, open list:RISC-V, Sagar Karandikar, Bastian Koppelmann, Alistair Francis, Palmer Dabbelt, Bin Meng On Fri, Mar 13, 2020 at 12:35 PM Corey Wharton <coreyw7@fb.com> wrote: > > Allows the CPU to be changed from the default via the -cpu command > line option. > > Signed-off-by: Corey Wharton <coreyw7@fb.com> > Reviewed-by: Bin Meng <bmeng.cn@gmail.com> > Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Thanks for the patch. Unfortunately this fails `make check`. The problem is that the machine has the `default_cpu_type` set but then you set "cpu-type" from the SoC. This diff fixes the make check failure for me: diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 1fd08f325c..b53109521e 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -123,8 +123,6 @@ static void riscv_sifive_e_soc_init(Object *obj) object_initialize_child(obj, "cpus", &s->cpus, sizeof(s->cpus), TYPE_RISCV_HART_ARRAY, &error_abort, NULL); - object_property_set_str(OBJECT(&s->cpus), ms->cpu_type, "cpu-type", - &error_abort); object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts", &error_abort); sysbus_init_child_obj(obj, "riscv.sifive.e.gpio0", @@ -141,6 +139,8 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp) SiFiveESoCState *s = RISCV_E_SOC(dev); MemoryRegion *sys_mem = get_system_memory(); + object_property_set_str(OBJECT(&s->cpus), ms->cpu_type, "cpu-type", + &error_abort); object_property_set_bool(OBJECT(&s->cpus), true, "realized", &error_abort); I'm happy to just squash that into the patch. Let me know if you don't want me to do that and I'll drop these patches and let you re-send them. Alistair > --- > hw/riscv/sifive_e.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c > index a254cad489..b0a611adb9 100644 > --- a/hw/riscv/sifive_e.c > +++ b/hw/riscv/sifive_e.c > @@ -123,7 +123,7 @@ static void riscv_sifive_e_soc_init(Object *obj) > object_initialize_child(obj, "cpus", &s->cpus, > sizeof(s->cpus), TYPE_RISCV_HART_ARRAY, > &error_abort, NULL); > - object_property_set_str(OBJECT(&s->cpus), SIFIVE_E_CPU, "cpu-type", > + object_property_set_str(OBJECT(&s->cpus), ms->cpu_type, "cpu-type", > &error_abort); > object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts", > &error_abort); > @@ -220,6 +220,7 @@ static void riscv_sifive_e_machine_init(MachineClass *mc) > mc->desc = "RISC-V Board compatible with SiFive E SDK"; > mc->init = riscv_sifive_e_init; > mc->max_cpus = 1; > + mc->default_cpu_type = SIFIVE_E_CPU; > } > > DEFINE_MACHINE("sifive_e", riscv_sifive_e_machine_init) > -- > 2.21.1 > > ^ permalink raw reply related [flat|nested] 21+ messages in thread
* RE: [PATCH v2 1/2] riscv: sifive_e: Support changing CPU type 2020-04-24 16:03 ` Alistair Francis (?) @ 2020-04-24 19:12 ` Corey Wharton 2020-04-24 19:40 ` Alistair Francis -1 siblings, 1 reply; 21+ messages in thread From: Corey Wharton @ 2020-04-24 19:12 UTC (permalink / raw) To: Alistair Francis Cc: qemu-devel@nongnu.org Developers, open list:RISC-V, Sagar Karandikar, Bastian Koppelmann, Alistair Francis, Palmer Dabbelt, Bin Meng > -----Original Message----- > From: Alistair Francis <alistair23@gmail.com> > Sent: Friday, April 24, 2020 9:04 AM > To: Corey Wharton <coreyw7@fb.com> > Cc: qemu-devel@nongnu.org Developers <qemu-devel@nongnu.org>; open > list:RISC-V <qemu-riscv@nongnu.org>; Sagar Karandikar > <sagark@eecs.berkeley.edu>; Bastian Koppelmann <kbastian@mail.uni- > paderborn.de>; Alistair Francis <alistair.francis@wdc.com>; Palmer Dabbelt > <palmer@dabbelt.com>; Bin Meng <bmeng.cn@gmail.com> > Subject: Re: [PATCH v2 1/2] riscv: sifive_e: Support changing CPU type > > On Fri, Mar 13, 2020 at 12:35 PM Corey Wharton <coreyw7@fb.com> wrote: > > > > Allows the CPU to be changed from the default via the -cpu command > > line option. > > > > Signed-off-by: Corey Wharton <coreyw7@fb.com> > > Reviewed-by: Bin Meng <bmeng.cn@gmail.com> > > Reviewed-by: Alistair Francis <alistair.francis@wdc.com> > > Thanks for the patch. > > Unfortunately this fails `make check`. > > The problem is that the machine has the `default_cpu_type` set but then you > set "cpu-type" from the SoC. > > This diff fixes the make check failure for me: > > diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index > 1fd08f325c..b53109521e 100644 > --- a/hw/riscv/sifive_e.c > +++ b/hw/riscv/sifive_e.c > @@ -123,8 +123,6 @@ static void riscv_sifive_e_soc_init(Object *obj) > object_initialize_child(obj, "cpus", &s->cpus, > sizeof(s->cpus), TYPE_RISCV_HART_ARRAY, > &error_abort, NULL); > - object_property_set_str(OBJECT(&s->cpus), ms->cpu_type, "cpu-type", > - &error_abort); > object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts", > &error_abort); > sysbus_init_child_obj(obj, "riscv.sifive.e.gpio0", @@ -141,6 +139,8 @@ > static void riscv_sifive_e_soc_realize(DeviceState > *dev, Error **errp) > SiFiveESoCState *s = RISCV_E_SOC(dev); > MemoryRegion *sys_mem = get_system_memory(); > > + object_property_set_str(OBJECT(&s->cpus), ms->cpu_type, "cpu-type", > + &error_abort); > object_property_set_bool(OBJECT(&s->cpus), true, "realized", > &error_abort); > > > I'm happy to just squash that into the patch. Let me know if you don't want > me to do that and I'll drop these patches and let you re-send them. > > Alistair > Thanks for fixing this issue. I tested your patch and it seems to work as Intended and I'm fine with you squashing it into the patch. Corey > > --- > > hw/riscv/sifive_e.c | 3 ++- > > 1 file changed, 2 insertions(+), 1 deletion(-) > > > > diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index > > a254cad489..b0a611adb9 100644 > > --- a/hw/riscv/sifive_e.c > > +++ b/hw/riscv/sifive_e.c > > @@ -123,7 +123,7 @@ static void riscv_sifive_e_soc_init(Object *obj) > > object_initialize_child(obj, "cpus", &s->cpus, > > sizeof(s->cpus), TYPE_RISCV_HART_ARRAY, > > &error_abort, NULL); > > - object_property_set_str(OBJECT(&s->cpus), SIFIVE_E_CPU, "cpu-type", > > + object_property_set_str(OBJECT(&s->cpus), ms->cpu_type, > > + "cpu-type", > > &error_abort); > > object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num- > harts", > > &error_abort); @@ -220,6 +220,7 @@ static > > void riscv_sifive_e_machine_init(MachineClass *mc) > > mc->desc = "RISC-V Board compatible with SiFive E SDK"; > > mc->init = riscv_sifive_e_init; > > mc->max_cpus = 1; > > + mc->default_cpu_type = SIFIVE_E_CPU; > > } > > > > DEFINE_MACHINE("sifive_e", riscv_sifive_e_machine_init) > > -- > > 2.21.1 > > > > ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v2 1/2] riscv: sifive_e: Support changing CPU type 2020-04-24 19:12 ` Corey Wharton @ 2020-04-24 19:40 ` Alistair Francis 0 siblings, 0 replies; 21+ messages in thread From: Alistair Francis @ 2020-04-24 19:40 UTC (permalink / raw) To: Corey Wharton Cc: open list:RISC-V, Sagar Karandikar, Bastian Koppelmann, qemu-devel@nongnu.org Developers, Alistair Francis, Palmer Dabbelt, Bin Meng On Fri, Apr 24, 2020 at 12:12 PM Corey Wharton <coreyw7@fb.com> wrote: > > > > > -----Original Message----- > > From: Alistair Francis <alistair23@gmail.com> > > Sent: Friday, April 24, 2020 9:04 AM > > To: Corey Wharton <coreyw7@fb.com> > > Cc: qemu-devel@nongnu.org Developers <qemu-devel@nongnu.org>; open > > list:RISC-V <qemu-riscv@nongnu.org>; Sagar Karandikar > > <sagark@eecs.berkeley.edu>; Bastian Koppelmann <kbastian@mail.uni- > > paderborn.de>; Alistair Francis <alistair.francis@wdc.com>; Palmer Dabbelt > > <palmer@dabbelt.com>; Bin Meng <bmeng.cn@gmail.com> > > Subject: Re: [PATCH v2 1/2] riscv: sifive_e: Support changing CPU type > > > > On Fri, Mar 13, 2020 at 12:35 PM Corey Wharton <coreyw7@fb.com> wrote: > > > > > > Allows the CPU to be changed from the default via the -cpu command > > > line option. > > > > > > Signed-off-by: Corey Wharton <coreyw7@fb.com> > > > Reviewed-by: Bin Meng <bmeng.cn@gmail.com> > > > Reviewed-by: Alistair Francis <alistair.francis@wdc.com> > > > > Thanks for the patch. > > > > Unfortunately this fails `make check`. > > > > The problem is that the machine has the `default_cpu_type` set but then you > > set "cpu-type" from the SoC. > > > > This diff fixes the make check failure for me: > > > > diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index > > 1fd08f325c..b53109521e 100644 > > --- a/hw/riscv/sifive_e.c > > +++ b/hw/riscv/sifive_e.c > > @@ -123,8 +123,6 @@ static void riscv_sifive_e_soc_init(Object *obj) > > object_initialize_child(obj, "cpus", &s->cpus, > > sizeof(s->cpus), TYPE_RISCV_HART_ARRAY, > > &error_abort, NULL); > > - object_property_set_str(OBJECT(&s->cpus), ms->cpu_type, "cpu-type", > > - &error_abort); > > object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts", > > &error_abort); > > sysbus_init_child_obj(obj, "riscv.sifive.e.gpio0", @@ -141,6 +139,8 @@ > > static void riscv_sifive_e_soc_realize(DeviceState > > *dev, Error **errp) > > SiFiveESoCState *s = RISCV_E_SOC(dev); > > MemoryRegion *sys_mem = get_system_memory(); > > > > + object_property_set_str(OBJECT(&s->cpus), ms->cpu_type, "cpu-type", > > + &error_abort); > > object_property_set_bool(OBJECT(&s->cpus), true, "realized", > > &error_abort); > > > > > > I'm happy to just squash that into the patch. Let me know if you don't want > > me to do that and I'll drop these patches and let you re-send them. > > > > Alistair > > > > Thanks for fixing this issue. I tested your patch and it seems to work as > Intended and I'm fine with you squashing it into the patch. Great! I'll send this patch as part of the PR after 5.0 then. I also realised that my justification was wrong. It's not because of the machine/SoC split, but because of the order between init/realise. Alistair > > Corey > > > > --- > > > hw/riscv/sifive_e.c | 3 ++- > > > 1 file changed, 2 insertions(+), 1 deletion(-) > > > > > > diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index > > > a254cad489..b0a611adb9 100644 > > > --- a/hw/riscv/sifive_e.c > > > +++ b/hw/riscv/sifive_e.c > > > @@ -123,7 +123,7 @@ static void riscv_sifive_e_soc_init(Object *obj) > > > object_initialize_child(obj, "cpus", &s->cpus, > > > sizeof(s->cpus), TYPE_RISCV_HART_ARRAY, > > > &error_abort, NULL); > > > - object_property_set_str(OBJECT(&s->cpus), SIFIVE_E_CPU, "cpu-type", > > > + object_property_set_str(OBJECT(&s->cpus), ms->cpu_type, > > > + "cpu-type", > > > &error_abort); > > > object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num- > > harts", > > > &error_abort); @@ -220,6 +220,7 @@ static > > > void riscv_sifive_e_machine_init(MachineClass *mc) > > > mc->desc = "RISC-V Board compatible with SiFive E SDK"; > > > mc->init = riscv_sifive_e_init; > > > mc->max_cpus = 1; > > > + mc->default_cpu_type = SIFIVE_E_CPU; > > > } > > > > > > DEFINE_MACHINE("sifive_e", riscv_sifive_e_machine_init) > > > -- > > > 2.21.1 > > > > > > ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v2 1/2] riscv: sifive_e: Support changing CPU type @ 2020-04-24 19:40 ` Alistair Francis 0 siblings, 0 replies; 21+ messages in thread From: Alistair Francis @ 2020-04-24 19:40 UTC (permalink / raw) To: Corey Wharton Cc: qemu-devel@nongnu.org Developers, open list:RISC-V, Sagar Karandikar, Bastian Koppelmann, Alistair Francis, Palmer Dabbelt, Bin Meng On Fri, Apr 24, 2020 at 12:12 PM Corey Wharton <coreyw7@fb.com> wrote: > > > > > -----Original Message----- > > From: Alistair Francis <alistair23@gmail.com> > > Sent: Friday, April 24, 2020 9:04 AM > > To: Corey Wharton <coreyw7@fb.com> > > Cc: qemu-devel@nongnu.org Developers <qemu-devel@nongnu.org>; open > > list:RISC-V <qemu-riscv@nongnu.org>; Sagar Karandikar > > <sagark@eecs.berkeley.edu>; Bastian Koppelmann <kbastian@mail.uni- > > paderborn.de>; Alistair Francis <alistair.francis@wdc.com>; Palmer Dabbelt > > <palmer@dabbelt.com>; Bin Meng <bmeng.cn@gmail.com> > > Subject: Re: [PATCH v2 1/2] riscv: sifive_e: Support changing CPU type > > > > On Fri, Mar 13, 2020 at 12:35 PM Corey Wharton <coreyw7@fb.com> wrote: > > > > > > Allows the CPU to be changed from the default via the -cpu command > > > line option. > > > > > > Signed-off-by: Corey Wharton <coreyw7@fb.com> > > > Reviewed-by: Bin Meng <bmeng.cn@gmail.com> > > > Reviewed-by: Alistair Francis <alistair.francis@wdc.com> > > > > Thanks for the patch. > > > > Unfortunately this fails `make check`. > > > > The problem is that the machine has the `default_cpu_type` set but then you > > set "cpu-type" from the SoC. > > > > This diff fixes the make check failure for me: > > > > diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index > > 1fd08f325c..b53109521e 100644 > > --- a/hw/riscv/sifive_e.c > > +++ b/hw/riscv/sifive_e.c > > @@ -123,8 +123,6 @@ static void riscv_sifive_e_soc_init(Object *obj) > > object_initialize_child(obj, "cpus", &s->cpus, > > sizeof(s->cpus), TYPE_RISCV_HART_ARRAY, > > &error_abort, NULL); > > - object_property_set_str(OBJECT(&s->cpus), ms->cpu_type, "cpu-type", > > - &error_abort); > > object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts", > > &error_abort); > > sysbus_init_child_obj(obj, "riscv.sifive.e.gpio0", @@ -141,6 +139,8 @@ > > static void riscv_sifive_e_soc_realize(DeviceState > > *dev, Error **errp) > > SiFiveESoCState *s = RISCV_E_SOC(dev); > > MemoryRegion *sys_mem = get_system_memory(); > > > > + object_property_set_str(OBJECT(&s->cpus), ms->cpu_type, "cpu-type", > > + &error_abort); > > object_property_set_bool(OBJECT(&s->cpus), true, "realized", > > &error_abort); > > > > > > I'm happy to just squash that into the patch. Let me know if you don't want > > me to do that and I'll drop these patches and let you re-send them. > > > > Alistair > > > > Thanks for fixing this issue. I tested your patch and it seems to work as > Intended and I'm fine with you squashing it into the patch. Great! I'll send this patch as part of the PR after 5.0 then. I also realised that my justification was wrong. It's not because of the machine/SoC split, but because of the order between init/realise. Alistair > > Corey > > > > --- > > > hw/riscv/sifive_e.c | 3 ++- > > > 1 file changed, 2 insertions(+), 1 deletion(-) > > > > > > diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index > > > a254cad489..b0a611adb9 100644 > > > --- a/hw/riscv/sifive_e.c > > > +++ b/hw/riscv/sifive_e.c > > > @@ -123,7 +123,7 @@ static void riscv_sifive_e_soc_init(Object *obj) > > > object_initialize_child(obj, "cpus", &s->cpus, > > > sizeof(s->cpus), TYPE_RISCV_HART_ARRAY, > > > &error_abort, NULL); > > > - object_property_set_str(OBJECT(&s->cpus), SIFIVE_E_CPU, "cpu-type", > > > + object_property_set_str(OBJECT(&s->cpus), ms->cpu_type, > > > + "cpu-type", > > > &error_abort); > > > object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num- > > harts", > > > &error_abort); @@ -220,6 +220,7 @@ static > > > void riscv_sifive_e_machine_init(MachineClass *mc) > > > mc->desc = "RISC-V Board compatible with SiFive E SDK"; > > > mc->init = riscv_sifive_e_init; > > > mc->max_cpus = 1; > > > + mc->default_cpu_type = SIFIVE_E_CPU; > > > } > > > > > > DEFINE_MACHINE("sifive_e", riscv_sifive_e_machine_init) > > > -- > > > 2.21.1 > > > > > > ^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v2 2/2] target/riscv: Add a sifive-e34 cpu type 2020-03-13 19:34 ` Corey Wharton @ 2020-03-13 19:34 ` Corey Wharton -1 siblings, 0 replies; 21+ messages in thread From: Corey Wharton @ 2020-03-13 19:34 UTC (permalink / raw) To: qemu-devel, qemu-riscv Cc: Sagar Karandikar, Corey Wharton, Bastian Koppelmann, Alistair Francis, Palmer Dabbelt, Bin Meng The sifive-e34 cpu type is the same as the sifive-e31 with the single precision floating-point extension enabled. Signed-off-by: Corey Wharton <coreyw7@fb.com> --- v2: Added missing RVU flag target/riscv/cpu.c | 10 ++++++++++ target/riscv/cpu.h | 1 + 2 files changed, 11 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c0b7023100..1ae9d085b8 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -164,6 +164,15 @@ static void rv32imacu_nommu_cpu_init(Object *obj) set_feature(env, RISCV_FEATURE_PMP); } +static void rv32imafcu_nommu_cpu_init(Object *obj) +{ + CPURISCVState *env = &RISCV_CPU(obj)->env; + set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC | RVU); + set_priv_version(env, PRIV_VERSION_1_10_0); + set_resetvec(env, DEFAULT_RSTVEC); + set_feature(env, RISCV_FEATURE_PMP); +} + #elif defined(TARGET_RISCV64) static void riscv_base64_cpu_init(Object *obj) @@ -609,6 +618,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { #if defined(TARGET_RISCV32) DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base32_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32imafcu_nommu_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init), /* Depreacted */ DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU, rv32imacu_nommu_cpu_init), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 3dcdf92227..ae5a1d9dce 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -36,6 +36,7 @@ #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") +#define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") -- 2.21.1 ^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v2 2/2] target/riscv: Add a sifive-e34 cpu type @ 2020-03-13 19:34 ` Corey Wharton 0 siblings, 0 replies; 21+ messages in thread From: Corey Wharton @ 2020-03-13 19:34 UTC (permalink / raw) To: qemu-devel, qemu-riscv Cc: Palmer Dabbelt, Alistair Francis, Sagar Karandikar, Bastian Koppelmann, Bin Meng, Corey Wharton The sifive-e34 cpu type is the same as the sifive-e31 with the single precision floating-point extension enabled. Signed-off-by: Corey Wharton <coreyw7@fb.com> --- v2: Added missing RVU flag target/riscv/cpu.c | 10 ++++++++++ target/riscv/cpu.h | 1 + 2 files changed, 11 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c0b7023100..1ae9d085b8 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -164,6 +164,15 @@ static void rv32imacu_nommu_cpu_init(Object *obj) set_feature(env, RISCV_FEATURE_PMP); } +static void rv32imafcu_nommu_cpu_init(Object *obj) +{ + CPURISCVState *env = &RISCV_CPU(obj)->env; + set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC | RVU); + set_priv_version(env, PRIV_VERSION_1_10_0); + set_resetvec(env, DEFAULT_RSTVEC); + set_feature(env, RISCV_FEATURE_PMP); +} + #elif defined(TARGET_RISCV64) static void riscv_base64_cpu_init(Object *obj) @@ -609,6 +618,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { #if defined(TARGET_RISCV32) DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base32_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32imafcu_nommu_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init), /* Depreacted */ DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU, rv32imacu_nommu_cpu_init), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 3dcdf92227..ae5a1d9dce 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -36,6 +36,7 @@ #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") +#define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") -- 2.21.1 ^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH v2 2/2] target/riscv: Add a sifive-e34 cpu type 2020-03-13 19:34 ` Corey Wharton @ 2020-03-13 20:00 ` Alistair Francis -1 siblings, 0 replies; 21+ messages in thread From: Alistair Francis @ 2020-03-13 20:00 UTC (permalink / raw) To: Corey Wharton Cc: open list:RISC-V, Sagar Karandikar, Bastian Koppelmann, qemu-devel@nongnu.org Developers, Alistair Francis, Palmer Dabbelt, Bin Meng On Fri, Mar 13, 2020 at 12:37 PM Corey Wharton <coreyw7@fb.com> wrote: > > The sifive-e34 cpu type is the same as the sifive-e31 with the > single precision floating-point extension enabled. > > Signed-off-by: Corey Wharton <coreyw7@fb.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > v2: Added missing RVU flag > > target/riscv/cpu.c | 10 ++++++++++ > target/riscv/cpu.h | 1 + > 2 files changed, 11 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index c0b7023100..1ae9d085b8 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -164,6 +164,15 @@ static void rv32imacu_nommu_cpu_init(Object *obj) > set_feature(env, RISCV_FEATURE_PMP); > } > > +static void rv32imafcu_nommu_cpu_init(Object *obj) > +{ > + CPURISCVState *env = &RISCV_CPU(obj)->env; > + set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC | RVU); > + set_priv_version(env, PRIV_VERSION_1_10_0); > + set_resetvec(env, DEFAULT_RSTVEC); > + set_feature(env, RISCV_FEATURE_PMP); > +} > + > #elif defined(TARGET_RISCV64) > > static void riscv_base64_cpu_init(Object *obj) > @@ -609,6 +618,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { > #if defined(TARGET_RISCV32) > DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base32_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init), > + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32imafcu_nommu_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init), > /* Depreacted */ > DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU, rv32imacu_nommu_cpu_init), > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 3dcdf92227..ae5a1d9dce 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -36,6 +36,7 @@ > #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") > #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") > #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") > +#define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") > #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") > #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") > #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") > -- > 2.21.1 > > ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v2 2/2] target/riscv: Add a sifive-e34 cpu type @ 2020-03-13 20:00 ` Alistair Francis 0 siblings, 0 replies; 21+ messages in thread From: Alistair Francis @ 2020-03-13 20:00 UTC (permalink / raw) To: Corey Wharton Cc: qemu-devel@nongnu.org Developers, open list:RISC-V, Sagar Karandikar, Bastian Koppelmann, Alistair Francis, Palmer Dabbelt, Bin Meng On Fri, Mar 13, 2020 at 12:37 PM Corey Wharton <coreyw7@fb.com> wrote: > > The sifive-e34 cpu type is the same as the sifive-e31 with the > single precision floating-point extension enabled. > > Signed-off-by: Corey Wharton <coreyw7@fb.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > v2: Added missing RVU flag > > target/riscv/cpu.c | 10 ++++++++++ > target/riscv/cpu.h | 1 + > 2 files changed, 11 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index c0b7023100..1ae9d085b8 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -164,6 +164,15 @@ static void rv32imacu_nommu_cpu_init(Object *obj) > set_feature(env, RISCV_FEATURE_PMP); > } > > +static void rv32imafcu_nommu_cpu_init(Object *obj) > +{ > + CPURISCVState *env = &RISCV_CPU(obj)->env; > + set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC | RVU); > + set_priv_version(env, PRIV_VERSION_1_10_0); > + set_resetvec(env, DEFAULT_RSTVEC); > + set_feature(env, RISCV_FEATURE_PMP); > +} > + > #elif defined(TARGET_RISCV64) > > static void riscv_base64_cpu_init(Object *obj) > @@ -609,6 +618,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { > #if defined(TARGET_RISCV32) > DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base32_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init), > + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32imafcu_nommu_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init), > /* Depreacted */ > DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU, rv32imacu_nommu_cpu_init), > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 3dcdf92227..ae5a1d9dce 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -36,6 +36,7 @@ > #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") > #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") > #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") > +#define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") > #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") > #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") > #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") > -- > 2.21.1 > > ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v2 2/2] target/riscv: Add a sifive-e34 cpu type 2020-03-13 19:34 ` Corey Wharton @ 2020-03-14 2:47 ` Bin Meng -1 siblings, 0 replies; 21+ messages in thread From: Bin Meng @ 2020-03-14 2:47 UTC (permalink / raw) To: Corey Wharton Cc: open list:RISC-V, Sagar Karandikar, Bastian Koppelmann, qemu-devel@nongnu.org Developers, Palmer Dabbelt, Alistair Francis On Sat, Mar 14, 2020 at 3:35 AM Corey Wharton <coreyw7@fb.com> wrote: > > The sifive-e34 cpu type is the same as the sifive-e31 with the > single precision floating-point extension enabled. > > Signed-off-by: Corey Wharton <coreyw7@fb.com> > --- > v2: Added missing RVU flag > > target/riscv/cpu.c | 10 ++++++++++ > target/riscv/cpu.h | 1 + > 2 files changed, 11 insertions(+) > Reviewed-by: Bin Meng <bmeng.cn@gmail.com> ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v2 2/2] target/riscv: Add a sifive-e34 cpu type @ 2020-03-14 2:47 ` Bin Meng 0 siblings, 0 replies; 21+ messages in thread From: Bin Meng @ 2020-03-14 2:47 UTC (permalink / raw) To: Corey Wharton Cc: qemu-devel@nongnu.org Developers, open list:RISC-V, Palmer Dabbelt, Alistair Francis, Sagar Karandikar, Bastian Koppelmann On Sat, Mar 14, 2020 at 3:35 AM Corey Wharton <coreyw7@fb.com> wrote: > > The sifive-e34 cpu type is the same as the sifive-e31 with the > single precision floating-point extension enabled. > > Signed-off-by: Corey Wharton <coreyw7@fb.com> > --- > v2: Added missing RVU flag > > target/riscv/cpu.c | 10 ++++++++++ > target/riscv/cpu.h | 1 + > 2 files changed, 11 insertions(+) > Reviewed-by: Bin Meng <bmeng.cn@gmail.com> ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v2 0/2] Support different CPU types for the sifive_e machine 2020-03-13 19:34 ` Corey Wharton @ 2020-04-06 17:20 ` Corey Wharton -1 siblings, 0 replies; 21+ messages in thread From: Corey Wharton @ 2020-04-06 17:20 UTC (permalink / raw) To: qemu-devel, qemu-riscv Cc: Alistair Francis, Bin Meng, Palmer Dabbelt, Sagar Karandikar, Bastian Koppelmann [-- Attachment #1: Type: text/plain, Size: 1312 bytes --] ping https://patchwork.kernel.org/patch/11437661/ https://patchwork.kernel.org/patch/11437665/ ________________________________ From: Corey Wharton <coreyw7@fb.com> Sent: Friday, March 13, 2020 12:35 PM To: qemu-devel@nongnu.org <qemu-devel@nongnu.org>; qemu-riscv@nongnu.org <qemu-riscv@nongnu.org> Cc: Palmer Dabbelt <palmer@dabbelt.com>; Alistair Francis <Alistair.Francis@wdc.com>; Sagar Karandikar <sagark@eecs.berkeley.edu>; Bastian Koppelmann <kbastian@mail.uni-paderborn.de>; Bin Meng <bmeng.cn@gmail.com>; Corey Wharton <coreyw7@fb.com> Subject: [PATCH v2 0/2] Support different CPU types for the sifive_e machine The purpose of this patch set is to allow the sifive_e machine to run with different CPU targets to enable different ISA entensions. To that end it also introduces a new sifive-e34 CPU type which provides the same ISA as sifive-e31, with the addition of the single precision floating-point extension (f). The default CPU for the sifive_e machine is unchanged. v2: Added missing RVU flag Corey Wharton (2): riscv: sifive_e: Support changing CPU type target/riscv: Add a sifive-e34 cpu type hw/riscv/sifive_e.c | 3 ++- target/riscv/cpu.c | 10 ++++++++++ target/riscv/cpu.h | 1 + 3 files changed, 13 insertions(+), 1 deletion(-) -- 2.21.1 [-- Attachment #2: Type: text/html, Size: 2527 bytes --] ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v2 0/2] Support different CPU types for the sifive_e machine @ 2020-04-06 17:20 ` Corey Wharton 0 siblings, 0 replies; 21+ messages in thread From: Corey Wharton @ 2020-04-06 17:20 UTC (permalink / raw) To: qemu-devel, qemu-riscv Cc: Palmer Dabbelt, Alistair Francis, Sagar Karandikar, Bastian Koppelmann, Bin Meng [-- Attachment #1: Type: text/plain, Size: 1312 bytes --] ping https://patchwork.kernel.org/patch/11437661/ https://patchwork.kernel.org/patch/11437665/ ________________________________ From: Corey Wharton <coreyw7@fb.com> Sent: Friday, March 13, 2020 12:35 PM To: qemu-devel@nongnu.org <qemu-devel@nongnu.org>; qemu-riscv@nongnu.org <qemu-riscv@nongnu.org> Cc: Palmer Dabbelt <palmer@dabbelt.com>; Alistair Francis <Alistair.Francis@wdc.com>; Sagar Karandikar <sagark@eecs.berkeley.edu>; Bastian Koppelmann <kbastian@mail.uni-paderborn.de>; Bin Meng <bmeng.cn@gmail.com>; Corey Wharton <coreyw7@fb.com> Subject: [PATCH v2 0/2] Support different CPU types for the sifive_e machine The purpose of this patch set is to allow the sifive_e machine to run with different CPU targets to enable different ISA entensions. To that end it also introduces a new sifive-e34 CPU type which provides the same ISA as sifive-e31, with the addition of the single precision floating-point extension (f). The default CPU for the sifive_e machine is unchanged. v2: Added missing RVU flag Corey Wharton (2): riscv: sifive_e: Support changing CPU type target/riscv: Add a sifive-e34 cpu type hw/riscv/sifive_e.c | 3 ++- target/riscv/cpu.c | 10 ++++++++++ target/riscv/cpu.h | 1 + 3 files changed, 13 insertions(+), 1 deletion(-) -- 2.21.1 [-- Attachment #2: Type: text/html, Size: 2527 bytes --] ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v2 0/2] Support different CPU types for the sifive_e machine 2020-03-13 19:34 ` Corey Wharton @ 2020-04-20 19:22 ` Alistair Francis -1 siblings, 0 replies; 21+ messages in thread From: Alistair Francis @ 2020-04-20 19:22 UTC (permalink / raw) To: Corey Wharton Cc: open list:RISC-V, Sagar Karandikar, Bastian Koppelmann, qemu-devel@nongnu.org Developers, Alistair Francis, Palmer Dabbelt, Bin Meng On Fri, Mar 13, 2020 at 12:36 PM Corey Wharton <coreyw7@fb.com> wrote: > > The purpose of this patch set is to allow the sifive_e machine to run > with different CPU targets to enable different ISA entensions. To that > end it also introduces a new sifive-e34 CPU type which provides the > same ISA as sifive-e31, with the addition of the single precision > floating-point extension (f). The default CPU for the sifive_e machine > is unchanged. > > v2: Added missing RVU flag Applied to the RISC-V tree for 5.1 Alistair > > Corey Wharton (2): > riscv: sifive_e: Support changing CPU type > target/riscv: Add a sifive-e34 cpu type > > hw/riscv/sifive_e.c | 3 ++- > target/riscv/cpu.c | 10 ++++++++++ > target/riscv/cpu.h | 1 + > 3 files changed, 13 insertions(+), 1 deletion(-) > > -- > 2.21.1 > > ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v2 0/2] Support different CPU types for the sifive_e machine @ 2020-04-20 19:22 ` Alistair Francis 0 siblings, 0 replies; 21+ messages in thread From: Alistair Francis @ 2020-04-20 19:22 UTC (permalink / raw) To: Corey Wharton Cc: qemu-devel@nongnu.org Developers, open list:RISC-V, Sagar Karandikar, Bastian Koppelmann, Alistair Francis, Palmer Dabbelt, Bin Meng On Fri, Mar 13, 2020 at 12:36 PM Corey Wharton <coreyw7@fb.com> wrote: > > The purpose of this patch set is to allow the sifive_e machine to run > with different CPU targets to enable different ISA entensions. To that > end it also introduces a new sifive-e34 CPU type which provides the > same ISA as sifive-e31, with the addition of the single precision > floating-point extension (f). The default CPU for the sifive_e machine > is unchanged. > > v2: Added missing RVU flag Applied to the RISC-V tree for 5.1 Alistair > > Corey Wharton (2): > riscv: sifive_e: Support changing CPU type > target/riscv: Add a sifive-e34 cpu type > > hw/riscv/sifive_e.c | 3 ++- > target/riscv/cpu.c | 10 ++++++++++ > target/riscv/cpu.h | 1 + > 3 files changed, 13 insertions(+), 1 deletion(-) > > -- > 2.21.1 > > ^ permalink raw reply [flat|nested] 21+ messages in thread
end of thread, other threads:[~2020-04-24 19:49 UTC | newest] Thread overview: 21+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-03-13 19:34 [PATCH v2 0/2] Support different CPU types for the sifive_e machine Corey Wharton 2020-03-13 19:34 ` Corey Wharton 2020-03-13 19:34 ` [PATCH v2 1/2] riscv: sifive_e: Support changing CPU type Corey Wharton 2020-03-13 19:34 ` Corey Wharton 2020-03-13 19:46 ` Philippe Mathieu-Daudé 2020-03-13 19:46 ` Philippe Mathieu-Daudé 2020-04-24 16:03 ` Alistair Francis 2020-04-24 16:03 ` Alistair Francis 2020-04-24 19:12 ` Corey Wharton 2020-04-24 19:40 ` Alistair Francis 2020-04-24 19:40 ` Alistair Francis 2020-03-13 19:34 ` [PATCH v2 2/2] target/riscv: Add a sifive-e34 cpu type Corey Wharton 2020-03-13 19:34 ` Corey Wharton 2020-03-13 20:00 ` Alistair Francis 2020-03-13 20:00 ` Alistair Francis 2020-03-14 2:47 ` Bin Meng 2020-03-14 2:47 ` Bin Meng 2020-04-06 17:20 ` [PATCH v2 0/2] Support different CPU types for the sifive_e machine Corey Wharton 2020-04-06 17:20 ` Corey Wharton 2020-04-20 19:22 ` Alistair Francis 2020-04-20 19:22 ` Alistair Francis
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