[PATCH-for-5.0 03/12] hw/arm/fsl-imx: Add missing error-propagation code

["Philippe Mathieu-Daudé" <f4bug@amsat.org>]

Patch created mechanically by running:

  $ spatch \
    --macro-file scripts/cocci-macro-file.h --include-headers \
    --sp-file scripts/coccinelle/object_property_missing_error_propagate.cocci \
    --keep-comments --smpl-spacing --in-place --dir hw

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 hw/arm/fsl-imx25.c | 8 ++++++++
 hw/arm/fsl-imx6.c  | 8 ++++++++
 2 files changed, 16 insertions(+)

diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c
index 6f1a82ce3d..c915a2106d 100644
--- a/hw/arm/fsl-imx25.c
+++ b/hw/arm/fsl-imx25.c
@@ -92,247 +92,255 @@ static void fsl_imx25_init(Object *obj)
 static void fsl_imx25_realize(DeviceState *dev, Error **errp)
 {
     FslIMX25State *s = FSL_IMX25(dev);
     uint8_t i;
     Error *err = NULL;
 
     object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
     if (err) {
         error_propagate(errp, err);
         return;
     }
 
     object_property_set_bool(OBJECT(&s->avic), true, "realized", &err);
     if (err) {
         error_propagate(errp, err);
         return;
     }
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->avic), 0, FSL_IMX25_AVIC_ADDR);
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 0,
                        qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1,
                        qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
 
     object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err);
     if (err) {
         error_propagate(errp, err);
         return;
     }
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX25_CCM_ADDR);
 
     /* Initialize all UARTs */
     for (i = 0; i < FSL_IMX25_NUM_UARTS; i++) {
         static const struct {
             hwaddr addr;
             unsigned int irq;
         } serial_table[FSL_IMX25_NUM_UARTS] = {
             { FSL_IMX25_UART1_ADDR, FSL_IMX25_UART1_IRQ },
             { FSL_IMX25_UART2_ADDR, FSL_IMX25_UART2_IRQ },
             { FSL_IMX25_UART3_ADDR, FSL_IMX25_UART3_IRQ },
             { FSL_IMX25_UART4_ADDR, FSL_IMX25_UART4_IRQ },
             { FSL_IMX25_UART5_ADDR, FSL_IMX25_UART5_IRQ }
         };
 
         qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
 
         object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
         if (err) {
             error_propagate(errp, err);
             return;
         }
         sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
                            qdev_get_gpio_in(DEVICE(&s->avic),
                                             serial_table[i].irq));
     }
 
     /* Initialize all GPT timers */
     for (i = 0; i < FSL_IMX25_NUM_GPTS; i++) {
         static const struct {
             hwaddr addr;
             unsigned int irq;
         } gpt_table[FSL_IMX25_NUM_GPTS] = {
             { FSL_IMX25_GPT1_ADDR, FSL_IMX25_GPT1_IRQ },
             { FSL_IMX25_GPT2_ADDR, FSL_IMX25_GPT2_IRQ },
             { FSL_IMX25_GPT3_ADDR, FSL_IMX25_GPT3_IRQ },
             { FSL_IMX25_GPT4_ADDR, FSL_IMX25_GPT4_IRQ }
         };
 
         s->gpt[i].ccm = IMX_CCM(&s->ccm);
 
         object_property_set_bool(OBJECT(&s->gpt[i]), true, "realized", &err);
         if (err) {
             error_propagate(errp, err);
             return;
         }
         sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, gpt_table[i].addr);
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0,
                            qdev_get_gpio_in(DEVICE(&s->avic),
                                             gpt_table[i].irq));
     }
 
     /* Initialize all EPIT timers */
     for (i = 0; i < FSL_IMX25_NUM_EPITS; i++) {
         static const struct {
             hwaddr addr;
             unsigned int irq;
         } epit_table[FSL_IMX25_NUM_EPITS] = {
             { FSL_IMX25_EPIT1_ADDR, FSL_IMX25_EPIT1_IRQ },
             { FSL_IMX25_EPIT2_ADDR, FSL_IMX25_EPIT2_IRQ }
         };
 
         s->epit[i].ccm = IMX_CCM(&s->ccm);
 
         object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err);
         if (err) {
             error_propagate(errp, err);
             return;
         }
         sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr);
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
                            qdev_get_gpio_in(DEVICE(&s->avic),
                                             epit_table[i].irq));
     }
 
     qdev_set_nic_properties(DEVICE(&s->fec), &nd_table[0]);
 
     object_property_set_bool(OBJECT(&s->fec), true, "realized", &err);
     if (err) {
         error_propagate(errp, err);
         return;
     }
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->fec), 0, FSL_IMX25_FEC_ADDR);
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->fec), 0,
                        qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX25_FEC_IRQ));
 
     object_property_set_bool(OBJECT(&s->rngc), true, "realized", &err);
     if (err) {
         error_propagate(errp, err);
         return;
     }
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->rngc), 0, FSL_IMX25_RNGC_ADDR);
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->rngc), 0,
                        qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX25_RNGC_IRQ));
 
     /* Initialize all I2C */
     for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) {
         static const struct {
             hwaddr addr;
             unsigned int irq;
         } i2c_table[FSL_IMX25_NUM_I2CS] = {
             { FSL_IMX25_I2C1_ADDR, FSL_IMX25_I2C1_IRQ },
             { FSL_IMX25_I2C2_ADDR, FSL_IMX25_I2C2_IRQ },
             { FSL_IMX25_I2C3_ADDR, FSL_IMX25_I2C3_IRQ }
         };
 
         object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err);
         if (err) {
             error_propagate(errp, err);
             return;
         }
         sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr);
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
                            qdev_get_gpio_in(DEVICE(&s->avic),
                                             i2c_table[i].irq));
     }
 
     /* Initialize all GPIOs */
     for (i = 0; i < FSL_IMX25_NUM_GPIOS; i++) {
         static const struct {
             hwaddr addr;
             unsigned int irq;
         } gpio_table[FSL_IMX25_NUM_GPIOS] = {
             { FSL_IMX25_GPIO1_ADDR, FSL_IMX25_GPIO1_IRQ },
             { FSL_IMX25_GPIO2_ADDR, FSL_IMX25_GPIO2_IRQ },
             { FSL_IMX25_GPIO3_ADDR, FSL_IMX25_GPIO3_IRQ },
             { FSL_IMX25_GPIO4_ADDR, FSL_IMX25_GPIO4_IRQ }
         };
 
         object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", &err);
         if (err) {
             error_propagate(errp, err);
             return;
         }
         sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);
         /* Connect GPIO IRQ to PIC */
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
                            qdev_get_gpio_in(DEVICE(&s->avic),
                                             gpio_table[i].irq));
     }
 
     /* Initialize all SDHC */
     for (i = 0; i < FSL_IMX25_NUM_ESDHCS; i++) {
         static const struct {
             hwaddr addr;
             unsigned int irq;
         } esdhc_table[FSL_IMX25_NUM_ESDHCS] = {
             { FSL_IMX25_ESDHC1_ADDR, FSL_IMX25_ESDHC1_IRQ },
             { FSL_IMX25_ESDHC2_ADDR, FSL_IMX25_ESDHC2_IRQ },
         };
 
         object_property_set_uint(OBJECT(&s->esdhc[i]), 2, "sd-spec-version",
                                  &err);
+        if (err) {
+            error_propagate(errp, err);
+            return;
+        }
         object_property_set_uint(OBJECT(&s->esdhc[i]), IMX25_ESDHC_CAPABILITIES,
                                  "capareg", &err);
+        if (err) {
+            error_propagate(errp, err);
+            return;
+        }
         object_property_set_bool(OBJECT(&s->esdhc[i]), true, "realized", &err);
         if (err) {
             error_propagate(errp, err);
             return;
         }
         sysbus_mmio_map(SYS_BUS_DEVICE(&s->esdhc[i]), 0, esdhc_table[i].addr);
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->esdhc[i]), 0,
                            qdev_get_gpio_in(DEVICE(&s->avic),
                                             esdhc_table[i].irq));
     }
 
     /* USB */
     for (i = 0; i < FSL_IMX25_NUM_USBS; i++) {
         static const struct {
             hwaddr addr;
             unsigned int irq;
         } usb_table[FSL_IMX25_NUM_USBS] = {
             { FSL_IMX25_USB1_ADDR, FSL_IMX25_USB1_IRQ },
             { FSL_IMX25_USB2_ADDR, FSL_IMX25_USB2_IRQ },
         };
 
         object_property_set_bool(OBJECT(&s->usb[i]), true, "realized",
                                  &error_abort);
         sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, usb_table[i].addr);
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
                            qdev_get_gpio_in(DEVICE(&s->avic),
                                             usb_table[i].irq));
     }
 
     /* initialize 2 x 16 KB ROM */
     memory_region_init_rom(&s->rom[0], OBJECT(dev), "imx25.rom0",
                            FSL_IMX25_ROM0_SIZE, &err);
     if (err) {
         error_propagate(errp, err);
         return;
     }
     memory_region_add_subregion(get_system_memory(), FSL_IMX25_ROM0_ADDR,
                                 &s->rom[0]);
     memory_region_init_rom(&s->rom[1], OBJECT(dev), "imx25.rom1",
                            FSL_IMX25_ROM1_SIZE, &err);
     if (err) {
         error_propagate(errp, err);
         return;
     }
     memory_region_add_subregion(get_system_memory(), FSL_IMX25_ROM1_ADDR,
                                 &s->rom[1]);
 
     /* initialize internal RAM (128 KB) */
     memory_region_init_ram(&s->iram, NULL, "imx25.iram", FSL_IMX25_IRAM_SIZE,
                            &err);
     if (err) {
         error_propagate(errp, err);
         return;
     }
     memory_region_add_subregion(get_system_memory(), FSL_IMX25_IRAM_ADDR,
                                 &s->iram);
 
     /* internal RAM (128 KB) is aliased over 128 MB - 128 KB */
     memory_region_init_alias(&s->iram_alias, OBJECT(dev), "imx25.iram_alias",
                              &s->iram, 0, FSL_IMX25_IRAM_ALIAS_SIZE);
     memory_region_add_subregion(get_system_memory(), FSL_IMX25_IRAM_ALIAS_ADDR,
                                 &s->iram_alias);
 }
diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c
index 13f1bf23a6..71b2729298 100644
--- a/hw/arm/fsl-imx6.c
+++ b/hw/arm/fsl-imx6.c
@@ -116,363 +116,371 @@ static void fsl_imx6_init(Object *obj)
 static void fsl_imx6_realize(DeviceState *dev, Error **errp)
 {
     MachineState *ms = MACHINE(qdev_get_machine());
     FslIMX6State *s = FSL_IMX6(dev);
     uint16_t i;
     Error *err = NULL;
     unsigned int smp_cpus = ms->smp.cpus;
 
     if (smp_cpus > FSL_IMX6_NUM_CPUS) {
         error_setg(errp, "%s: Only %d CPUs are supported (%d requested)",
                    TYPE_FSL_IMX6, FSL_IMX6_NUM_CPUS, smp_cpus);
         return;
     }
 
     for (i = 0; i < smp_cpus; i++) {
 
         /* On uniprocessor, the CBAR is set to 0 */
         if (smp_cpus > 1) {
             object_property_set_int(OBJECT(&s->cpu[i]), FSL_IMX6_A9MPCORE_ADDR,
                                     "reset-cbar", &error_abort);
         }
 
         /* All CPU but CPU 0 start in power off mode */
         if (i) {
             object_property_set_bool(OBJECT(&s->cpu[i]), true,
                                      "start-powered-off", &error_abort);
         }
 
         object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
         if (err) {
             error_propagate(errp, err);
             return;
         }
     }
 
     object_property_set_int(OBJECT(&s->a9mpcore), smp_cpus, "num-cpu",
                             &error_abort);
 
     object_property_set_int(OBJECT(&s->a9mpcore),
                             FSL_IMX6_MAX_IRQ + GIC_INTERNAL, "num-irq",
                             &error_abort);
 
     object_property_set_bool(OBJECT(&s->a9mpcore), true, "realized", &err);
     if (err) {
         error_propagate(errp, err);
         return;
     }
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->a9mpcore), 0, FSL_IMX6_A9MPCORE_ADDR);
 
     for (i = 0; i < smp_cpus; i++) {
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i,
                            qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ));
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i + smp_cpus,
                            qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ));
     }
 
     object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err);
     if (err) {
         error_propagate(errp, err);
         return;
     }
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX6_CCM_ADDR);
 
     object_property_set_bool(OBJECT(&s->src), true, "realized", &err);
     if (err) {
         error_propagate(errp, err);
         return;
     }
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX6_SRC_ADDR);
 
     /* Initialize all UARTs */
     for (i = 0; i < FSL_IMX6_NUM_UARTS; i++) {
         static const struct {
             hwaddr addr;
             unsigned int irq;
         } serial_table[FSL_IMX6_NUM_UARTS] = {
             { FSL_IMX6_UART1_ADDR, FSL_IMX6_UART1_IRQ },
             { FSL_IMX6_UART2_ADDR, FSL_IMX6_UART2_IRQ },
             { FSL_IMX6_UART3_ADDR, FSL_IMX6_UART3_IRQ },
             { FSL_IMX6_UART4_ADDR, FSL_IMX6_UART4_IRQ },
             { FSL_IMX6_UART5_ADDR, FSL_IMX6_UART5_IRQ },
         };
 
         qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
 
         object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
         if (err) {
             error_propagate(errp, err);
             return;
         }
 
         sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
                            qdev_get_gpio_in(DEVICE(&s->a9mpcore),
                                             serial_table[i].irq));
     }
 
     s->gpt.ccm = IMX_CCM(&s->ccm);
 
     object_property_set_bool(OBJECT(&s->gpt), true, "realized", &err);
     if (err) {
         error_propagate(errp, err);
         return;
     }
 
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, FSL_IMX6_GPT_ADDR);
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), 0,
                        qdev_get_gpio_in(DEVICE(&s->a9mpcore),
                                         FSL_IMX6_GPT_IRQ));
 
     /* Initialize all EPIT timers */
     for (i = 0; i < FSL_IMX6_NUM_EPITS; i++) {
         static const struct {
             hwaddr addr;
             unsigned int irq;
         } epit_table[FSL_IMX6_NUM_EPITS] = {
             { FSL_IMX6_EPIT1_ADDR, FSL_IMX6_EPIT1_IRQ },
             { FSL_IMX6_EPIT2_ADDR, FSL_IMX6_EPIT2_IRQ },
         };
 
         s->epit[i].ccm = IMX_CCM(&s->ccm);
 
         object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err);
         if (err) {
             error_propagate(errp, err);
             return;
         }
 
         sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr);
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
                            qdev_get_gpio_in(DEVICE(&s->a9mpcore),
                                             epit_table[i].irq));
     }
 
     /* Initialize all I2C */
     for (i = 0; i < FSL_IMX6_NUM_I2CS; i++) {
         static const struct {
             hwaddr addr;
             unsigned int irq;
         } i2c_table[FSL_IMX6_NUM_I2CS] = {
             { FSL_IMX6_I2C1_ADDR, FSL_IMX6_I2C1_IRQ },
             { FSL_IMX6_I2C2_ADDR, FSL_IMX6_I2C2_IRQ },
             { FSL_IMX6_I2C3_ADDR, FSL_IMX6_I2C3_IRQ }
         };
 
         object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err);
         if (err) {
             error_propagate(errp, err);
             return;
         }
 
         sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr);
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
                            qdev_get_gpio_in(DEVICE(&s->a9mpcore),
                                             i2c_table[i].irq));
     }
 
     /* Initialize all GPIOs */
     for (i = 0; i < FSL_IMX6_NUM_GPIOS; i++) {
         static const struct {
             hwaddr addr;
             unsigned int irq_low;
             unsigned int irq_high;
         } gpio_table[FSL_IMX6_NUM_GPIOS] = {
             {
                 FSL_IMX6_GPIO1_ADDR,
                 FSL_IMX6_GPIO1_LOW_IRQ,
                 FSL_IMX6_GPIO1_HIGH_IRQ
             },
             {
                 FSL_IMX6_GPIO2_ADDR,
                 FSL_IMX6_GPIO2_LOW_IRQ,
                 FSL_IMX6_GPIO2_HIGH_IRQ
             },
             {
                 FSL_IMX6_GPIO3_ADDR,
                 FSL_IMX6_GPIO3_LOW_IRQ,
                 FSL_IMX6_GPIO3_HIGH_IRQ
             },
             {
                 FSL_IMX6_GPIO4_ADDR,
                 FSL_IMX6_GPIO4_LOW_IRQ,
                 FSL_IMX6_GPIO4_HIGH_IRQ
             },
             {
                 FSL_IMX6_GPIO5_ADDR,
                 FSL_IMX6_GPIO5_LOW_IRQ,
                 FSL_IMX6_GPIO5_HIGH_IRQ
             },
             {
                 FSL_IMX6_GPIO6_ADDR,
                 FSL_IMX6_GPIO6_LOW_IRQ,
                 FSL_IMX6_GPIO6_HIGH_IRQ
             },
             {
                 FSL_IMX6_GPIO7_ADDR,
                 FSL_IMX6_GPIO7_LOW_IRQ,
                 FSL_IMX6_GPIO7_HIGH_IRQ
             },
         };
 
         object_property_set_bool(OBJECT(&s->gpio[i]), true, "has-edge-sel",
                                  &error_abort);
         object_property_set_bool(OBJECT(&s->gpio[i]), true, "has-upper-pin-irq",
                                  &error_abort);
         object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", &err);
         if (err) {
             error_propagate(errp, err);
             return;
         }
 
         sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
                            qdev_get_gpio_in(DEVICE(&s->a9mpcore),
                                             gpio_table[i].irq_low));
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1,
                            qdev_get_gpio_in(DEVICE(&s->a9mpcore),
                                             gpio_table[i].irq_high));
     }
 
     /* Initialize all SDHC */
     for (i = 0; i < FSL_IMX6_NUM_ESDHCS; i++) {
         static const struct {
             hwaddr addr;
             unsigned int irq;
         } esdhc_table[FSL_IMX6_NUM_ESDHCS] = {
             { FSL_IMX6_uSDHC1_ADDR, FSL_IMX6_uSDHC1_IRQ },
             { FSL_IMX6_uSDHC2_ADDR, FSL_IMX6_uSDHC2_IRQ },
             { FSL_IMX6_uSDHC3_ADDR, FSL_IMX6_uSDHC3_IRQ },
             { FSL_IMX6_uSDHC4_ADDR, FSL_IMX6_uSDHC4_IRQ },
         };
 
         /* UHS-I SDIO3.0 SDR104 1.8V ADMA */
         object_property_set_uint(OBJECT(&s->esdhc[i]), 3, "sd-spec-version",
                                  &err);
+        if (err) {
+            error_propagate(errp, err);
+            return;
+        }
         object_property_set_uint(OBJECT(&s->esdhc[i]), IMX6_ESDHC_CAPABILITIES,
                                  "capareg", &err);
+        if (err) {
+            error_propagate(errp, err);
+            return;
+        }
         object_property_set_bool(OBJECT(&s->esdhc[i]), true, "realized", &err);
         if (err) {
             error_propagate(errp, err);
             return;
         }
         sysbus_mmio_map(SYS_BUS_DEVICE(&s->esdhc[i]), 0, esdhc_table[i].addr);
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->esdhc[i]), 0,
                            qdev_get_gpio_in(DEVICE(&s->a9mpcore),
                                             esdhc_table[i].irq));
     }
 
     /* USB */
     for (i = 0; i < FSL_IMX6_NUM_USB_PHYS; i++) {
         object_property_set_bool(OBJECT(&s->usbphy[i]), true, "realized",
                                  &error_abort);
         sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0,
                         FSL_IMX6_USBPHY1_ADDR + i * 0x1000);
     }
     for (i = 0; i < FSL_IMX6_NUM_USBS; i++) {
         static const int FSL_IMX6_USBn_IRQ[] = {
             FSL_IMX6_USB_OTG_IRQ,
             FSL_IMX6_USB_HOST1_IRQ,
             FSL_IMX6_USB_HOST2_IRQ,
             FSL_IMX6_USB_HOST3_IRQ,
         };
 
         object_property_set_bool(OBJECT(&s->usb[i]), true, "realized",
                                  &error_abort);
         sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
                         FSL_IMX6_USBOH3_USB_ADDR + i * 0x200);
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
                            qdev_get_gpio_in(DEVICE(&s->a9mpcore),
                                             FSL_IMX6_USBn_IRQ[i]));
     }
 
     /* Initialize all ECSPI */
     for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) {
         static const struct {
             hwaddr addr;
             unsigned int irq;
         } spi_table[FSL_IMX6_NUM_ECSPIS] = {
             { FSL_IMX6_eCSPI1_ADDR, FSL_IMX6_ECSPI1_IRQ },
             { FSL_IMX6_eCSPI2_ADDR, FSL_IMX6_ECSPI2_IRQ },
             { FSL_IMX6_eCSPI3_ADDR, FSL_IMX6_ECSPI3_IRQ },
             { FSL_IMX6_eCSPI4_ADDR, FSL_IMX6_ECSPI4_IRQ },
             { FSL_IMX6_eCSPI5_ADDR, FSL_IMX6_ECSPI5_IRQ },
         };
 
         /* Initialize the SPI */
         object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
         if (err) {
             error_propagate(errp, err);
             return;
         }
 
         sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_table[i].addr);
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
                            qdev_get_gpio_in(DEVICE(&s->a9mpcore),
                                             spi_table[i].irq));
     }
 
     qdev_set_nic_properties(DEVICE(&s->eth), &nd_table[0]);
     object_property_set_bool(OBJECT(&s->eth), true, "realized", &err);
     if (err) {
         error_propagate(errp, err);
         return;
     }
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth), 0, FSL_IMX6_ENET_ADDR);
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth), 0,
                        qdev_get_gpio_in(DEVICE(&s->a9mpcore),
                                         FSL_IMX6_ENET_MAC_IRQ));
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth), 1,
                        qdev_get_gpio_in(DEVICE(&s->a9mpcore),
                                         FSL_IMX6_ENET_MAC_1588_IRQ));
 
     /*
      * Watchdog
      */
     for (i = 0; i < FSL_IMX6_NUM_WDTS; i++) {
         static const hwaddr FSL_IMX6_WDOGn_ADDR[FSL_IMX6_NUM_WDTS] = {
             FSL_IMX6_WDOG1_ADDR,
             FSL_IMX6_WDOG2_ADDR,
         };
 
         object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized",
                                  &error_abort);
 
         sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX6_WDOGn_ADDR[i]);
     }
 
     /* ROM memory */
     memory_region_init_rom(&s->rom, OBJECT(dev), "imx6.rom",
                            FSL_IMX6_ROM_SIZE, &err);
     if (err) {
         error_propagate(errp, err);
         return;
     }
     memory_region_add_subregion(get_system_memory(), FSL_IMX6_ROM_ADDR,
                                 &s->rom);
 
     /* CAAM memory */
     memory_region_init_rom(&s->caam, OBJECT(dev), "imx6.caam",
                            FSL_IMX6_CAAM_MEM_SIZE, &err);
     if (err) {
         error_propagate(errp, err);
         return;
     }
     memory_region_add_subregion(get_system_memory(), FSL_IMX6_CAAM_MEM_ADDR,
                                 &s->caam);
 
     /* OCRAM memory */
     memory_region_init_ram(&s->ocram, NULL, "imx6.ocram", FSL_IMX6_OCRAM_SIZE,
                            &err);
     if (err) {
         error_propagate(errp, err);
         return;
     }
     memory_region_add_subregion(get_system_memory(), FSL_IMX6_OCRAM_ADDR,
                                 &s->ocram);
 
     /* internal OCRAM (256 KB) is aliased over 1 MB */
     memory_region_init_alias(&s->ocram_alias, OBJECT(dev), "imx6.ocram_alias",
                              &s->ocram, 0, FSL_IMX6_OCRAM_ALIAS_SIZE);
     memory_region_add_subregion(get_system_memory(), FSL_IMX6_OCRAM_ALIAS_ADDR,
                                 &s->ocram_alias);
 }
-- 
2.21.1