[Intel-gfx] [PATCH 1/9] Revert "drm/i915/tgl: Include ro parts of l3 to invalidate"

[Intel-gfx] [PATCH 1/9] Revert "drm/i915/tgl: Include ro parts of l3 to invalidate"

[Mika Kuoppala]

This reverts commit 62037ffff229b7d94f1db5ef8d2e2ec819832ef3.

L3 ro cache invalidation is part of the dword0 of pipe
control. Also it is not relevant to this gen.

Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 -
 drivers/gpu/drm/i915/gt/intel_lrc.c          | 1 -
 2 files changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index ee10122a511e..b3cf09657fb2 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -236,7 +236,6 @@
 #define   PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH	(1<<12) /* gen6+ */
 #define   PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE	(1<<11) /* MBZ on ILK */
 #define   PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE		(1<<10) /* GM45+ only */
-#define   PIPE_CONTROL_L3_RO_CACHE_INVALIDATE		REG_BIT(10) /* gen12 */
 #define   PIPE_CONTROL_INDIRECT_STATE_DISABLE		(1<<9)
 #define   PIPE_CONTROL_HDC_PIPELINE_FLUSH		REG_BIT(9)  /* gen12 */
 #define   PIPE_CONTROL_NOTIFY				(1<<8)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 4311b12542fb..8f82b960f2a1 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -4585,7 +4585,6 @@ static int gen12_emit_flush_render(struct i915_request *request,
 		flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 		flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 		flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
-		flags |= PIPE_CONTROL_L3_RO_CACHE_INVALIDATE;
 
 		flags |= PIPE_CONTROL_STORE_DATA_INDEX;
 		flags |= PIPE_CONTROL_QW_WRITE;
-- 
2.17.1

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[Intel-gfx] [PATCH 2/9] drm/i915/gen12: Fix HDC pipeline flush

[Mika Kuoppala]

HDC pipeline flush is bit on the first dword of
the PIPE_CONTROL, not the second. Make it so.

Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_engine.h       | 23 +++++++++++----
 drivers/gpu/drm/i915/gt/intel_gpu_commands.h |  2 +-
 drivers/gpu/drm/i915/gt/intel_lrc.c          | 30 ++++++++++----------
 3 files changed, 33 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
index d10e52ff059f..f449171ae808 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -241,19 +241,24 @@ void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine);
 void intel_engine_print_breadcrumbs(struct intel_engine_cs *engine,
 				    struct drm_printer *p);
 
-static inline u32 *gen8_emit_pipe_control(u32 *batch, u32 flags, u32 offset)
+static inline u32 *gen12_emit_pipe_control(u32 *batch, u32 flags0, u32 flags1, u32 offset)
 {
 	memset(batch, 0, 6 * sizeof(u32));
 
-	batch[0] = GFX_OP_PIPE_CONTROL(6);
-	batch[1] = flags;
+	batch[0] = GFX_OP_PIPE_CONTROL(6) | flags0;
+	batch[1] = flags1;
 	batch[2] = offset;
 
 	return batch + 6;
 }
 
+static inline u32 *gen8_emit_pipe_control(u32 *batch, u32 flags, u32 offset)
+{
+	return gen12_emit_pipe_control(batch, 0, flags, offset);
+}
+
 static inline u32 *
-gen8_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
+gen12_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags0, u32 flags1)
 {
 	/* We're using qword write, offset should be aligned to 8 bytes. */
 	GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8));
@@ -262,8 +267,8 @@ gen8_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
 	 * need a prior CS_STALL, which is emitted by the flush
 	 * following the batch.
 	 */
-	*cs++ = GFX_OP_PIPE_CONTROL(6);
-	*cs++ = flags | PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_GLOBAL_GTT_IVB;
+	*cs++ = GFX_OP_PIPE_CONTROL(6) | flags0;
+	*cs++ = flags1 | PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_GLOBAL_GTT_IVB;
 	*cs++ = gtt_offset;
 	*cs++ = 0;
 	*cs++ = value;
@@ -273,6 +278,12 @@ gen8_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
 	return cs;
 }
 
+static inline u32 *
+gen8_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
+{
+	return gen12_emit_ggtt_write_rcs(cs, value, gtt_offset, 0, flags);
+}
+
 static inline u32 *
 gen8_emit_ggtt_write(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
 {
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index b3cf09657fb2..534e435f20bc 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -237,7 +237,7 @@
 #define   PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE	(1<<11) /* MBZ on ILK */
 #define   PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE		(1<<10) /* GM45+ only */
 #define   PIPE_CONTROL_INDIRECT_STATE_DISABLE		(1<<9)
-#define   PIPE_CONTROL_HDC_PIPELINE_FLUSH		REG_BIT(9)  /* gen12 */
+#define   PIPE_CONTROL0_HDC_PIPELINE_FLUSH		REG_BIT(9)  /* gen12 */
 #define   PIPE_CONTROL_NOTIFY				(1<<8)
 #define   PIPE_CONTROL_FLUSH_ENABLE			(1<<7) /* gen7+ */
 #define   PIPE_CONTROL_DC_FLUSH_ENABLE			(1<<5)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 8f82b960f2a1..3c5e55ad4f9f 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -4559,7 +4559,6 @@ static int gen12_emit_flush_render(struct i915_request *request,
 		flags |= PIPE_CONTROL_DEPTH_STALL;
 		flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
 		flags |= PIPE_CONTROL_FLUSH_ENABLE;
-		flags |= PIPE_CONTROL_HDC_PIPELINE_FLUSH;
 
 		flags |= PIPE_CONTROL_STORE_DATA_INDEX;
 		flags |= PIPE_CONTROL_QW_WRITE;
@@ -4570,7 +4569,8 @@ static int gen12_emit_flush_render(struct i915_request *request,
 		if (IS_ERR(cs))
 			return PTR_ERR(cs);
 
-		cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR);
+		cs = gen12_emit_pipe_control(cs, PIPE_CONTROL0_HDC_PIPELINE_FLUSH,
+					     flags, LRC_PPHWSP_SCRATCH_ADDR);
 		intel_ring_advance(request, cs);
 	}
 
@@ -4602,7 +4602,7 @@ static int gen12_emit_flush_render(struct i915_request *request,
 		 */
 		*cs++ = preparser_disable(true);
 
-		cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR);
+		cs = gen12_emit_pipe_control(cs, 0, flags, LRC_PPHWSP_SCRATCH_ADDR);
 
 		*cs++ = preparser_disable(false);
 		intel_ring_advance(request, cs);
@@ -4761,18 +4761,18 @@ static u32 *gen12_emit_fini_breadcrumb(struct i915_request *request, u32 *cs)
 static u32 *
 gen12_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs)
 {
-	cs = gen8_emit_ggtt_write_rcs(cs,
-				      request->fence.seqno,
-				      i915_request_active_timeline(request)->hwsp_offset,
-				      PIPE_CONTROL_CS_STALL |
-				      PIPE_CONTROL_TILE_CACHE_FLUSH |
-				      PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
-				      PIPE_CONTROL_DEPTH_CACHE_FLUSH |
-				      /* Wa_1409600907:tgl */
-				      PIPE_CONTROL_DEPTH_STALL |
-				      PIPE_CONTROL_DC_FLUSH_ENABLE |
-				      PIPE_CONTROL_FLUSH_ENABLE |
-				      PIPE_CONTROL_HDC_PIPELINE_FLUSH);
+	cs = gen12_emit_ggtt_write_rcs(cs,
+				       request->fence.seqno,
+				       i915_request_active_timeline(request)->hwsp_offset,
+				       PIPE_CONTROL0_HDC_PIPELINE_FLUSH,
+				       PIPE_CONTROL_CS_STALL |
+				       PIPE_CONTROL_TILE_CACHE_FLUSH |
+				       PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
+				       PIPE_CONTROL_DEPTH_CACHE_FLUSH |
+				       /* Wa_1409600907:tgl */
+				       PIPE_CONTROL_DEPTH_STALL |
+				       PIPE_CONTROL_DC_FLUSH_ENABLE |
+				       PIPE_CONTROL_FLUSH_ENABLE);
 
 	return gen12_emit_fini_breadcrumb_footer(request, cs);
 }
-- 
2.17.1

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Re: [Intel-gfx] [PATCH 2/9] drm/i915/gen12: Fix HDC pipeline flush

[Chris Wilson]

Quoting Mika Kuoppala (2020-04-30 16:47:28)
> HDC pipeline flush is bit on the first dword of
> the PIPE_CONTROL, not the second. Make it so.
> 
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_engine.h       | 23 +++++++++++----
>  drivers/gpu/drm/i915/gt/intel_gpu_commands.h |  2 +-
>  drivers/gpu/drm/i915/gt/intel_lrc.c          | 30 ++++++++++----------
>  3 files changed, 33 insertions(+), 22 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
> index d10e52ff059f..f449171ae808 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine.h
> @@ -241,19 +241,24 @@ void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine);
>  void intel_engine_print_breadcrumbs(struct intel_engine_cs *engine,
>                                     struct drm_printer *p);
>  
> -static inline u32 *gen8_emit_pipe_control(u32 *batch, u32 flags, u32 offset)
> +static inline u32 *gen12_emit_pipe_control(u32 *batch, u32 flags0, u32 flags1, u32 offset)
>  {
>         memset(batch, 0, 6 * sizeof(u32));
>  
> -       batch[0] = GFX_OP_PIPE_CONTROL(6);
> -       batch[1] = flags;
> +       batch[0] = GFX_OP_PIPE_CONTROL(6) | flags0;
> +       batch[1] = flags1;
>         batch[2] = offset;
>  
>         return batch + 6;
>  }
>  
> +static inline u32 *gen8_emit_pipe_control(u32 *batch, u32 flags, u32 offset)
> +{
> +       return gen12_emit_pipe_control(batch, 0, flags, offset);

We always call into older; the gen prefix indicates the earliest the
function is usable.
-Chris
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Re: [Intel-gfx] [PATCH 2/9] drm/i915/gen12: Fix HDC pipeline flush

[Chris Wilson]

Quoting Mika Kuoppala (2020-04-30 16:47:28)
> diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> index b3cf09657fb2..534e435f20bc 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> @@ -237,7 +237,7 @@
>  #define   PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE    (1<<11) /* MBZ on ILK */
>  #define   PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE                (1<<10) /* GM45+ only */
>  #define   PIPE_CONTROL_INDIRECT_STATE_DISABLE          (1<<9)
> -#define   PIPE_CONTROL_HDC_PIPELINE_FLUSH              REG_BIT(9)  /* gen12 */
> +#define   PIPE_CONTROL0_HDC_PIPELINE_FLUSH             REG_BIT(9)  /* gen12 */
>  #define   PIPE_CONTROL_NOTIFY                          (1<<8)
>  #define   PIPE_CONTROL_FLUSH_ENABLE                    (1<<7) /* gen7+ */
>  #define   PIPE_CONTROL_DC_FLUSH_ENABLE                 (1<<5)

Confirmed. With the naming inversion resolved,
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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Re: [Intel-gfx] [PATCH 2/9] drm/i915/gen12: Fix HDC pipeline flush

[D Scott Phillips]

Mika Kuoppala <mika.kuoppala@linux.intel.com> writes:

> HDC pipeline flush is bit on the first dword of
> the PIPE_CONTROL, not the second. Make it so.
>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

Fixes: 4aa0b5d457f5 ("drm/i915/tgl: Add HDC Pipeline Flush")
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[Intel-gfx] [PATCH 3/9] drm/i915/gen12: Add L3 fabric flush

[Mika Kuoppala]

Do a l3 fabric flush when emitting flush.

Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 +
 drivers/gpu/drm/i915/gt/intel_lrc.c          | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index 534e435f20bc..98b39e65aed9 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -219,6 +219,7 @@
 #define   DISPLAY_PLANE_A           (0<<20)
 #define   DISPLAY_PLANE_B           (1<<20)
 #define GFX_OP_PIPE_CONTROL(len)	((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2))
+#define   PIPE_CONTROL_L3_FABRIC_FLUSH		        (1<<30) /* gen12+ */
 #define   PIPE_CONTROL_COMMAND_CACHE_INVALIDATE		(1<<29) /* gen11+ */
 #define   PIPE_CONTROL_TILE_CACHE_FLUSH			(1<<28) /* gen11+ */
 #define   PIPE_CONTROL_FLUSH_L3				(1<<27)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 3c5e55ad4f9f..b3ddb928d231 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -4552,6 +4552,7 @@ static int gen12_emit_flush_render(struct i915_request *request,
 		u32 flags = 0;
 		u32 *cs;
 
+		flags |= PIPE_CONTROL_L3_FABRIC_FLUSH;
 		flags |= PIPE_CONTROL_TILE_CACHE_FLUSH;
 		flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 		flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
@@ -4766,6 +4767,7 @@ gen12_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs)
 				       i915_request_active_timeline(request)->hwsp_offset,
 				       PIPE_CONTROL0_HDC_PIPELINE_FLUSH,
 				       PIPE_CONTROL_CS_STALL |
+				       PIPE_CONTROL_L3_FABRIC_FLUSH |
 				       PIPE_CONTROL_TILE_CACHE_FLUSH |
 				       PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
 				       PIPE_CONTROL_DEPTH_CACHE_FLUSH |
-- 
2.17.1

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Re: [Intel-gfx] [PATCH 3/9] drm/i915/gen12: Add L3 fabric flush

[Chris Wilson]

Quoting Mika Kuoppala (2020-04-30 16:47:29)
> Do a l3 fabric flush when emitting flush.

It's quoted as being a debug bit, and that the L3 flush is a part of the
post-sync op.

Not sure if we want this without being told we must, or reason to
believe we do.

> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 +
>  drivers/gpu/drm/i915/gt/intel_lrc.c          | 2 ++
>  2 files changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> index 534e435f20bc..98b39e65aed9 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> @@ -219,6 +219,7 @@
>  #define   DISPLAY_PLANE_A           (0<<20)
>  #define   DISPLAY_PLANE_B           (1<<20)
>  #define GFX_OP_PIPE_CONTROL(len)       ((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2))
> +#define   PIPE_CONTROL_L3_FABRIC_FLUSH                 (1<<30) /* gen12+ */

Nevertheless bits check out,

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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[Intel-gfx] [PATCH 4/9] drm/i915/gen12: Flush L3

[Mika Kuoppala]

Flush TDL and L3.

Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_lrc.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index b3ddb928d231..0bbce218157f 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -4554,6 +4554,7 @@ static int gen12_emit_flush_render(struct i915_request *request,
 
 		flags |= PIPE_CONTROL_L3_FABRIC_FLUSH;
 		flags |= PIPE_CONTROL_TILE_CACHE_FLUSH;
+		flags |= PIPE_CONTROL_FLUSH_L3;
 		flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 		flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 		/* Wa_1409600907:tgl */
@@ -4769,6 +4770,7 @@ gen12_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs)
 				       PIPE_CONTROL_CS_STALL |
 				       PIPE_CONTROL_L3_FABRIC_FLUSH |
 				       PIPE_CONTROL_TILE_CACHE_FLUSH |
+				       PIPE_CONTROL_FLUSH_L3 |
 				       PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
 				       PIPE_CONTROL_DEPTH_CACHE_FLUSH |
 				       /* Wa_1409600907:tgl */
-- 
2.17.1

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Re: [Intel-gfx] [PATCH 4/9] drm/i915/gen12: Flush L3

[Chris Wilson]

Quoting Mika Kuoppala (2020-04-30 16:47:30)
> Flush TDL and L3.
> 
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

That's very misnamed bit!

There's a comment that this must be paired with the corresponding pc in
the same HW dispatch.
-Chris
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Re: [Intel-gfx] [PATCH 4/9] drm/i915/gen12: Flush L3

[Mika Kuoppala]

Chris Wilson <chris@chris-wilson.co.uk> writes:

> Quoting Mika Kuoppala (2020-04-30 16:47:30)
>> Flush TDL and L3.
>> 
>> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>
> That's very misnamed bit!
>
> There's a comment that this must be paired with the corresponding pc in
> the same HW dispatch.

Not for gen12.
-Mika
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[Intel-gfx] [PATCH 5/9] drm/i915/gen12: Flush AMFS

[Mika Kuoppala]

To ensure that we have global observation point wrt to
all data, flush amfs.

Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 +
 drivers/gpu/drm/i915/gt/intel_lrc.c          | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index 98b39e65aed9..69979cc86caa 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -223,6 +223,7 @@
 #define   PIPE_CONTROL_COMMAND_CACHE_INVALIDATE		(1<<29) /* gen11+ */
 #define   PIPE_CONTROL_TILE_CACHE_FLUSH			(1<<28) /* gen11+ */
 #define   PIPE_CONTROL_FLUSH_L3				(1<<27)
+#define   PIPE_CONTROL_FLUSH_AMFS			(1<<25) /* gen12+ */
 #define   PIPE_CONTROL_GLOBAL_GTT_IVB			(1<<24) /* gen7+ */
 #define   PIPE_CONTROL_MMIO_WRITE			(1<<23)
 #define   PIPE_CONTROL_STORE_DATA_INDEX			(1<<21)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 0bbce218157f..b47230583494 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -4555,6 +4555,7 @@ static int gen12_emit_flush_render(struct i915_request *request,
 		flags |= PIPE_CONTROL_L3_FABRIC_FLUSH;
 		flags |= PIPE_CONTROL_TILE_CACHE_FLUSH;
 		flags |= PIPE_CONTROL_FLUSH_L3;
+		flags |= PIPE_CONTROL_FLUSH_AMFS;
 		flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 		flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 		/* Wa_1409600907:tgl */
@@ -4771,6 +4772,7 @@ gen12_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs)
 				       PIPE_CONTROL_L3_FABRIC_FLUSH |
 				       PIPE_CONTROL_TILE_CACHE_FLUSH |
 				       PIPE_CONTROL_FLUSH_L3 |
+				       PIPE_CONTROL_FLUSH_AMFS |
 				       PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
 				       PIPE_CONTROL_DEPTH_CACHE_FLUSH |
 				       /* Wa_1409600907:tgl */
-- 
2.17.1

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Re: [Intel-gfx] [PATCH 5/9] drm/i915/gen12: Flush AMFS

[Chris Wilson]

Quoting Mika Kuoppala (2020-04-30 16:47:31)
> To ensure that we have global observation point wrt to
> all data, flush amfs.
> 
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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[Intel-gfx] [PATCH 6/9] drm/i915/gen12: Invalidate indirect state pointers

[Mika Kuoppala]

Aim for completeness for invalidating everything
and mark state pointers stale.

Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_lrc.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index b47230583494..7807f53eae18 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -4585,6 +4585,7 @@ static int gen12_emit_flush_render(struct i915_request *request,
 		flags |= PIPE_CONTROL_TLB_INVALIDATE;
 		flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 		flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
+		flags |= PIPE_CONTROL_INDIRECT_STATE_DISABLE;
 		flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 		flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 		flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
-- 
2.17.1

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Re: [Intel-gfx] [PATCH 6/9] drm/i915/gen12: Invalidate indirect state pointers

[Chris Wilson]

Quoting Mika Kuoppala (2020-04-30 16:47:32)
> Aim for completeness for invalidating everything
> and mark state pointers stale.
> 
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

There's a confusing mention that the indirect state pointers are not
saved in the context... But we still need to invalidate if we rebind new
buffers at the old pointer locations.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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Re: [Intel-gfx] [PATCH 6/9] drm/i915/gen12: Invalidate indirect state pointers

[D Scott Phillips]

Mika Kuoppala <mika.kuoppala@linux.intel.com> writes:

> Aim for completeness for invalidating everything
> and mark state pointers stale.
>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

nak, this breaks iris. indirect state disable removes push constant
state from the render context, not just invalidating it
emphemerally. iris is depending on that state to persist.
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[Intel-gfx] [PATCH 7/9] drm/i915/gen12: Wait on previous flush on invalidate

[Mika Kuoppala]

Flush enable bit is a sync point which makes this
pipecontrol to wait that everything on a previous
pipe control are flushed. Enable it to make
sure that our invalidates doesn't overlap.

Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_lrc.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 7807f53eae18..789efece1fc0 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -4590,6 +4590,8 @@ static int gen12_emit_flush_render(struct i915_request *request,
 		flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 		flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 
+		flags |= PIPE_CONTROL_FLUSH_ENABLE;
+
 		flags |= PIPE_CONTROL_STORE_DATA_INDEX;
 		flags |= PIPE_CONTROL_QW_WRITE;
 
-- 
2.17.1

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Re: [Intel-gfx] [PATCH 7/9] drm/i915/gen12: Wait on previous flush on invalidate

[Chris Wilson]

Quoting Mika Kuoppala (2020-04-30 16:47:33)
> Flush enable bit is a sync point which makes this
> pipecontrol to wait that everything on a previous
> pipe control are flushed. Enable it to make
> sure that our invalidates doesn't overlap.

Not sold. We terminated the previous context with a serialising flush;
the pipe should be idle... But what about preemption, hmm? But then you
have preemption between batches past the invalidate point, and so it
must all be safely restored from context.

So the primarily concern here is with state being overwritten by GTT
updates.

Still not sold.
-Chris
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[Intel-gfx] [PATCH 8/9] drm/i915/gen12: Invalidate media state

[Mika Kuoppala]

Treat media state as any other state and invalidate it.

Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_lrc.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 789efece1fc0..859c901c8935 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -4583,6 +4583,7 @@ static int gen12_emit_flush_render(struct i915_request *request,
 
 		flags |= PIPE_CONTROL_COMMAND_CACHE_INVALIDATE;
 		flags |= PIPE_CONTROL_TLB_INVALIDATE;
+		flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
 		flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 		flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 		flags |= PIPE_CONTROL_INDIRECT_STATE_DISABLE;
-- 
2.17.1

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Re: [Intel-gfx] [PATCH 8/9] drm/i915/gen12: Invalidate media state

[Chris Wilson]

Quoting Mika Kuoppala (2020-04-30 16:47:34)
> Treat media state as any other state and invalidate it.
> 
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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[Intel-gfx] [PATCH 9/9] drm/i915/gen12: Flush LLC

[Mika Kuoppala]

Request boundary is a global observation point for
all operations. Thus flush the LLC too.

Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 +
 drivers/gpu/drm/i915/gt/intel_lrc.c          | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index 69979cc86caa..a7f4f0934508 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -223,6 +223,7 @@
 #define   PIPE_CONTROL_COMMAND_CACHE_INVALIDATE		(1<<29) /* gen11+ */
 #define   PIPE_CONTROL_TILE_CACHE_FLUSH			(1<<28) /* gen11+ */
 #define   PIPE_CONTROL_FLUSH_L3				(1<<27)
+#define   PIPE_CONTROL_FLUSH_LLC			(1<<26) /* gen12+ */
 #define   PIPE_CONTROL_FLUSH_AMFS			(1<<25) /* gen12+ */
 #define   PIPE_CONTROL_GLOBAL_GTT_IVB			(1<<24) /* gen7+ */
 #define   PIPE_CONTROL_MMIO_WRITE			(1<<23)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 859c901c8935..2a4ef2ea042f 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -4555,6 +4555,7 @@ static int gen12_emit_flush_render(struct i915_request *request,
 		flags |= PIPE_CONTROL_L3_FABRIC_FLUSH;
 		flags |= PIPE_CONTROL_TILE_CACHE_FLUSH;
 		flags |= PIPE_CONTROL_FLUSH_L3;
+		flags |= PIPE_CONTROL_FLUSH_LLC;
 		flags |= PIPE_CONTROL_FLUSH_AMFS;
 		flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 		flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
@@ -4776,6 +4777,7 @@ gen12_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs)
 				       PIPE_CONTROL_L3_FABRIC_FLUSH |
 				       PIPE_CONTROL_TILE_CACHE_FLUSH |
 				       PIPE_CONTROL_FLUSH_L3 |
+				       PIPE_CONTROL_FLUSH_LLC |
 				       PIPE_CONTROL_FLUSH_AMFS |
 				       PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
 				       PIPE_CONTROL_DEPTH_CACHE_FLUSH |
-- 
2.17.1

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Re: [Intel-gfx] [PATCH 9/9] drm/i915/gen12: Flush LLC

[Chris Wilson]

Quoting Mika Kuoppala (2020-04-30 16:47:35)
> Request boundary is a global observation point for
> all operations. Thus flush the LLC too.
> 
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

This one always concerned me for being unbounded in cost: flush all the
LLC lines that might be framebuffer.

We don't mix scanout and LLC, so we've never felt concerned to enable
this flush. [It's definitely not gen12+!]

I would not enable this bit without good cause and verification it
doesn't cost anything for normal render paths.

Still we need to record this bit. For example, I might
suggest it is coupled into the flush-display path directly.
-Chris
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/9] Revert "drm/i915/tgl: Include ro parts of l3 to invalidate"

[Patchwork]

== Series Details ==

Series: series starting with [1/9] Revert "drm/i915/tgl: Include ro parts of l3 to invalidate"
URL   : https://patchwork.freedesktop.org/series/76777/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
53177bdb8662 Revert "drm/i915/tgl: Include ro parts of l3 to invalidate"
7e235ad6db72 drm/i915/gen12: Fix HDC pipeline flush
868476e157a0 drm/i915/gen12: Add L3 fabric flush
-:18: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#18: FILE: drivers/gpu/drm/i915/gt/intel_gpu_commands.h:222:
+#define   PIPE_CONTROL_L3_FABRIC_FLUSH		        (1<<30) /* gen12+ */
                                       		          ^

total: 0 errors, 0 warnings, 1 checks, 21 lines checked
8411dc590177 drm/i915/gen12: Flush L3
abb852252bfa drm/i915/gen12: Flush AMFS
-:19: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#19: FILE: drivers/gpu/drm/i915/gt/intel_gpu_commands.h:226:
+#define   PIPE_CONTROL_FLUSH_AMFS			(1<<25) /* gen12+ */
                                  			  ^

total: 0 errors, 0 warnings, 1 checks, 21 lines checked
cdb89beff0e2 drm/i915/gen12: Invalidate indirect state pointers
4289817480ba drm/i915/gen12: Wait on previous flush on invalidate
dda90d2bdc6d drm/i915/gen12: Invalidate media state
987ed1f2f5ee drm/i915/gen12: Flush LLC
-:19: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#19: FILE: drivers/gpu/drm/i915/gt/intel_gpu_commands.h:226:
+#define   PIPE_CONTROL_FLUSH_LLC			(1<<26) /* gen12+ */
                                 			  ^

total: 0 errors, 0 warnings, 1 checks, 21 lines checked

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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/9] Revert "drm/i915/tgl: Include ro parts of l3 to invalidate"

[Patchwork]

== Series Details ==

Series: series starting with [1/9] Revert "drm/i915/tgl: Include ro parts of l3 to invalidate"
URL   : https://patchwork.freedesktop.org/series/76777/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_8401 -> Patchwork_17529
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17529/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_17529:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@debugfs_test@read_all_entries:
    - fi-kbl-7500u:       NOTRUN -> [{ABORT}][1]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17529/fi-kbl-7500u/igt@debugfs_test@read_all_entries.html

  
Known issues
------------

  Here are the changes found in Patchwork_17529 that come from known issues:

### IGT changes ###

#### Possible fixes ####

  * igt@i915_selftest@live@gem_contexts:
    - fi-bwr-2160:        [INCOMPLETE][2] ([i915#489]) -> [PASS][3]
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8401/fi-bwr-2160/igt@i915_selftest@live@gem_contexts.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17529/fi-bwr-2160/igt@i915_selftest@live@gem_contexts.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#489]: https://gitlab.freedesktop.org/drm/intel/issues/489


Participating hosts (50 -> 44)
------------------------------

  Missing    (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_8401 -> Patchwork_17529

  CI-20190529: 20190529
  CI_DRM_8401: 41fac0e3809be301af095c66e717eb9843b80212 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5617: 807b26292a3f21057ef7865a4028d22c512590df @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_17529: 987ed1f2f5ee6841ef96e02808b35fd17dc72028 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

987ed1f2f5ee drm/i915/gen12: Flush LLC
dda90d2bdc6d drm/i915/gen12: Invalidate media state
4289817480ba drm/i915/gen12: Wait on previous flush on invalidate
cdb89beff0e2 drm/i915/gen12: Invalidate indirect state pointers
abb852252bfa drm/i915/gen12: Flush AMFS
8411dc590177 drm/i915/gen12: Flush L3
868476e157a0 drm/i915/gen12: Add L3 fabric flush
7e235ad6db72 drm/i915/gen12: Fix HDC pipeline flush
53177bdb8662 Revert "drm/i915/tgl: Include ro parts of l3 to invalidate"

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17529/index.html
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Re: [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/9] Revert "drm/i915/tgl: Include ro parts of l3 to invalidate"

[Chris Wilson]

Quoting Patchwork (2020-04-30 17:25:55)
> == Series Details ==
> 
> Series: series starting with [1/9] Revert "drm/i915/tgl: Include ro parts of l3 to invalidate"
> URL   : https://patchwork.freedesktop.org/series/76777/
> State : success
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_8401 -> Patchwork_17529
> ====================================================
> 
> Summary
> -------
> 
>   **SUCCESS**

Coherency/pipecontrol are the worst. How do we design tests to even
detect and probe for unknown missed flushes?

I wonder if there are some debug [context] registers that can tell us the
status of all caches? Set to nonzero for a dirty cache, and we're allowed
to set, but is then cleared by pipecontrol. Seems worth asking.
-Chris
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/9] Revert "drm/i915/tgl: Include ro parts of l3 to invalidate"

[Patchwork]

== Series Details ==

Series: series starting with [1/9] Revert "drm/i915/tgl: Include ro parts of l3 to invalidate"
URL   : https://patchwork.freedesktop.org/series/76777/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_8401_full -> Patchwork_17529_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_17529_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_eio@in-flight-suspend:
    - shard-kbl:          [PASS][1] -> [DMESG-WARN][2] ([i915#180]) +1 similar issue
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8401/shard-kbl6/igt@gem_eio@in-flight-suspend.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17529/shard-kbl6/igt@gem_eio@in-flight-suspend.html

  * igt@gem_exec_params@invalid-bsd-ring:
    - shard-iclb:         [PASS][3] -> [SKIP][4] ([fdo#109276])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8401/shard-iclb1/igt@gem_exec_params@invalid-bsd-ring.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17529/shard-iclb5/igt@gem_exec_params@invalid-bsd-ring.html

  * igt@gen9_exec_parse@allowed-single:
    - shard-skl:          [PASS][5] -> [DMESG-WARN][6] ([i915#716])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8401/shard-skl7/igt@gen9_exec_parse@allowed-single.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17529/shard-skl4/igt@gen9_exec_parse@allowed-single.html

  * igt@i915_suspend@fence-restore-untiled:
    - shard-apl:          [PASS][7] -> [DMESG-WARN][8] ([i915#180])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8401/shard-apl1/igt@i915_suspend@fence-restore-untiled.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17529/shard-apl1/igt@i915_suspend@fence-restore-untiled.html

  * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
    - shard-hsw:          [PASS][9] -> [FAIL][10] ([i915#96])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8401/shard-hsw2/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17529/shard-hsw8/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-skl:          [PASS][11] -> [INCOMPLETE][12] ([i915#69]) +1 similar issue
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8401/shard-skl5/igt@kms_fbcon_fbt@psr-suspend.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17529/shard-skl5/igt@kms_fbcon_fbt@psr-suspend.html

  * igt@kms_plane@plane-panning-top-left-pipe-a-planes:
    - shard-skl:          [PASS][13] -> [FAIL][14] ([i915#1036])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8401/shard-skl6/igt@kms_plane@plane-panning-top-left-pipe-a-planes.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17529/shard-skl3/igt@kms_plane@plane-panning-top-left-pipe-a-planes.html

  * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
    - shard-skl:          [PASS][15] -> [FAIL][16] ([fdo#108145] / [i915#265]) +1 similar issue
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8401/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17529/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html

  * igt@kms_plane_lowres@pipe-a-tiling-x:
    - shard-glk:          [PASS][17] -> [FAIL][18] ([i915#899])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8401/shard-glk1/igt@kms_plane_lowres@pipe-a-tiling-x.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17529/shard-glk4/igt@kms_plane_lowres@pipe-a-tiling-x.html

  * igt@kms_psr2_su@frontbuffer:
    - shard-iclb:         [PASS][19] -> [SKIP][20] ([fdo#109642] / [fdo#111068])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8401/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17529/shard-iclb6/igt@kms_psr2_su@frontbuffer.html

  * igt@kms_psr@psr2_basic:
    - shard-iclb:         [PASS][21] -> [SKIP][22] ([fdo#109441]) +2 similar issues
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8401/shard-iclb2/igt@kms_psr@psr2_basic.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17529/shard-iclb3/igt@kms_psr@psr2_basic.html

  * igt@kms_vblank@pipe-a-query-idle-hang:
    - shard-snb:          [PASS][23] -> [SKIP][24] ([fdo#109271]) +6 similar issues
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8401/shard-snb1/igt@kms_vblank@pipe-a-query-idle-hang.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17529/shard-snb4/igt@kms_vblank@pipe-a-query-idle-hang.html

  
#### Possible fixes ####

  * igt@gen9_exec_parse@allowed-all:
    - shard-apl:          [DMESG-WARN][25] ([i915#716]) -> [PASS][26]
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8401/shard-apl2/igt@gen9_exec_parse@allowed-all.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17529/shard-apl3/igt@gen9_exec_parse@allowed-all.html

  * igt@i915_pm_dc@dc6-psr:
    - shard-iclb:         [FAIL][27] ([i915#454]) -> [PASS][28]
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8401/shard-iclb4/igt@i915_pm_dc@dc6-psr.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17529/shard-iclb4/igt@i915_pm_dc@dc6-psr.html

  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
    - shard-kbl:          [DMESG-WARN][29] ([i915#180]) -> [PASS][30]
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8401/shard-kbl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17529/shard-kbl3/igt@kms_cursor_crc@pipe-c-cursor-suspend.html

  * {igt@kms_flip@flip-vs-expired-vblank@c-edp1}:
    - shard-skl:          [FAIL][31] ([i915#79]) -> [PASS][32]
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8401/shard-skl7/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17529/shard-skl1/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html

  * {igt@kms_flip@flip-vs-suspend-interruptible@c-dp1}:
    - shard-apl:          [DMESG-WARN][33] ([i915#180]) -> [PASS][34] +1 similar issue
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8401/shard-apl8/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17529/shard-apl4/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html

  * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
    - shard-skl:          [FAIL][35] ([fdo#108145] / [i915#265]) -> [PASS][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8401/shard-skl8/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17529/shard-skl1/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html

  * igt@kms_psr@psr2_cursor_render:
    - shard-iclb:         [SKIP][37] ([fdo#109441]) -> [PASS][38] +2 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8401/shard-iclb4/igt@kms_psr@psr2_cursor_render.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17529/shard-iclb2/igt@kms_psr@psr2_cursor_render.html

  * igt@perf@gen8-unprivileged-single-ctx-counters:
    - shard-glk:          [TIMEOUT][39] ([i915#1813]) -> [PASS][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8401/shard-glk6/igt@perf@gen8-unprivileged-single-ctx-counters.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17529/shard-glk4/igt@perf@gen8-unprivileged-single-ctx-counters.html

  
#### Warnings ####

  * igt@i915_pm_dc@dc6-psr:
    - shard-tglb:         [FAIL][41] ([i915#454]) -> [SKIP][42] ([i915#468])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8401/shard-tglb3/igt@i915_pm_dc@dc6-psr.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17529/shard-tglb2/igt@i915_pm_dc@dc6-psr.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [i915#1036]: https://gitlab.freedesktop.org/drm/intel/issues/1036
  [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#1813]: https://gitlab.freedesktop.org/drm/intel/issues/1813
  [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
  [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
  [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468
  [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
  [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
  [i915#899]: https://gitlab.freedesktop.org/drm/intel/issues/899
  [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
  [i915#96]: https://gitlab.freedesktop.org/drm/intel/issues/96


Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_8401 -> Patchwork_17529

  CI-20190529: 20190529
  CI_DRM_8401: 41fac0e3809be301af095c66e717eb9843b80212 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5617: 807b26292a3f21057ef7865a4028d22c512590df @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_17529: 987ed1f2f5ee6841ef96e02808b35fd17dc72028 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17529/index.html
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Re: [Intel-gfx] [PATCH 1/9] Revert "drm/i915/tgl: Include ro parts of l3 to invalidate"

[Chris Wilson]

Quoting Mika Kuoppala (2020-04-30 16:47:27)
> This reverts commit 62037ffff229b7d94f1db5ef8d2e2ec819832ef3.
> 
> L3 ro cache invalidation is part of the dword0 of pipe
> control.

True.

> Also it is not relevant to this gen.

?

> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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