* [Intel-gfx] [PATCH v27 0/6] SAGV support for Gen12+
@ 2020-05-05 10:22 Stanislav Lisovskiy
2020-05-05 10:22 ` [Intel-gfx] [PATCH v27 1/6] drm/i915: Introduce skl_plane_wm_level accessor Stanislav Lisovskiy
` (7 more replies)
0 siblings, 8 replies; 24+ messages in thread
From: Stanislav Lisovskiy @ 2020-05-05 10:22 UTC (permalink / raw)
To: intel-gfx
For Gen11+ platforms BSpec suggests disabling specific
QGV points separately, depending on bandwidth limitations
and current display configuration. Thus it required adding
a new PCode request for disabling QGV points and some
refactoring of already existing SAGV code.
Also had to refactor intel_can_enable_sagv function,
as current seems to be outdated and using skl specific
workarounds, also not following BSpec for Gen11+.
v25: Rebased patch series as part was merged already
v26: Had to resend the whole series as one more mid patch was added
v27: Patches 2,3,7 were pushed, have to resend the series to prevent
build failure.
Stanislav Lisovskiy (6):
drm/i915: Introduce skl_plane_wm_level accessor.
drm/i915: Separate icl and skl SAGV checking
drm/i915: Add TGL+ SAGV support
drm/i915: Added required new PCode commands
drm/i915: Restrict qgv points which don't have enough bandwidth.
drm/i915: Enable SAGV support for Gen12
drivers/gpu/drm/i915/display/intel_bw.c | 139 ++++++--
drivers/gpu/drm/i915/display/intel_bw.h | 9 +
drivers/gpu/drm/i915/display/intel_display.c | 8 +-
.../drm/i915/display/intel_display_types.h | 6 +
drivers/gpu/drm/i915/i915_reg.h | 4 +
drivers/gpu/drm/i915/intel_pm.c | 303 ++++++++++++++++--
drivers/gpu/drm/i915/intel_pm.h | 2 +
drivers/gpu/drm/i915/intel_sideband.c | 2 +
8 files changed, 407 insertions(+), 66 deletions(-)
--
2.24.1.485.gad05a3d8e5
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 24+ messages in thread
* [Intel-gfx] [PATCH v27 1/6] drm/i915: Introduce skl_plane_wm_level accessor.
2020-05-05 10:22 [Intel-gfx] [PATCH v27 0/6] SAGV support for Gen12+ Stanislav Lisovskiy
@ 2020-05-05 10:22 ` Stanislav Lisovskiy
2020-05-05 10:22 ` [Intel-gfx] [PATCH v27 2/6] drm/i915: Separate icl and skl SAGV checking Stanislav Lisovskiy
` (6 subsequent siblings)
7 siblings, 0 replies; 24+ messages in thread
From: Stanislav Lisovskiy @ 2020-05-05 10:22 UTC (permalink / raw)
To: intel-gfx
For future Gen12 SAGV implementation we need to
seemlessly alter wm levels calculated, depending
on whether we are allowed to enable SAGV or not.
So this accessor will give additional flexibility
to do that.
Currently this accessor is still simply working
as "pass-through" function. This will be changed
in next coming patches from this series.
v2: - plane_id -> plane->id(Ville Syrjälä)
- Moved wm_level var to have more local scope
(Ville Syrjälä)
- Renamed yuv to color_plane(Ville Syrjälä) in
skl_plane_wm_level
v3: - plane->id -> plane_id(this time for real, Ville Syrjälä)
- Changed colorplane id type from boolean to int as index
(Ville Syrjälä)
- Moved crtc_state param so that it is first now
(Ville Syrjälä)
- Moved wm_level declaration to tigher scope in
skl_write_plane_wm(Ville Syrjälä)
v4: - Started to use enum values for color plane
- Do sizeof for a type what we are memset'ing
- Zero out wm_uv as well(Ville Syrjälä)
v5: - Fixed rebase conflict caused by COLOR_PLANE_*
enum removal
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 85 ++++++++++++++++++++++++++-------
1 file changed, 67 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 416cb1a1e7cb..da567fac7c93 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4632,6 +4632,18 @@ icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
return total_data_rate;
}
+static const struct skl_wm_level *
+skl_plane_wm_level(const struct intel_crtc_state *crtc_state,
+ enum plane_id plane_id,
+ int level,
+ int color_plane)
+{
+ const struct skl_plane_wm *wm =
+ &crtc_state->wm.skl.optimal.planes[plane_id];
+
+ return color_plane == 0 ? &wm->wm[level] : &wm->uv_wm[level];
+}
+
static int
skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
{
@@ -4691,22 +4703,28 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
*/
for (level = ilk_wm_max_level(dev_priv); level >= 0; level--) {
blocks = 0;
+
for_each_plane_id_on_crtc(crtc, plane_id) {
- const struct skl_plane_wm *wm =
- &crtc_state->wm.skl.optimal.planes[plane_id];
+ const struct skl_wm_level *wm_level;
+ const struct skl_wm_level *wm_uv_level;
+
+ wm_level = skl_plane_wm_level(crtc_state, plane_id,
+ level, 0);
+ wm_uv_level = skl_plane_wm_level(crtc_state, plane_id,
+ level, 1);
if (plane_id == PLANE_CURSOR) {
- if (wm->wm[level].min_ddb_alloc > total[PLANE_CURSOR]) {
+ if (wm_level->min_ddb_alloc > total[PLANE_CURSOR]) {
drm_WARN_ON(&dev_priv->drm,
- wm->wm[level].min_ddb_alloc != U16_MAX);
+ wm_level->min_ddb_alloc != U16_MAX);
blocks = U32_MAX;
break;
}
continue;
}
- blocks += wm->wm[level].min_ddb_alloc;
- blocks += wm->uv_wm[level].min_ddb_alloc;
+ blocks += wm_level->min_ddb_alloc;
+ blocks += wm_uv_level->min_ddb_alloc;
}
if (blocks <= alloc_size) {
@@ -4729,11 +4747,16 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
* proportional to its relative data rate.
*/
for_each_plane_id_on_crtc(crtc, plane_id) {
- const struct skl_plane_wm *wm =
- &crtc_state->wm.skl.optimal.planes[plane_id];
+ const struct skl_wm_level *wm_level;
+ const struct skl_wm_level *wm_uv_level;
u64 rate;
u16 extra;
+ wm_level = skl_plane_wm_level(crtc_state, plane_id,
+ level, 0);
+ wm_uv_level = skl_plane_wm_level(crtc_state, plane_id,
+ level, 1);
+
if (plane_id == PLANE_CURSOR)
continue;
@@ -4748,7 +4771,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
extra = min_t(u16, alloc_size,
DIV64_U64_ROUND_UP(alloc_size * rate,
total_data_rate));
- total[plane_id] = wm->wm[level].min_ddb_alloc + extra;
+ total[plane_id] = wm_level->min_ddb_alloc + extra;
alloc_size -= extra;
total_data_rate -= rate;
@@ -4759,7 +4782,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
extra = min_t(u16, alloc_size,
DIV64_U64_ROUND_UP(alloc_size * rate,
total_data_rate));
- uv_total[plane_id] = wm->uv_wm[level].min_ddb_alloc + extra;
+ uv_total[plane_id] = wm_uv_level->min_ddb_alloc + extra;
alloc_size -= extra;
total_data_rate -= rate;
}
@@ -4802,9 +4825,16 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
*/
for (level++; level <= ilk_wm_max_level(dev_priv); level++) {
for_each_plane_id_on_crtc(crtc, plane_id) {
+ const struct skl_wm_level *wm_level;
+ const struct skl_wm_level *wm_uv_level;
struct skl_plane_wm *wm =
&crtc_state->wm.skl.optimal.planes[plane_id];
+ wm_level = skl_plane_wm_level(crtc_state, plane_id,
+ level, 0);
+ wm_uv_level = skl_plane_wm_level(crtc_state, plane_id,
+ level, 1);
+
/*
* We only disable the watermarks for each plane if
* they exceed the ddb allocation of said plane. This
@@ -4817,9 +4847,13 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
* planes must be enabled before the level will be used."
* So this is actually safe to do.
*/
- if (wm->wm[level].min_ddb_alloc > total[plane_id] ||
- wm->uv_wm[level].min_ddb_alloc > uv_total[plane_id])
- memset(&wm->wm[level], 0, sizeof(wm->wm[level]));
+ if (wm_level->min_ddb_alloc > total[plane_id] ||
+ wm_uv_level->min_ddb_alloc > uv_total[plane_id]) {
+ memset(&wm->wm[level], 0,
+ sizeof(wm->wm[level]));
+ memset(&wm->uv_wm[level], 0,
+ sizeof(wm->uv_wm[level]));
+ }
/*
* Wa_1408961008:icl, ehl
@@ -4827,9 +4861,14 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
*/
if (IS_GEN(dev_priv, 11) &&
level == 1 && wm->wm[0].plane_en) {
- wm->wm[level].plane_res_b = wm->wm[0].plane_res_b;
- wm->wm[level].plane_res_l = wm->wm[0].plane_res_l;
- wm->wm[level].ignore_lines = wm->wm[0].ignore_lines;
+ wm_level = skl_plane_wm_level(crtc_state, plane_id,
+ 0, 0);
+ wm->wm[level].plane_res_b =
+ wm_level->plane_res_b;
+ wm->wm[level].plane_res_l =
+ wm_level->plane_res_l;
+ wm->wm[level].ignore_lines =
+ wm_level->ignore_lines;
}
}
}
@@ -5439,8 +5478,13 @@ void skl_write_plane_wm(struct intel_plane *plane,
&crtc_state->wm.skl.plane_ddb_uv[plane_id];
for (level = 0; level <= max_level; level++) {
+ const struct skl_wm_level *wm_level;
+ int color_plane = 0;
+
+ wm_level = skl_plane_wm_level(crtc_state, plane_id, level, color_plane);
+
skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),
- &wm->wm[level]);
+ wm_level);
}
skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
&wm->trans_wm);
@@ -5473,8 +5517,13 @@ void skl_write_cursor_wm(struct intel_plane *plane,
&crtc_state->wm.skl.plane_ddb_y[plane_id];
for (level = 0; level <= max_level; level++) {
+ const struct skl_wm_level *wm_level;
+ int color_plane = 0;
+
+ wm_level = skl_plane_wm_level(crtc_state, plane_id, level, color_plane);
+
skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
- &wm->wm[level]);
+ wm_level);
}
skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
--
2.24.1.485.gad05a3d8e5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [Intel-gfx] [PATCH v27 2/6] drm/i915: Separate icl and skl SAGV checking
2020-05-05 10:22 [Intel-gfx] [PATCH v27 0/6] SAGV support for Gen12+ Stanislav Lisovskiy
2020-05-05 10:22 ` [Intel-gfx] [PATCH v27 1/6] drm/i915: Introduce skl_plane_wm_level accessor Stanislav Lisovskiy
@ 2020-05-05 10:22 ` Stanislav Lisovskiy
2020-05-05 10:42 ` Ville Syrjälä
2020-05-05 10:22 ` [Intel-gfx] [PATCH v27 3/6] drm/i915: Add TGL+ SAGV support Stanislav Lisovskiy
` (5 subsequent siblings)
7 siblings, 1 reply; 24+ messages in thread
From: Stanislav Lisovskiy @ 2020-05-05 10:22 UTC (permalink / raw)
To: intel-gfx
Introduce platform dependent SAGV checking in
combination with bandwidth state pipe SAGV mask.
v2, v3, v4, v5, v6: Fix rebase conflict
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 30 ++++++++++++++++++++++++++++--
1 file changed, 28 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index da567fac7c93..c7d726a656b2 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3853,6 +3853,24 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state
return true;
}
+static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
+ /*
+ * SKL+ workaround: bspec recommends we disable SAGV when we have
+ * more then one pipe enabled
+ */
+ if (hweight8(state->active_pipes) > 1)
+ return false;
+
+ return intel_crtc_can_enable_sagv(crtc_state);
+}
+
+static bool icl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
+{
+ return intel_crtc_can_enable_sagv(crtc_state);
+}
+
bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
{
if (bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes))
@@ -3863,22 +3881,30 @@ bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
static int intel_compute_sagv_mask(struct intel_atomic_state *state)
{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
int ret;
struct intel_crtc *crtc;
- struct intel_crtc_state *new_crtc_state;
+ const struct intel_crtc_state *new_crtc_state;
struct intel_bw_state *new_bw_state = NULL;
const struct intel_bw_state *old_bw_state = NULL;
int i;
for_each_new_intel_crtc_in_state(state, crtc,
new_crtc_state, i) {
+ bool can_sagv;
+
new_bw_state = intel_atomic_get_bw_state(state);
if (IS_ERR(new_bw_state))
return PTR_ERR(new_bw_state);
old_bw_state = intel_atomic_get_old_bw_state(state);
- if (intel_crtc_can_enable_sagv(new_crtc_state))
+ if (INTEL_GEN(dev_priv) >= 11)
+ can_sagv = icl_crtc_can_enable_sagv(new_crtc_state);
+ else
+ can_sagv = skl_crtc_can_enable_sagv(new_crtc_state);
+
+ if (can_sagv)
new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
else
new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
--
2.24.1.485.gad05a3d8e5
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [Intel-gfx] [PATCH v27 3/6] drm/i915: Add TGL+ SAGV support
2020-05-05 10:22 [Intel-gfx] [PATCH v27 0/6] SAGV support for Gen12+ Stanislav Lisovskiy
2020-05-05 10:22 ` [Intel-gfx] [PATCH v27 1/6] drm/i915: Introduce skl_plane_wm_level accessor Stanislav Lisovskiy
2020-05-05 10:22 ` [Intel-gfx] [PATCH v27 2/6] drm/i915: Separate icl and skl SAGV checking Stanislav Lisovskiy
@ 2020-05-05 10:22 ` Stanislav Lisovskiy
2020-05-05 10:59 ` Ville Syrjälä
2020-05-05 10:22 ` [Intel-gfx] [PATCH v27 4/6] drm/i915: Added required new PCode commands Stanislav Lisovskiy
` (4 subsequent siblings)
7 siblings, 1 reply; 24+ messages in thread
From: Stanislav Lisovskiy @ 2020-05-05 10:22 UTC (permalink / raw)
To: intel-gfx
Starting from TGL we need to have a separate wm0
values for SAGV and non-SAGV which affects
how calculations are done.
v2: Remove long lines
v3: Removed COLOR_PLANE enum references
v4, v5, v6: Fixed rebase conflict
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 8 +-
.../drm/i915/display/intel_display_types.h | 3 +
drivers/gpu/drm/i915/intel_pm.c | 128 +++++++++++++++++-
3 files changed, 130 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index fd6d63b03489..be5741cb7595 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13961,7 +13961,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
/* Watermarks */
for (level = 0; level <= max_level; level++) {
if (skl_wm_level_equals(&hw_plane_wm->wm[level],
- &sw_plane_wm->wm[level]))
+ &sw_plane_wm->wm[level]) ||
+ (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
+ &sw_plane_wm->sagv_wm0)))
continue;
drm_err(&dev_priv->drm,
@@ -14016,7 +14018,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
/* Watermarks */
for (level = 0; level <= max_level; level++) {
if (skl_wm_level_equals(&hw_plane_wm->wm[level],
- &sw_plane_wm->wm[level]))
+ &sw_plane_wm->wm[level]) ||
+ (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
+ &sw_plane_wm->sagv_wm0)))
continue;
drm_err(&dev_priv->drm,
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 9488449e4b94..32cbbf7dddc6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -688,11 +688,14 @@ struct skl_plane_wm {
struct skl_wm_level wm[8];
struct skl_wm_level uv_wm[8];
struct skl_wm_level trans_wm;
+ struct skl_wm_level sagv_wm0;
+ struct skl_wm_level uv_sagv_wm0;
bool is_planar;
};
struct skl_pipe_wm {
struct skl_plane_wm planes[I915_MAX_PLANES];
+ bool can_sagv;
};
enum vlv_wm_level {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index c7d726a656b2..1b9925b6672c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3871,6 +3871,9 @@ static bool icl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
return intel_crtc_can_enable_sagv(crtc_state);
}
+static bool
+tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state);
+
bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
{
if (bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes))
@@ -3884,7 +3887,7 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
int ret;
struct intel_crtc *crtc;
- const struct intel_crtc_state *new_crtc_state;
+ struct intel_crtc_state *new_crtc_state;
struct intel_bw_state *new_bw_state = NULL;
const struct intel_bw_state *old_bw_state = NULL;
int i;
@@ -3899,7 +3902,9 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
old_bw_state = intel_atomic_get_old_bw_state(state);
- if (INTEL_GEN(dev_priv) >= 11)
+ if (INTEL_GEN(dev_priv) >= 12)
+ can_sagv = tgl_crtc_can_enable_sagv(new_crtc_state);
+ else if (INTEL_GEN(dev_priv) >= 11)
can_sagv = icl_crtc_can_enable_sagv(new_crtc_state);
else
can_sagv = skl_crtc_can_enable_sagv(new_crtc_state);
@@ -3921,6 +3926,24 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
return ret;
}
+ for_each_new_intel_crtc_in_state(state, crtc,
+ new_crtc_state, i) {
+ struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal;
+
+ /*
+ * Due to drm limitation at commit state, when
+ * changes are written the whole atomic state is
+ * zeroed away => which prevents from using it,
+ * so just sticking it into pipe wm state for
+ * keeping it simple - anyway this is related to wm.
+ * Proper way in ideal universe would be of course not
+ * to lose parent atomic state object from child crtc_state,
+ * and stick to OOP programming principles, which had been
+ * scientifically proven to work.
+ */
+ pipe_wm->can_sagv = intel_can_enable_sagv(new_bw_state);
+ }
+
if (intel_can_enable_sagv(new_bw_state) != intel_can_enable_sagv(old_bw_state)) {
ret = intel_atomic_serialize_global_state(&new_bw_state->base);
if (ret)
@@ -4664,12 +4687,39 @@ skl_plane_wm_level(const struct intel_crtc_state *crtc_state,
int level,
int color_plane)
{
- const struct skl_plane_wm *wm =
- &crtc_state->wm.skl.optimal.planes[plane_id];
+ const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
+ const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
+
+ if (!level) {
+ if (pipe_wm->can_sagv)
+ return color_plane == 0 ? &wm->sagv_wm0 : &wm->uv_sagv_wm0;
+ }
return color_plane == 0 ? &wm->wm[level] : &wm->uv_wm[level];
}
+static bool
+tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ enum plane_id plane_id;
+
+ if (!crtc_state->hw.active)
+ return true;
+
+ for_each_plane_id_on_crtc(crtc, plane_id) {
+ const struct skl_ddb_entry *plane_alloc =
+ &crtc_state->wm.skl.plane_ddb_y[plane_id];
+ const struct skl_plane_wm *wm =
+ &crtc_state->wm.skl.optimal.planes[plane_id];
+
+ if (skl_ddb_entry_size(plane_alloc) < wm->sagv_wm0.min_ddb_alloc)
+ return false;
+ }
+
+ return true;
+}
+
static int
skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
{
@@ -5251,10 +5301,17 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
static void
skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
const struct skl_wm_params *wm_params,
- struct skl_wm_level *levels)
+ struct skl_plane_wm *plane_wm,
+ int color_plane)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
int level, max_level = ilk_wm_max_level(dev_priv);
+ /*
+ * Check which kind of plane is it and based on that calculate
+ * correspondent WM levels.
+ */
+ struct skl_wm_level *levels = color_plane == 1 ?
+ plane_wm->uv_wm : plane_wm->wm;
struct skl_wm_level *result_prev = &levels[0];
for (level = 0; level <= max_level; level++) {
@@ -5268,6 +5325,40 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
}
}
+static void skl_compute_sagv_wm(const struct intel_crtc_state *crtc_state,
+ const struct skl_wm_params *wm_params,
+ struct skl_plane_wm *plane_wm,
+ int color_plane)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+ struct skl_wm_level *sagv_wm = color_plane == 1 ?
+ &plane_wm->uv_sagv_wm0 : &plane_wm->sagv_wm0;
+ struct skl_wm_level *levels = color_plane == 1 ?
+ plane_wm->uv_wm : plane_wm->wm;
+
+ /*
+ * For Gen12 if it is an L0 we need to also
+ * consider sagv_block_time when calculating
+ * L0 watermark - we will need that when making
+ * a decision whether enable SAGV or not.
+ * For older gens we agreed to copy L0 value for
+ * compatibility.
+ */
+ if ((INTEL_GEN(dev_priv) >= 12)) {
+ u32 latency = dev_priv->wm.skl_latency[0];
+
+ latency += dev_priv->sagv_block_time_us;
+ skl_compute_plane_wm(crtc_state, 0, latency,
+ wm_params, &levels[0],
+ sagv_wm);
+ DRM_DEBUG_KMS("%d L0 blocks required for SAGV vs %d for non-SAGV\n",
+ sagv_wm->min_ddb_alloc, levels[0].min_ddb_alloc);
+ } else {
+ /* Since all members are POD */
+ *sagv_wm = levels[0];
+ }
+}
+
static void skl_compute_transition_wm(const struct intel_crtc_state *crtc_state,
const struct skl_wm_params *wp,
struct skl_plane_wm *wm)
@@ -5344,7 +5435,8 @@ static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
- skl_compute_wm_levels(crtc_state, &wm_params, wm->wm);
+ skl_compute_wm_levels(crtc_state, &wm_params, wm, 0);
+ skl_compute_sagv_wm(crtc_state, &wm_params, wm, 0);
skl_compute_transition_wm(crtc_state, &wm_params, wm);
return 0;
@@ -5366,7 +5458,8 @@ static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
- skl_compute_wm_levels(crtc_state, &wm_params, wm->uv_wm);
+ skl_compute_wm_levels(crtc_state, &wm_params, wm, 1);
+ skl_compute_sagv_wm(crtc_state, &wm_params, wm, 1);
return 0;
}
@@ -5751,6 +5844,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
enast(new_wm->wm[7].ignore_lines), new_wm->wm[7].plane_res_l,
enast(new_wm->trans_wm.ignore_lines), new_wm->trans_wm.plane_res_l);
+ drm_dbg_kms(&dev_priv->drm,
+ "[PLANE:%d:%s] sagv wm0 lines %4d -> %4d\n",
+ plane->base.base.id, plane->base.name,
+ old_wm->sagv_wm0.plane_res_l,
+ new_wm->sagv_wm0.plane_res_l);
+
drm_dbg_kms(&dev_priv->drm,
"[PLANE:%d:%s] blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
" -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
@@ -5766,6 +5865,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
new_wm->wm[6].plane_res_b, new_wm->wm[7].plane_res_b,
new_wm->trans_wm.plane_res_b);
+ drm_dbg_kms(&dev_priv->drm,
+ "[PLANE:%d:%s] sagv wm0 blocks %4d -> %4d\n",
+ plane->base.base.id, plane->base.name,
+ old_wm->sagv_wm0.plane_res_b,
+ new_wm->sagv_wm0.plane_res_b);
+
drm_dbg_kms(&dev_priv->drm,
"[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
" -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
@@ -5780,6 +5885,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
new_wm->wm[4].min_ddb_alloc, new_wm->wm[5].min_ddb_alloc,
new_wm->wm[6].min_ddb_alloc, new_wm->wm[7].min_ddb_alloc,
new_wm->trans_wm.min_ddb_alloc);
+
+ drm_dbg_kms(&dev_priv->drm,
+ "[PLANE:%d:%s] sagv wm0 min ddb %4d -> %4d\n",
+ plane->base.base.id, plane->base.name,
+ old_wm->sagv_wm0.min_ddb_alloc,
+ new_wm->sagv_wm0.min_ddb_alloc);
}
}
}
@@ -6072,6 +6183,9 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
skl_wm_level_from_reg_val(val, &wm->wm[level]);
}
+ memcpy(&wm->sagv_wm0, &wm->wm[0],
+ sizeof(struct skl_wm_level));
+
if (plane_id != PLANE_CURSOR)
val = I915_READ(PLANE_WM_TRANS(pipe, plane_id));
else
--
2.24.1.485.gad05a3d8e5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [Intel-gfx] [PATCH v27 4/6] drm/i915: Added required new PCode commands
2020-05-05 10:22 [Intel-gfx] [PATCH v27 0/6] SAGV support for Gen12+ Stanislav Lisovskiy
` (2 preceding siblings ...)
2020-05-05 10:22 ` [Intel-gfx] [PATCH v27 3/6] drm/i915: Add TGL+ SAGV support Stanislav Lisovskiy
@ 2020-05-05 10:22 ` Stanislav Lisovskiy
2020-05-05 11:04 ` Ville Syrjälä
2020-05-05 10:22 ` [Intel-gfx] [PATCH v27 5/6] drm/i915: Restrict qgv points which don't have enough bandwidth Stanislav Lisovskiy
` (3 subsequent siblings)
7 siblings, 1 reply; 24+ messages in thread
From: Stanislav Lisovskiy @ 2020-05-05 10:22 UTC (permalink / raw)
To: intel-gfx
We need a new PCode request commands and reply codes
to be added as a prepartion patch for QGV points
restricting for new SAGV support.
v2: - Extracted those changes into separate patch
(Ville Syrjälä)
v3: - Moved new PCode masks to another place from
PCode commands(Ville)
v4: - Moved new PCode masks to correspondent PCode
command, with identation(Ville)
- Changed naming to ICL_ instead of GEN11_
to fit more nicely into existing definition
style.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 4 ++++
drivers/gpu/drm/i915/intel_sideband.c | 2 ++
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fd9f2904d93c..f23a18ee28f9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9064,6 +9064,7 @@ enum {
#define GEN7_PCODE_ILLEGAL_DATA 0x3
#define GEN11_PCODE_ILLEGAL_SUBCOMMAND 0x4
#define GEN11_PCODE_LOCKED 0x6
+#define GEN11_PCODE_REJECTED 0x11
#define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
#define GEN6_PCODE_WRITE_RC6VIDS 0x4
#define GEN6_PCODE_READ_RC6VIDS 0x5
@@ -9085,6 +9086,9 @@ enum {
#define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd
#define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8)
#define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8))
+#define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe
+#define ICL_PCODE_POINTS_RESTRICTED 0x0
+#define ICL_PCODE_POINTS_RESTRICTED_MASK 0x1
#define GEN6_PCODE_READ_D_COMP 0x10
#define GEN6_PCODE_WRITE_D_COMP 0x11
#define ICL_PCODE_EXIT_TCCOLD 0x12
diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
index d5129c1dd452..916ccd1c0e96 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -371,6 +371,8 @@ static int gen7_check_mailbox_status(u32 mbox)
return -ENXIO;
case GEN11_PCODE_LOCKED:
return -EBUSY;
+ case GEN11_PCODE_REJECTED:
+ return -EACCES;
case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
return -EOVERFLOW;
default:
--
2.24.1.485.gad05a3d8e5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [Intel-gfx] [PATCH v27 5/6] drm/i915: Restrict qgv points which don't have enough bandwidth.
2020-05-05 10:22 [Intel-gfx] [PATCH v27 0/6] SAGV support for Gen12+ Stanislav Lisovskiy
` (3 preceding siblings ...)
2020-05-05 10:22 ` [Intel-gfx] [PATCH v27 4/6] drm/i915: Added required new PCode commands Stanislav Lisovskiy
@ 2020-05-05 10:22 ` Stanislav Lisovskiy
2020-05-05 10:22 ` [Intel-gfx] [PATCH v27 6/6] drm/i915: Enable SAGV support for Gen12 Stanislav Lisovskiy
` (2 subsequent siblings)
7 siblings, 0 replies; 24+ messages in thread
From: Stanislav Lisovskiy @ 2020-05-05 10:22 UTC (permalink / raw)
To: intel-gfx
According to BSpec 53998, we should try to
restrict qgv points, which can't provide
enough bandwidth for desired display configuration.
Currently we are just comparing against all of
those and take minimum(worst case).
v2: Fixed wrong PCode reply mask, removed hardcoded
values.
v3: Forbid simultaneous legacy SAGV PCode requests and
restricting qgv points. Put the actual restriction
to commit function, added serialization(thanks to Ville)
to prevent commit being applied out of order in case of
nonblocking and/or nomodeset commits.
v4:
- Minor code refactoring, fixed few typos(thanks to James Ausmus)
- Change the naming of qgv point
masking/unmasking functions(James Ausmus).
- Simplify the masking/unmasking operation itself,
as we don't need to mask only single point per request(James Ausmus)
- Reject and stick to highest bandwidth point if SAGV
can't be enabled(BSpec)
v5:
- Add new mailbox reply codes, which seems to happen during boot
time for TGL and indicate that QGV setting is not yet available.
v6:
- Increase number of supported QGV points to be in sync with BSpec.
v7: - Rebased and resolved conflict to fix build failure.
- Fix NUM_QGV_POINTS to 8 and moved that to header file(James Ausmus)
v8: - Don't report an error if we can't restrict qgv points, as SAGV
can be disabled by BIOS, which is completely legal. So don't
make CI panic. Instead if we detect that there is only 1 QGV
point accessible just analyze if we can fit the required bandwidth
requirements, but no need in restricting.
v9: - Fix wrong QGV transition if we have 0 planes and no SAGV
simultaneously.
v10: - Fix CDCLK corruption, because of global state getting serialized
without modeset, which caused copying of non-calculated cdclk
to be copied to dev_priv(thanks to Ville for the hint).
v11: - Remove unneeded headers and spaces(Matthew Roper)
- Remove unneeded intel_qgv_info qi struct from bw check and zero
out the needed one(Matthew Roper)
- Changed QGV error message to have more clear meaning(Matthew Roper)
- Use state->modeset_set instead of any_ms(Matthew Roper)
- Moved NUM_SAGV_POINTS from i915_reg.h to i915_drv.h where it's used
- Keep using crtc_state->hw.active instead of .enable(Matthew Roper)
- Moved unrelated changes to other patch(using latency as parameter
for plane wm calculation, moved to SAGV refactoring patch)
v12: - Fix rebase conflict with own temporary SAGV/QGV fix.
- Remove unnecessary mask being zero check when unmasking
qgv points as this is completely legal(Matt Roper)
- Check if we are setting the same mask as already being set
in hardware to prevent error from PCode.
- Fix error message when restricting/unrestricting qgv points
to "mask/unmask" which sounds more accurate(Matt Roper)
- Move sagv status setting to icl_get_bw_info from atomic check
as this should be calculated only once.(Matt Roper)
- Edited comments for the case when we can't enable SAGV and
use only 1 QGV point with highest bandwidth to be more
understandable.(Matt Roper)
v13: - Moved max_data_rate in bw check to closer scope(Ville Syrjälä)
- Changed comment for zero new_mask in qgv points masking function
to better reflect reality(Ville Syrjälä)
- Simplified bit mask operation in qgv points masking function
(Ville Syrjälä)
- Moved intel_qgv_points_mask closer to gen11 SAGV disabling,
however this still can't be under modeset condition(Ville Syrjälä)
- Packed qgv_points_mask as u8 and moved closer to pipe_sagv_mask
(Ville Syrjälä)
- Extracted PCode changes to separate patch.(Ville Syrjälä)
- Now treat num_planes 0 same as 1 to avoid confusion and
returning max_bw as 0, which would prevent choosing QGV
point having max bandwidth in case if SAGV is not allowed,
as per BSpec(Ville Syrjälä)
- Do the actual qgv_points_mask swap in the same place as
all other global state parts like cdclk are swapped.
In the next patch, this all will be moved to bw state as
global state, once new global state patch series from Ville
lands
v14: - Now using global state to serialize access to qgv points
- Added global state locking back, otherwise we seem to read
bw state in a wrong way.
v15: - Added TODO comment for near atomic global state locking in
bw code.
v16: - Fixed intel_atomic_bw_* functions to be intel_bw_* as discussed
with Jani Nikula.
- Take bw_state_changed flag into use.
v17: - Moved qgv point related manipulations next to SAGV code, as
those are semantically related(Ville Syrjälä)
- Renamed those into intel_sagv_(pre)|(post)_plane_update
(Ville Syrjälä)
v18: - Move sagv related calls from commit tail into
intel_sagv_(pre)|(post)_plane_update(Ville Syrjälä)
v19: - Use intel_atomic_get_bw_(old)|(new)_state which is intended
for commit tail stage.
v20: - Return max bandwidth for 0 planes(Ville)
- Constify old_bw_state in bw_atomic_check(Ville)
- Removed some debugs(Ville)
- Added data rate to debug print when no QGV points(Ville)
- Removed some comments(Ville)
v21, v22, v23: - Fixed rebase conflict
v24: - Changed PCode mask to use ICL_ prefix
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: Ville Syrjälä <ville.syrjala@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.c | 139 +++++++++++++-----
drivers/gpu/drm/i915/display/intel_bw.h | 9 ++
.../drm/i915/display/intel_display_types.h | 3 +
drivers/gpu/drm/i915/intel_pm.c | 66 ++++++++-
drivers/gpu/drm/i915/intel_pm.h | 2 +
5 files changed, 181 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 6e7cc3a4f1aa..a192fd02c463 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -8,6 +8,9 @@
#include "intel_bw.h"
#include "intel_display_types.h"
#include "intel_sideband.h"
+#include "intel_atomic.h"
+#include "intel_pm.h"
+
/* Parameters for Qclk Geyserville (QGV) */
struct intel_qgv_point {
@@ -113,6 +116,26 @@ static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
return 0;
}
+int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
+ u32 points_mask)
+{
+ int ret;
+
+ /* bspec says to keep retrying for at least 1 ms */
+ ret = skl_pcode_request(dev_priv, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
+ points_mask,
+ ICL_PCODE_POINTS_RESTRICTED_MASK,
+ ICL_PCODE_POINTS_RESTRICTED,
+ 1);
+
+ if (ret < 0) {
+ DRM_ERROR("Failed to disable qgv points (%d)\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
struct intel_qgv_info *qi)
{
@@ -240,6 +263,16 @@ static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel
break;
}
+ /*
+ * In case if SAGV is disabled in BIOS, we always get 1
+ * SAGV point, but we can't send PCode commands to restrict it
+ * as it will fail and pointless anyway.
+ */
+ if (qi.num_points == 1)
+ dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
+ else
+ dev_priv->sagv_status = I915_SAGV_ENABLED;
+
return 0;
}
@@ -248,6 +281,11 @@ static unsigned int icl_max_bw(struct drm_i915_private *dev_priv,
{
int i;
+ /*
+ * Let's return max bw for 0 planes
+ */
+ num_planes = max(1, num_planes);
+
for (i = 0; i < ARRAY_SIZE(dev_priv->max_bw); i++) {
const struct intel_bw_info *bi =
&dev_priv->max_bw[i];
@@ -277,34 +315,6 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv)
icl_get_bw_info(dev_priv, &icl_sa_info);
}
-static unsigned int intel_max_data_rate(struct drm_i915_private *dev_priv,
- int num_planes)
-{
- if (INTEL_GEN(dev_priv) >= 11) {
- /*
- * Any bw group has same amount of QGV points
- */
- const struct intel_bw_info *bi =
- &dev_priv->max_bw[0];
- unsigned int min_bw = UINT_MAX;
- int i;
-
- /*
- * FIXME with SAGV disabled maybe we can assume
- * point 1 will always be used? Seems to match
- * the behaviour observed in the wild.
- */
- for (i = 0; i < bi->num_qgv_points; i++) {
- unsigned int bw = icl_max_bw(dev_priv, num_planes, i);
-
- min_bw = min(bw, min_bw);
- }
- return min_bw;
- } else {
- return UINT_MAX;
- }
-}
-
static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_state *crtc_state)
{
/*
@@ -415,10 +425,15 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_crtc_state *new_crtc_state, *old_crtc_state;
struct intel_bw_state *new_bw_state = NULL;
- unsigned int data_rate, max_data_rate;
+ const struct intel_bw_state *old_bw_state = NULL;
+ unsigned int data_rate;
unsigned int num_active_planes;
struct intel_crtc *crtc;
int i, ret;
+ u32 allowed_points = 0;
+ unsigned int max_bw_point = 0, max_bw = 0;
+ unsigned int num_qgv_points = dev_priv->max_bw[0].num_qgv_points;
+ u32 mask = (1 << num_qgv_points) - 1;
/* FIXME earlier gens need some checks too */
if (INTEL_GEN(dev_priv) < 11)
@@ -465,19 +480,73 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
return ret;
data_rate = intel_bw_data_rate(dev_priv, new_bw_state);
+ data_rate = DIV_ROUND_UP(data_rate, 1000);
+
num_active_planes = intel_bw_num_active_planes(dev_priv, new_bw_state);
- max_data_rate = intel_max_data_rate(dev_priv, num_active_planes);
+ for (i = 0; i < num_qgv_points; i++) {
+ unsigned int max_data_rate;
- data_rate = DIV_ROUND_UP(data_rate, 1000);
+ max_data_rate = icl_max_bw(dev_priv, num_active_planes, i);
+ /*
+ * We need to know which qgv point gives us
+ * maximum bandwidth in order to disable SAGV
+ * if we find that we exceed SAGV block time
+ * with watermarks. By that moment we already
+ * have those, as it is calculated earlier in
+ * intel_atomic_check,
+ */
+ if (max_data_rate > max_bw) {
+ max_bw_point = i;
+ max_bw = max_data_rate;
+ }
+ if (max_data_rate >= data_rate)
+ allowed_points |= BIT(i);
+ DRM_DEBUG_KMS("QGV point %d: max bw %d required %d\n",
+ i, max_data_rate, data_rate);
+ }
- if (data_rate > max_data_rate) {
- drm_dbg_kms(&dev_priv->drm,
- "Bandwidth %u MB/s exceeds max available %d MB/s (%d active planes)\n",
- data_rate, max_data_rate, num_active_planes);
+ /*
+ * BSpec states that we always should have at least one allowed point
+ * left, so if we couldn't - simply reject the configuration for obvious
+ * reasons.
+ */
+ if (allowed_points == 0) {
+ DRM_DEBUG_KMS("No QGV points provide sufficient memory"
+ " bandwidth %d for display configuration.\n", data_rate);
return -EINVAL;
}
+ /*
+ * Leave only single point with highest bandwidth, if
+ * we can't enable SAGV due to the increased memory latency it may
+ * cause.
+ */
+ if (!intel_can_enable_sagv(new_bw_state)) {
+ allowed_points = BIT(max_bw_point);
+ DRM_DEBUG_KMS("No SAGV, using single QGV point %d\n",
+ max_bw_point);
+ }
+ /*
+ * We store the ones which need to be masked as that is what PCode
+ * actually accepts as a parameter.
+ */
+ new_bw_state->qgv_points_mask = (~allowed_points) & mask;
+
+ old_bw_state = intel_atomic_get_old_bw_state(state);
+ if (!old_bw_state)
+ return -EINVAL;
+
+ /*
+ * If the actual mask had changed we need to make sure that
+ * the commits are serialized(in case this is a nomodeset, nonblocking)
+ */
+ if (new_bw_state->qgv_points_mask != old_bw_state->qgv_points_mask) {
+ ret = intel_atomic_serialize_global_state(&new_bw_state->base);
+ if (ret)
+ return ret;
+ }
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index 898b4a85ccab..bbcaaa73ec1b 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -24,6 +24,13 @@ struct intel_bw_state {
*/
u8 pipe_sagv_reject;
+ /*
+ * Current QGV points mask, which restricts
+ * some particular SAGV states, not to confuse
+ * with pipe_sagv_mask.
+ */
+ u8 qgv_points_mask;
+
unsigned int data_rate[I915_MAX_PIPES];
u8 num_active_planes[I915_MAX_PIPES];
@@ -47,5 +54,7 @@ int intel_bw_init(struct drm_i915_private *dev_priv);
int intel_bw_atomic_check(struct intel_atomic_state *state);
void intel_bw_crtc_update(struct intel_bw_state *bw_state,
const struct intel_crtc_state *crtc_state);
+int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
+ u32 points_mask);
#endif /* __INTEL_BW_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 32cbbf7dddc6..a16aeb235654 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -693,6 +693,9 @@ struct skl_plane_wm {
bool is_planar;
};
+/* BSpec precisely defines this */
+#define NUM_SAGV_POINTS 8
+
struct skl_pipe_wm {
struct skl_plane_wm planes[I915_MAX_PLANES];
bool can_sagv;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1b9925b6672c..5d0aab515e2a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3761,7 +3761,10 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ int ret;
const struct intel_bw_state *new_bw_state;
+ const struct intel_bw_state *old_bw_state;
+ u32 new_mask = 0;
/*
* Just return if we can't control SAGV or don't have it.
@@ -3777,15 +3780,48 @@ void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
if (!new_bw_state)
return;
- if (!intel_can_enable_sagv(new_bw_state))
+ if (INTEL_GEN(dev_priv) < 11 && !intel_can_enable_sagv(new_bw_state)) {
intel_disable_sagv(dev_priv);
+ return;
+ }
+
+ old_bw_state = intel_atomic_get_old_bw_state(state);
+ if (!old_bw_state)
+ return;
+
+ /*
+ * Nothing to mask
+ */
+ if (new_bw_state->qgv_points_mask == old_bw_state->qgv_points_mask)
+ return;
+
+ new_mask = old_bw_state->qgv_points_mask | new_bw_state->qgv_points_mask;
+
+ /*
+ * If new mask is zero - means there is nothing to mask,
+ * we can only unmask, which should be done in unmask.
+ */
+ if (!new_mask)
+ return;
+
+ /*
+ * Restrict required qgv points before updating the configuration.
+ * According to BSpec we can't mask and unmask qgv points at the same
+ * time. Also masking should be done before updating the configuration
+ * and unmasking afterwards.
+ */
+ ret = icl_pcode_restrict_qgv_points(dev_priv, new_mask);
+ if (ret < 0)
+ drm_err(&dev_priv->drm, "Could not mask required qgv points(%d)\n", ret);
}
void intel_sagv_post_plane_update(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ int ret;
const struct intel_bw_state *new_bw_state;
-
+ const struct intel_bw_state *old_bw_state;
+ u32 new_mask = 0;
/*
* Just return if we can't control SAGV or don't have it.
* This is different from situation when we have SAGV but just can't
@@ -3800,8 +3836,32 @@ void intel_sagv_post_plane_update(struct intel_atomic_state *state)
if (!new_bw_state)
return;
- if (intel_can_enable_sagv(new_bw_state))
+ if (INTEL_GEN(dev_priv) < 11 && intel_can_enable_sagv(new_bw_state)) {
intel_enable_sagv(dev_priv);
+ return;
+ }
+
+ old_bw_state = intel_atomic_get_old_bw_state(state);
+ if (!old_bw_state)
+ return;
+
+ /*
+ * Nothing to unmask
+ */
+ if (new_bw_state->qgv_points_mask == old_bw_state->qgv_points_mask)
+ return;
+
+ new_mask = new_bw_state->qgv_points_mask;
+
+ /*
+ * Allow required qgv points after updating the configuration.
+ * According to BSpec we can't mask and unmask qgv points at the same
+ * time. Also masking should be done before updating the configuration
+ * and unmasking afterwards.
+ */
+ ret = icl_pcode_restrict_qgv_points(dev_priv, new_mask);
+ if (ret < 0)
+ drm_err(&dev_priv->drm, "Could not unmask required qgv points(%d)\n", ret);
}
static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index fd1dc422e6c5..4ae91ad5d5b3 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -42,6 +42,8 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
struct skl_pipe_wm *out);
void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
+void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
+void intel_sagv_post_plane_update(struct intel_atomic_state *state);
bool intel_can_enable_sagv(const struct intel_bw_state *bw_state);
int intel_enable_sagv(struct drm_i915_private *dev_priv);
int intel_disable_sagv(struct drm_i915_private *dev_priv);
--
2.24.1.485.gad05a3d8e5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [Intel-gfx] [PATCH v27 6/6] drm/i915: Enable SAGV support for Gen12
2020-05-05 10:22 [Intel-gfx] [PATCH v27 0/6] SAGV support for Gen12+ Stanislav Lisovskiy
` (4 preceding siblings ...)
2020-05-05 10:22 ` [Intel-gfx] [PATCH v27 5/6] drm/i915: Restrict qgv points which don't have enough bandwidth Stanislav Lisovskiy
@ 2020-05-05 10:22 ` Stanislav Lisovskiy
2020-05-05 13:46 ` [Intel-gfx] ✓ Fi.CI.BAT: success for SAGV support for Gen12+ (rev35) Patchwork
2020-05-06 1:01 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
7 siblings, 0 replies; 24+ messages in thread
From: Stanislav Lisovskiy @ 2020-05-05 10:22 UTC (permalink / raw)
To: intel-gfx
Flip the switch and enable SAGV support
for Gen12 also.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5d0aab515e2a..a12f1d0a0be2 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3638,10 +3638,6 @@ static bool skl_needs_memory_bw_wa(struct drm_i915_private *dev_priv)
static bool
intel_has_sagv(struct drm_i915_private *dev_priv)
{
- /* HACK! */
- if (IS_GEN(dev_priv, 12))
- return false;
-
return (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) &&
dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
}
--
2.24.1.485.gad05a3d8e5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [Intel-gfx] [PATCH v27 2/6] drm/i915: Separate icl and skl SAGV checking
2020-05-05 10:22 ` [Intel-gfx] [PATCH v27 2/6] drm/i915: Separate icl and skl SAGV checking Stanislav Lisovskiy
@ 2020-05-05 10:42 ` Ville Syrjälä
2020-05-05 11:01 ` Ville Syrjälä
2020-05-06 7:55 ` Lisovskiy, Stanislav
0 siblings, 2 replies; 24+ messages in thread
From: Ville Syrjälä @ 2020-05-05 10:42 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
On Tue, May 05, 2020 at 01:22:43PM +0300, Stanislav Lisovskiy wrote:
> Introduce platform dependent SAGV checking in
> combination with bandwidth state pipe SAGV mask.
>
> v2, v3, v4, v5, v6: Fix rebase conflict
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 30 ++++++++++++++++++++++++++++--
> 1 file changed, 28 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index da567fac7c93..c7d726a656b2 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3853,6 +3853,24 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state
> return true;
> }
>
> +static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
> + /*
> + * SKL+ workaround: bspec recommends we disable SAGV when we have
> + * more then one pipe enabled
> + */
> + if (hweight8(state->active_pipes) > 1)
> + return false;
That stuff should no longer be here since we now have it done properly
in intel_can_eanble_sagv().
> +
> + return intel_crtc_can_enable_sagv(crtc_state);
> +}
> +
> +static bool icl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> +{
> + return intel_crtc_can_enable_sagv(crtc_state);
> +}
This looks the wrong way around. IMO intel_crtc_can_enable_sagv()
should rather call the skl vs. icl variants as needed. Although we
don't yet have the icl variant so the oerdering of the patches is
a bit weird.
> +
> bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
> {
> if (bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes))
> @@ -3863,22 +3881,30 @@ bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
>
> static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> {
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> int ret;
> struct intel_crtc *crtc;
> - struct intel_crtc_state *new_crtc_state;
> + const struct intel_crtc_state *new_crtc_state;
> struct intel_bw_state *new_bw_state = NULL;
> const struct intel_bw_state *old_bw_state = NULL;
> int i;
>
> for_each_new_intel_crtc_in_state(state, crtc,
> new_crtc_state, i) {
> + bool can_sagv;
> +
> new_bw_state = intel_atomic_get_bw_state(state);
> if (IS_ERR(new_bw_state))
> return PTR_ERR(new_bw_state);
>
> old_bw_state = intel_atomic_get_old_bw_state(state);
>
> - if (intel_crtc_can_enable_sagv(new_crtc_state))
> + if (INTEL_GEN(dev_priv) >= 11)
> + can_sagv = icl_crtc_can_enable_sagv(new_crtc_state);
> + else
> + can_sagv = skl_crtc_can_enable_sagv(new_crtc_state);
> +
> + if (can_sagv)
> new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
> else
> new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
> --
> 2.24.1.485.gad05a3d8e5
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Intel-gfx] [PATCH v27 3/6] drm/i915: Add TGL+ SAGV support
2020-05-05 10:22 ` [Intel-gfx] [PATCH v27 3/6] drm/i915: Add TGL+ SAGV support Stanislav Lisovskiy
@ 2020-05-05 10:59 ` Ville Syrjälä
2020-05-06 8:31 ` Lisovskiy, Stanislav
0 siblings, 1 reply; 24+ messages in thread
From: Ville Syrjälä @ 2020-05-05 10:59 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
On Tue, May 05, 2020 at 01:22:44PM +0300, Stanislav Lisovskiy wrote:
> Starting from TGL we need to have a separate wm0
> values for SAGV and non-SAGV which affects
> how calculations are done.
>
> v2: Remove long lines
> v3: Removed COLOR_PLANE enum references
> v4, v5, v6: Fixed rebase conflict
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 8 +-
> .../drm/i915/display/intel_display_types.h | 3 +
> drivers/gpu/drm/i915/intel_pm.c | 128 +++++++++++++++++-
> 3 files changed, 130 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index fd6d63b03489..be5741cb7595 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -13961,7 +13961,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
> /* Watermarks */
> for (level = 0; level <= max_level; level++) {
> if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> - &sw_plane_wm->wm[level]))
> + &sw_plane_wm->wm[level]) ||
> + (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
> + &sw_plane_wm->sagv_wm0)))
> continue;
>
> drm_err(&dev_priv->drm,
> @@ -14016,7 +14018,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
> /* Watermarks */
> for (level = 0; level <= max_level; level++) {
> if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> - &sw_plane_wm->wm[level]))
> + &sw_plane_wm->wm[level]) ||
> + (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
> + &sw_plane_wm->sagv_wm0)))
> continue;
>
> drm_err(&dev_priv->drm,
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 9488449e4b94..32cbbf7dddc6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -688,11 +688,14 @@ struct skl_plane_wm {
> struct skl_wm_level wm[8];
> struct skl_wm_level uv_wm[8];
> struct skl_wm_level trans_wm;
> + struct skl_wm_level sagv_wm0;
> + struct skl_wm_level uv_sagv_wm0;
As mentioned before uv_wm is not a thing on icl+, so nuke this.
> bool is_planar;
> };
>
> struct skl_pipe_wm {
> struct skl_plane_wm planes[I915_MAX_PLANES];
> + bool can_sagv;
I would call it use_sagv_wm or somesuch to make it actually clear what
it does.
> };
>
> enum vlv_wm_level {
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index c7d726a656b2..1b9925b6672c 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3871,6 +3871,9 @@ static bool icl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> return intel_crtc_can_enable_sagv(crtc_state);
> }
>
> +static bool
> +tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state);
> +
> bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
> {
> if (bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes))
> @@ -3884,7 +3887,7 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> int ret;
> struct intel_crtc *crtc;
> - const struct intel_crtc_state *new_crtc_state;
> + struct intel_crtc_state *new_crtc_state;
> struct intel_bw_state *new_bw_state = NULL;
> const struct intel_bw_state *old_bw_state = NULL;
> int i;
> @@ -3899,7 +3902,9 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
>
> old_bw_state = intel_atomic_get_old_bw_state(state);
>
> - if (INTEL_GEN(dev_priv) >= 11)
> + if (INTEL_GEN(dev_priv) >= 12)
> + can_sagv = tgl_crtc_can_enable_sagv(new_crtc_state);
> + else if (INTEL_GEN(dev_priv) >= 11)
> can_sagv = icl_crtc_can_enable_sagv(new_crtc_state);
> else
> can_sagv = skl_crtc_can_enable_sagv(new_crtc_state);
> @@ -3921,6 +3926,24 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> return ret;
> }
>
> + for_each_new_intel_crtc_in_state(state, crtc,
> + new_crtc_state, i) {
> + struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal;
> +
> + /*
> + * Due to drm limitation at commit state, when
> + * changes are written the whole atomic state is
> + * zeroed away => which prevents from using it,
> + * so just sticking it into pipe wm state for
> + * keeping it simple - anyway this is related to wm.
> + * Proper way in ideal universe would be of course not
> + * to lose parent atomic state object from child crtc_state,
> + * and stick to OOP programming principles, which had been
> + * scientifically proven to work.
Seems like random ramblings. I'd just nuke the comment.
> + */
> + pipe_wm->can_sagv = intel_can_enable_sagv(new_bw_state);
> + }
> +
> if (intel_can_enable_sagv(new_bw_state) != intel_can_enable_sagv(old_bw_state)) {
> ret = intel_atomic_serialize_global_state(&new_bw_state->base);
> if (ret)
> @@ -4664,12 +4687,39 @@ skl_plane_wm_level(const struct intel_crtc_state *crtc_state,
> int level,
> int color_plane)
> {
> - const struct skl_plane_wm *wm =
> - &crtc_state->wm.skl.optimal.planes[plane_id];
> + const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
> + const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
> +
> + if (!level) {
> + if (pipe_wm->can_sagv)
> + return color_plane == 0 ? &wm->sagv_wm0 : &wm->uv_sagv_wm0;
> + }
>
> return color_plane == 0 ? &wm->wm[level] : &wm->uv_wm[level];
> }
>
> +static bool
> +tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + enum plane_id plane_id;
> +
> + if (!crtc_state->hw.active)
> + return true;
> +
> + for_each_plane_id_on_crtc(crtc, plane_id) {
> + const struct skl_ddb_entry *plane_alloc =
> + &crtc_state->wm.skl.plane_ddb_y[plane_id];
> + const struct skl_plane_wm *wm =
> + &crtc_state->wm.skl.optimal.planes[plane_id];
> +
> + if (skl_ddb_entry_size(plane_alloc) < wm->sagv_wm0.min_ddb_alloc)
> + return false;
> + }
> +
> + return true;
> +}
> +
> static int
> skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
> {
> @@ -5251,10 +5301,17 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
> static void
> skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
> const struct skl_wm_params *wm_params,
> - struct skl_wm_level *levels)
> + struct skl_plane_wm *plane_wm,
> + int color_plane)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> int level, max_level = ilk_wm_max_level(dev_priv);
> + /*
> + * Check which kind of plane is it and based on that calculate
> + * correspondent WM levels.
> + */
> + struct skl_wm_level *levels = color_plane == 1 ?
> + plane_wm->uv_wm : plane_wm->wm;
> struct skl_wm_level *result_prev = &levels[0];
>
> for (level = 0; level <= max_level; level++) {
> @@ -5268,6 +5325,40 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
> }
> }
>
> +static void skl_compute_sagv_wm(const struct intel_crtc_state *crtc_state,
> + const struct skl_wm_params *wm_params,
> + struct skl_plane_wm *plane_wm,
> + int color_plane)
> +{
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> + struct skl_wm_level *sagv_wm = color_plane == 1 ?
> + &plane_wm->uv_sagv_wm0 : &plane_wm->sagv_wm0;
> + struct skl_wm_level *levels = color_plane == 1 ?
> + plane_wm->uv_wm : plane_wm->wm;
> +
> + /*
> + * For Gen12 if it is an L0 we need to also
> + * consider sagv_block_time when calculating
> + * L0 watermark - we will need that when making
> + * a decision whether enable SAGV or not.
> + * For older gens we agreed to copy L0 value for
> + * compatibility.
> + */
> + if ((INTEL_GEN(dev_priv) >= 12)) {
> + u32 latency = dev_priv->wm.skl_latency[0];
> +
> + latency += dev_priv->sagv_block_time_us;
> + skl_compute_plane_wm(crtc_state, 0, latency,
> + wm_params, &levels[0],
> + sagv_wm);
> + DRM_DEBUG_KMS("%d L0 blocks required for SAGV vs %d for non-SAGV\n",
> + sagv_wm->min_ddb_alloc, levels[0].min_ddb_alloc);
> + } else {
> + /* Since all members are POD */
> + *sagv_wm = levels[0];
> + }
> +}
> +
> static void skl_compute_transition_wm(const struct intel_crtc_state *crtc_state,
> const struct skl_wm_params *wp,
> struct skl_plane_wm *wm)
> @@ -5344,7 +5435,8 @@ static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
> if (ret)
> return ret;
>
> - skl_compute_wm_levels(crtc_state, &wm_params, wm->wm);
> + skl_compute_wm_levels(crtc_state, &wm_params, wm, 0);
> + skl_compute_sagv_wm(crtc_state, &wm_params, wm, 0);
> skl_compute_transition_wm(crtc_state, &wm_params, wm);
>
> return 0;
> @@ -5366,7 +5458,8 @@ static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
> if (ret)
> return ret;
>
> - skl_compute_wm_levels(crtc_state, &wm_params, wm->uv_wm);
> + skl_compute_wm_levels(crtc_state, &wm_params, wm, 1);
> + skl_compute_sagv_wm(crtc_state, &wm_params, wm, 1);
>
> return 0;
> }
> @@ -5751,6 +5844,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
> enast(new_wm->wm[7].ignore_lines), new_wm->wm[7].plane_res_l,
> enast(new_wm->trans_wm.ignore_lines), new_wm->trans_wm.plane_res_l);
>
> + drm_dbg_kms(&dev_priv->drm,
> + "[PLANE:%d:%s] sagv wm0 lines %4d -> %4d\n",
> + plane->base.base.id, plane->base.name,
> + old_wm->sagv_wm0.plane_res_l,
> + new_wm->sagv_wm0.plane_res_l);
> +
> drm_dbg_kms(&dev_priv->drm,
> "[PLANE:%d:%s] blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
> " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
> @@ -5766,6 +5865,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
> new_wm->wm[6].plane_res_b, new_wm->wm[7].plane_res_b,
> new_wm->trans_wm.plane_res_b);
>
> + drm_dbg_kms(&dev_priv->drm,
> + "[PLANE:%d:%s] sagv wm0 blocks %4d -> %4d\n",
> + plane->base.base.id, plane->base.name,
> + old_wm->sagv_wm0.plane_res_b,
> + new_wm->sagv_wm0.plane_res_b);
> +
> drm_dbg_kms(&dev_priv->drm,
> "[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
> " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
> @@ -5780,6 +5885,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
> new_wm->wm[4].min_ddb_alloc, new_wm->wm[5].min_ddb_alloc,
> new_wm->wm[6].min_ddb_alloc, new_wm->wm[7].min_ddb_alloc,
> new_wm->trans_wm.min_ddb_alloc);
> +
> + drm_dbg_kms(&dev_priv->drm,
> + "[PLANE:%d:%s] sagv wm0 min ddb %4d -> %4d\n",
> + plane->base.base.id, plane->base.name,
> + old_wm->sagv_wm0.min_ddb_alloc,
> + new_wm->sagv_wm0.min_ddb_alloc);
> }
> }
> }
> @@ -6072,6 +6183,9 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
> skl_wm_level_from_reg_val(val, &wm->wm[level]);
> }
>
> + memcpy(&wm->sagv_wm0, &wm->wm[0],
> + sizeof(struct skl_wm_level));
> +
> if (plane_id != PLANE_CURSOR)
> val = I915_READ(PLANE_WM_TRANS(pipe, plane_id));
> else
> --
> 2.24.1.485.gad05a3d8e5
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Intel-gfx] [PATCH v27 2/6] drm/i915: Separate icl and skl SAGV checking
2020-05-05 10:42 ` Ville Syrjälä
@ 2020-05-05 11:01 ` Ville Syrjälä
2020-05-05 20:37 ` Lisovskiy, Stanislav
2020-05-06 7:55 ` Lisovskiy, Stanislav
1 sibling, 1 reply; 24+ messages in thread
From: Ville Syrjälä @ 2020-05-05 11:01 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
On Tue, May 05, 2020 at 01:42:46PM +0300, Ville Syrjälä wrote:
> On Tue, May 05, 2020 at 01:22:43PM +0300, Stanislav Lisovskiy wrote:
> > Introduce platform dependent SAGV checking in
> > combination with bandwidth state pipe SAGV mask.
> >
> > v2, v3, v4, v5, v6: Fix rebase conflict
> >
> > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_pm.c | 30 ++++++++++++++++++++++++++++--
> > 1 file changed, 28 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index da567fac7c93..c7d726a656b2 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3853,6 +3853,24 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state
> > return true;
> > }
> >
> > +static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> > +{
> > + struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
> > + /*
> > + * SKL+ workaround: bspec recommends we disable SAGV when we have
> > + * more then one pipe enabled
> > + */
> > + if (hweight8(state->active_pipes) > 1)
> > + return false;
>
> That stuff should no longer be here since we now have it done properly
> in intel_can_eanble_sagv().
>
> > +
> > + return intel_crtc_can_enable_sagv(crtc_state);
> > +}
> > +
> > +static bool icl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> > +{
> > + return intel_crtc_can_enable_sagv(crtc_state);
> > +}
>
> This looks the wrong way around. IMO intel_crtc_can_enable_sagv()
> should rather call the skl vs. icl variants as needed. Although we
> don't yet have the icl variant so the oerdering of the patches is
> a bit weird.
Do we even need an icl variant actually? Does it use the skl or tgl
way of checking for sagv yes vs. no?
>
> > +
> > bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
> > {
> > if (bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes))
> > @@ -3863,22 +3881,30 @@ bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
> >
> > static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > {
> > + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > int ret;
> > struct intel_crtc *crtc;
> > - struct intel_crtc_state *new_crtc_state;
> > + const struct intel_crtc_state *new_crtc_state;
> > struct intel_bw_state *new_bw_state = NULL;
> > const struct intel_bw_state *old_bw_state = NULL;
> > int i;
> >
> > for_each_new_intel_crtc_in_state(state, crtc,
> > new_crtc_state, i) {
> > + bool can_sagv;
> > +
> > new_bw_state = intel_atomic_get_bw_state(state);
> > if (IS_ERR(new_bw_state))
> > return PTR_ERR(new_bw_state);
> >
> > old_bw_state = intel_atomic_get_old_bw_state(state);
> >
> > - if (intel_crtc_can_enable_sagv(new_crtc_state))
> > + if (INTEL_GEN(dev_priv) >= 11)
> > + can_sagv = icl_crtc_can_enable_sagv(new_crtc_state);
> > + else
> > + can_sagv = skl_crtc_can_enable_sagv(new_crtc_state);
> > +
> > + if (can_sagv)
> > new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
> > else
> > new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
> > --
> > 2.24.1.485.gad05a3d8e5
>
> --
> Ville Syrjälä
> Intel
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Intel-gfx] [PATCH v27 4/6] drm/i915: Added required new PCode commands
2020-05-05 10:22 ` [Intel-gfx] [PATCH v27 4/6] drm/i915: Added required new PCode commands Stanislav Lisovskiy
@ 2020-05-05 11:04 ` Ville Syrjälä
0 siblings, 0 replies; 24+ messages in thread
From: Ville Syrjälä @ 2020-05-05 11:04 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
On Tue, May 05, 2020 at 01:22:45PM +0300, Stanislav Lisovskiy wrote:
> We need a new PCode request commands and reply codes
> to be added as a prepartion patch for QGV points
> restricting for new SAGV support.
>
> v2: - Extracted those changes into separate patch
> (Ville Syrjälä)
>
> v3: - Moved new PCode masks to another place from
> PCode commands(Ville)
>
> v4: - Moved new PCode masks to correspondent PCode
> command, with identation(Ville)
> - Changed naming to ICL_ instead of GEN11_
> to fit more nicely into existing definition
> style.
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Thanks. Pushed this one.
> ---
> drivers/gpu/drm/i915/i915_reg.h | 4 ++++
> drivers/gpu/drm/i915/intel_sideband.c | 2 ++
> 2 files changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index fd9f2904d93c..f23a18ee28f9 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9064,6 +9064,7 @@ enum {
> #define GEN7_PCODE_ILLEGAL_DATA 0x3
> #define GEN11_PCODE_ILLEGAL_SUBCOMMAND 0x4
> #define GEN11_PCODE_LOCKED 0x6
> +#define GEN11_PCODE_REJECTED 0x11
> #define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
> #define GEN6_PCODE_WRITE_RC6VIDS 0x4
> #define GEN6_PCODE_READ_RC6VIDS 0x5
> @@ -9085,6 +9086,9 @@ enum {
> #define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd
> #define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8)
> #define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8))
> +#define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe
> +#define ICL_PCODE_POINTS_RESTRICTED 0x0
> +#define ICL_PCODE_POINTS_RESTRICTED_MASK 0x1
> #define GEN6_PCODE_READ_D_COMP 0x10
> #define GEN6_PCODE_WRITE_D_COMP 0x11
> #define ICL_PCODE_EXIT_TCCOLD 0x12
> diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
> index d5129c1dd452..916ccd1c0e96 100644
> --- a/drivers/gpu/drm/i915/intel_sideband.c
> +++ b/drivers/gpu/drm/i915/intel_sideband.c
> @@ -371,6 +371,8 @@ static int gen7_check_mailbox_status(u32 mbox)
> return -ENXIO;
> case GEN11_PCODE_LOCKED:
> return -EBUSY;
> + case GEN11_PCODE_REJECTED:
> + return -EACCES;
> case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
> return -EOVERFLOW;
> default:
> --
> 2.24.1.485.gad05a3d8e5
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for SAGV support for Gen12+ (rev35)
2020-05-05 10:22 [Intel-gfx] [PATCH v27 0/6] SAGV support for Gen12+ Stanislav Lisovskiy
` (5 preceding siblings ...)
2020-05-05 10:22 ` [Intel-gfx] [PATCH v27 6/6] drm/i915: Enable SAGV support for Gen12 Stanislav Lisovskiy
@ 2020-05-05 13:46 ` Patchwork
2020-05-06 1:01 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
7 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2020-05-05 13:46 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: SAGV support for Gen12+ (rev35)
URL : https://patchwork.freedesktop.org/series/75129/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8430 -> Patchwork_17581
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17581/index.html
Changes
-------
No changes found
Participating hosts (50 -> 42)
------------------------------
Missing (8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-bwr-2160 fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8430 -> Patchwork_17581
CI-20190529: 20190529
CI_DRM_8430: 2daa6f8cad645f49a898158190a20a893b4aabe3 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5632: e630cb8cd2ec01d6d5358eb2a3f6ea70498b8183 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17581: c9b00f24365bb8afb5caae9aa834993b996bc66a @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
c9b00f24365b drm/i915: Enable SAGV support for Gen12
f4e7158266f6 drm/i915: Restrict qgv points which don't have enough bandwidth.
5dd210b03447 drm/i915: Add TGL+ SAGV support
9ac87f34c218 drm/i915: Separate icl and skl SAGV checking
c2e36d77edc9 drm/i915: Introduce skl_plane_wm_level accessor.
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17581/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Intel-gfx] [PATCH v27 2/6] drm/i915: Separate icl and skl SAGV checking
2020-05-05 11:01 ` Ville Syrjälä
@ 2020-05-05 20:37 ` Lisovskiy, Stanislav
2020-05-06 7:31 ` Ville Syrjälä
0 siblings, 1 reply; 24+ messages in thread
From: Lisovskiy, Stanislav @ 2020-05-05 20:37 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Tue, May 05, 2020 at 02:01:16PM +0300, Ville Syrjälä wrote:
> On Tue, May 05, 2020 at 01:42:46PM +0300, Ville Syrjälä wrote:
> > On Tue, May 05, 2020 at 01:22:43PM +0300, Stanislav Lisovskiy wrote:
> > > Introduce platform dependent SAGV checking in
> > > combination with bandwidth state pipe SAGV mask.
> > >
> > > v2, v3, v4, v5, v6: Fix rebase conflict
> > >
> > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/intel_pm.c | 30 ++++++++++++++++++++++++++++--
> > > 1 file changed, 28 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > index da567fac7c93..c7d726a656b2 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -3853,6 +3853,24 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state
> > > return true;
> > > }
> > >
> > > +static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> > > +{
> > > + struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
> > > + /*
> > > + * SKL+ workaround: bspec recommends we disable SAGV when we have
> > > + * more then one pipe enabled
> > > + */
> > > + if (hweight8(state->active_pipes) > 1)
> > > + return false;
> >
> > That stuff should no longer be here since we now have it done properly
> > in intel_can_eanble_sagv().
> >
> > > +
> > > + return intel_crtc_can_enable_sagv(crtc_state);
> > > +}
> > > +
> > > +static bool icl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> > > +{
> > > + return intel_crtc_can_enable_sagv(crtc_state);
> > > +}
> >
> > This looks the wrong way around. IMO intel_crtc_can_enable_sagv()
> > should rather call the skl vs. icl variants as needed. Although we
> > don't yet have the icl variant so the oerdering of the patches is
> > a bit weird.
>
> Do we even need an icl variant actually? Does it use the skl or tgl
> way of checking for sagv yes vs. no?
As I undestand icl implementation should be pretty much the same as
skl, except that icl doesn't have this one active pipe limitation
thing.
Stan
>
> >
> > > +
> > > bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
> > > {
> > > if (bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes))
> > > @@ -3863,22 +3881,30 @@ bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
> > >
> > > static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > > {
> > > + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > > int ret;
> > > struct intel_crtc *crtc;
> > > - struct intel_crtc_state *new_crtc_state;
> > > + const struct intel_crtc_state *new_crtc_state;
> > > struct intel_bw_state *new_bw_state = NULL;
> > > const struct intel_bw_state *old_bw_state = NULL;
> > > int i;
> > >
> > > for_each_new_intel_crtc_in_state(state, crtc,
> > > new_crtc_state, i) {
> > > + bool can_sagv;
> > > +
> > > new_bw_state = intel_atomic_get_bw_state(state);
> > > if (IS_ERR(new_bw_state))
> > > return PTR_ERR(new_bw_state);
> > >
> > > old_bw_state = intel_atomic_get_old_bw_state(state);
> > >
> > > - if (intel_crtc_can_enable_sagv(new_crtc_state))
> > > + if (INTEL_GEN(dev_priv) >= 11)
> > > + can_sagv = icl_crtc_can_enable_sagv(new_crtc_state);
> > > + else
> > > + can_sagv = skl_crtc_can_enable_sagv(new_crtc_state);
> > > +
> > > + if (can_sagv)
> > > new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
> > > else
> > > new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
> > > --
> > > 2.24.1.485.gad05a3d8e5
> >
> > --
> > Ville Syrjälä
> > Intel
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for SAGV support for Gen12+ (rev35)
2020-05-05 10:22 [Intel-gfx] [PATCH v27 0/6] SAGV support for Gen12+ Stanislav Lisovskiy
` (6 preceding siblings ...)
2020-05-05 13:46 ` [Intel-gfx] ✓ Fi.CI.BAT: success for SAGV support for Gen12+ (rev35) Patchwork
@ 2020-05-06 1:01 ` Patchwork
7 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2020-05-06 1:01 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx
== Series Details ==
Series: SAGV support for Gen12+ (rev35)
URL : https://patchwork.freedesktop.org/series/75129/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8430_full -> Patchwork_17581_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_17581_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_workarounds@suspend-resume:
- shard-apl: [PASS][1] -> [DMESG-WARN][2] ([i915#180])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8430/shard-apl4/igt@gem_workarounds@suspend-resume.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17581/shard-apl6/igt@gem_workarounds@suspend-resume.html
* igt@kms_cursor_edge_walk@pipe-a-64x64-top-edge:
- shard-apl: [PASS][3] -> [FAIL][4] ([i915#70] / [i915#95])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8430/shard-apl3/igt@kms_cursor_edge_walk@pipe-a-64x64-top-edge.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17581/shard-apl3/igt@kms_cursor_edge_walk@pipe-a-64x64-top-edge.html
- shard-kbl: [PASS][5] -> [FAIL][6] ([i915#70])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8430/shard-kbl6/igt@kms_cursor_edge_walk@pipe-a-64x64-top-edge.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17581/shard-kbl7/igt@kms_cursor_edge_walk@pipe-a-64x64-top-edge.html
* igt@kms_cursor_legacy@all-pipes-single-move:
- shard-hsw: [PASS][7] -> [INCOMPLETE][8] ([i915#61])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8430/shard-hsw7/igt@kms_cursor_legacy@all-pipes-single-move.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17581/shard-hsw8/igt@kms_cursor_legacy@all-pipes-single-move.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-pgflip-blt:
- shard-skl: [PASS][9] -> [FAIL][10] ([i915#49])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8430/shard-skl2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-pgflip-blt.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17581/shard-skl2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-pgflip-blt.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
- shard-skl: [PASS][11] -> [INCOMPLETE][12] ([i915#69])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8430/shard-skl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17581/shard-skl10/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#109441]) +2 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8430/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17581/shard-iclb4/igt@kms_psr@psr2_cursor_render.html
#### Possible fixes ####
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-apl: [DMESG-WARN][15] ([i915#180] / [i915#95]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8430/shard-apl8/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17581/shard-apl3/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_legacy@all-pipes-torture-move:
- shard-hsw: [DMESG-WARN][17] ([i915#128]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8430/shard-hsw1/igt@kms_cursor_legacy@all-pipes-torture-move.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17581/shard-hsw4/igt@kms_cursor_legacy@all-pipes-torture-move.html
* {igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1}:
- shard-apl: [FAIL][19] ([i915#79]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8430/shard-apl7/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17581/shard-apl8/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1.html
* {igt@kms_flip@flip-vs-expired-vblank@b-edp1}:
- shard-skl: [FAIL][21] ([i915#79]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8430/shard-skl2/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17581/shard-skl2/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
* {igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1}:
- shard-skl: [FAIL][23] ([i915#34]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8430/shard-skl1/igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17581/shard-skl5/igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [FAIL][25] ([i915#1188]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8430/shard-skl6/igt@kms_hdr@bpc-switch-dpms.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17581/shard-skl1/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-kbl: [INCOMPLETE][27] ([i915#155]) -> [PASS][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8430/shard-kbl3/igt@kms_hdr@bpc-switch-suspend.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17581/shard-kbl7/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: [FAIL][29] ([fdo#108145] / [i915#265]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8430/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17581/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [SKIP][31] ([fdo#109642] / [fdo#111068]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8430/shard-iclb3/igt@kms_psr2_su@frontbuffer.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17581/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@psr2_cursor_plane_onoff:
- shard-iclb: [SKIP][33] ([fdo#109441]) -> [PASS][34] +2 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8430/shard-iclb4/igt@kms_psr@psr2_cursor_plane_onoff.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17581/shard-iclb2/igt@kms_psr@psr2_cursor_plane_onoff.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-apl: [DMESG-WARN][35] ([i915#180]) -> [PASS][36] +2 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8430/shard-apl6/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17581/shard-apl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
#### Warnings ####
* igt@i915_pm_dc@dc6-psr:
- shard-tglb: [SKIP][37] ([i915#468]) -> [FAIL][38] ([i915#454])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8430/shard-tglb2/igt@i915_pm_dc@dc6-psr.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17581/shard-tglb3/igt@i915_pm_dc@dc6-psr.html
* igt@kms_content_protection@atomic:
- shard-apl: [FAIL][39] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][40] ([i915#1319])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8430/shard-apl1/igt@kms_content_protection@atomic.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17581/shard-apl1/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@atomic-dpms:
- shard-apl: [TIMEOUT][41] ([i915#1319]) -> [FAIL][42] ([fdo#110321] / [fdo#110336])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8430/shard-apl7/igt@kms_content_protection@atomic-dpms.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17581/shard-apl8/igt@kms_content_protection@atomic-dpms.html
* igt@kms_content_protection@lic:
- shard-kbl: [TIMEOUT][43] ([i915#1319]) -> [FAIL][44] ([fdo#110321] / [i915#93] / [i915#95])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8430/shard-kbl4/igt@kms_content_protection@lic.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17581/shard-kbl2/igt@kms_content_protection@lic.html
* igt@kms_content_protection@srm:
- shard-apl: [TIMEOUT][45] ([i915#1319]) -> [FAIL][46] ([fdo#110321])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8430/shard-apl1/igt@kms_content_protection@srm.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17581/shard-apl1/igt@kms_content_protection@srm.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321
[fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#34]: https://gitlab.freedesktop.org/drm/intel/issues/34
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468
[i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
[i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61
[i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
[i915#70]: https://gitlab.freedesktop.org/drm/intel/issues/70
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8430 -> Patchwork_17581
CI-20190529: 20190529
CI_DRM_8430: 2daa6f8cad645f49a898158190a20a893b4aabe3 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5632: e630cb8cd2ec01d6d5358eb2a3f6ea70498b8183 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17581: c9b00f24365bb8afb5caae9aa834993b996bc66a @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17581/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Intel-gfx] [PATCH v27 2/6] drm/i915: Separate icl and skl SAGV checking
2020-05-05 20:37 ` Lisovskiy, Stanislav
@ 2020-05-06 7:31 ` Ville Syrjälä
0 siblings, 0 replies; 24+ messages in thread
From: Ville Syrjälä @ 2020-05-06 7:31 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx
On Tue, May 05, 2020 at 11:37:23PM +0300, Lisovskiy, Stanislav wrote:
> On Tue, May 05, 2020 at 02:01:16PM +0300, Ville Syrjälä wrote:
> > On Tue, May 05, 2020 at 01:42:46PM +0300, Ville Syrjälä wrote:
> > > On Tue, May 05, 2020 at 01:22:43PM +0300, Stanislav Lisovskiy wrote:
> > > > Introduce platform dependent SAGV checking in
> > > > combination with bandwidth state pipe SAGV mask.
> > > >
> > > > v2, v3, v4, v5, v6: Fix rebase conflict
> > > >
> > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/intel_pm.c | 30 ++++++++++++++++++++++++++++--
> > > > 1 file changed, 28 insertions(+), 2 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > > index da567fac7c93..c7d726a656b2 100644
> > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > @@ -3853,6 +3853,24 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state
> > > > return true;
> > > > }
> > > >
> > > > +static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> > > > +{
> > > > + struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
> > > > + /*
> > > > + * SKL+ workaround: bspec recommends we disable SAGV when we have
> > > > + * more then one pipe enabled
> > > > + */
> > > > + if (hweight8(state->active_pipes) > 1)
> > > > + return false;
> > >
> > > That stuff should no longer be here since we now have it done properly
> > > in intel_can_eanble_sagv().
> > >
> > > > +
> > > > + return intel_crtc_can_enable_sagv(crtc_state);
> > > > +}
> > > > +
> > > > +static bool icl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> > > > +{
> > > > + return intel_crtc_can_enable_sagv(crtc_state);
> > > > +}
> > >
> > > This looks the wrong way around. IMO intel_crtc_can_enable_sagv()
> > > should rather call the skl vs. icl variants as needed. Although we
> > > don't yet have the icl variant so the oerdering of the patches is
> > > a bit weird.
> >
> > Do we even need an icl variant actually? Does it use the skl or tgl
> > way of checking for sagv yes vs. no?
>
> As I undestand icl implementation should be pretty much the same as
> skl, except that icl doesn't have this one active pipe limitation
> thing.
Right, and since that's now moved into intel_can_enable_sagv() we can
use skl_crtc_can_enable_sagv() for all pre-tgl.
>
>
> Stan
> >
> > >
> > > > +
> > > > bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
> > > > {
> > > > if (bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes))
> > > > @@ -3863,22 +3881,30 @@ bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
> > > >
> > > > static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > > > {
> > > > + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > > > int ret;
> > > > struct intel_crtc *crtc;
> > > > - struct intel_crtc_state *new_crtc_state;
> > > > + const struct intel_crtc_state *new_crtc_state;
> > > > struct intel_bw_state *new_bw_state = NULL;
> > > > const struct intel_bw_state *old_bw_state = NULL;
> > > > int i;
> > > >
> > > > for_each_new_intel_crtc_in_state(state, crtc,
> > > > new_crtc_state, i) {
> > > > + bool can_sagv;
> > > > +
> > > > new_bw_state = intel_atomic_get_bw_state(state);
> > > > if (IS_ERR(new_bw_state))
> > > > return PTR_ERR(new_bw_state);
> > > >
> > > > old_bw_state = intel_atomic_get_old_bw_state(state);
> > > >
> > > > - if (intel_crtc_can_enable_sagv(new_crtc_state))
> > > > + if (INTEL_GEN(dev_priv) >= 11)
> > > > + can_sagv = icl_crtc_can_enable_sagv(new_crtc_state);
> > > > + else
> > > > + can_sagv = skl_crtc_can_enable_sagv(new_crtc_state);
> > > > +
> > > > + if (can_sagv)
> > > > new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
> > > > else
> > > > new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
> > > > --
> > > > 2.24.1.485.gad05a3d8e5
> > >
> > > --
> > > Ville Syrjälä
> > > Intel
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
> > --
> > Ville Syrjälä
> > Intel
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Intel-gfx] [PATCH v27 2/6] drm/i915: Separate icl and skl SAGV checking
2020-05-05 10:42 ` Ville Syrjälä
2020-05-05 11:01 ` Ville Syrjälä
@ 2020-05-06 7:55 ` Lisovskiy, Stanislav
2020-05-06 8:08 ` Ville Syrjälä
1 sibling, 1 reply; 24+ messages in thread
From: Lisovskiy, Stanislav @ 2020-05-06 7:55 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Tue, May 05, 2020 at 01:42:46PM +0300, Ville Syrjälä wrote:
> On Tue, May 05, 2020 at 01:22:43PM +0300, Stanislav Lisovskiy wrote:
> > Introduce platform dependent SAGV checking in
> > combination with bandwidth state pipe SAGV mask.
> >
> > v2, v3, v4, v5, v6: Fix rebase conflict
> >
> > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_pm.c | 30 ++++++++++++++++++++++++++++--
> > 1 file changed, 28 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index da567fac7c93..c7d726a656b2 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3853,6 +3853,24 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state
> > return true;
> > }
> >
> > +static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> > +{
> > + struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
> > + /*
> > + * SKL+ workaround: bspec recommends we disable SAGV when we have
> > + * more then one pipe enabled
> > + */
> > + if (hweight8(state->active_pipes) > 1)
> > + return false;
>
> That stuff should no longer be here since we now have it done properly
> in intel_can_eanble_sagv().
>
> > +
> > + return intel_crtc_can_enable_sagv(crtc_state);
> > +}
> > +
> > +static bool icl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> > +{
> > + return intel_crtc_can_enable_sagv(crtc_state);
> > +}
>
> This looks the wrong way around. IMO intel_crtc_can_enable_sagv()
> should rather call the skl vs. icl variants as needed. Although we
> don't yet have the icl variant so the oerdering of the patches is
> a bit weird.
This is done so, because icl and skl checking share the same code
to check if SAGV can be enabled, except active_pipes > 1 thing.
So that icl and skl can share the same code avoiding duplicating,
i.e if I put code from intel_crtc_can_enable_sagv to
skl_crtc_can_enable_sagv, I will have to
1) either duplicate this code to icl_crtc_can_enable_sagv(if I add remaining active_pipes check to
skl)
2) use skl_crtc_can_enable_sagv from icl_crtc_can_enable_sagv,
but this active_pipes check will be still outside of this skl function,
which I don't find nice - to me the best way is to keep all skl
specific checks in a correspondent function.
So that is why I preferred to extract some common code to some separate
universal function which can be then used from both icl and skl functions:
from icl it is used "as is" and from skl it is intel_crtc_can_enable_sagv
+ this active_pipes check.
Currently anyway we of course have that active_pipes check in intel_can_enable_sagv
i.e already outside of skl_crtc_can_enable_sagv(where it should be imo),
so was your intention to leave it outside anyway?
Stan
>
> > +
> > bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
> > {
> > if (bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes))
> > @@ -3863,22 +3881,30 @@ bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
> >
> > static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > {
> > + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > int ret;
> > struct intel_crtc *crtc;
> > - struct intel_crtc_state *new_crtc_state;
> > + const struct intel_crtc_state *new_crtc_state;
> > struct intel_bw_state *new_bw_state = NULL;
> > const struct intel_bw_state *old_bw_state = NULL;
> > int i;
> >
> > for_each_new_intel_crtc_in_state(state, crtc,
> > new_crtc_state, i) {
> > + bool can_sagv;
> > +
> > new_bw_state = intel_atomic_get_bw_state(state);
> > if (IS_ERR(new_bw_state))
> > return PTR_ERR(new_bw_state);
> >
> > old_bw_state = intel_atomic_get_old_bw_state(state);
> >
> > - if (intel_crtc_can_enable_sagv(new_crtc_state))
> > + if (INTEL_GEN(dev_priv) >= 11)
> > + can_sagv = icl_crtc_can_enable_sagv(new_crtc_state);
> > + else
> > + can_sagv = skl_crtc_can_enable_sagv(new_crtc_state);
> > +
> > + if (can_sagv)
> > new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
> > else
> > new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
> > --
> > 2.24.1.485.gad05a3d8e5
>
> --
> Ville Syrjälä
> Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Intel-gfx] [PATCH v27 2/6] drm/i915: Separate icl and skl SAGV checking
2020-05-06 7:55 ` Lisovskiy, Stanislav
@ 2020-05-06 8:08 ` Ville Syrjälä
2020-05-06 8:43 ` Lisovskiy, Stanislav
0 siblings, 1 reply; 24+ messages in thread
From: Ville Syrjälä @ 2020-05-06 8:08 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx
On Wed, May 06, 2020 at 10:55:44AM +0300, Lisovskiy, Stanislav wrote:
> On Tue, May 05, 2020 at 01:42:46PM +0300, Ville Syrjälä wrote:
> > On Tue, May 05, 2020 at 01:22:43PM +0300, Stanislav Lisovskiy wrote:
> > > Introduce platform dependent SAGV checking in
> > > combination with bandwidth state pipe SAGV mask.
> > >
> > > v2, v3, v4, v5, v6: Fix rebase conflict
> > >
> > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/intel_pm.c | 30 ++++++++++++++++++++++++++++--
> > > 1 file changed, 28 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > index da567fac7c93..c7d726a656b2 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -3853,6 +3853,24 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state
> > > return true;
> > > }
> > >
> > > +static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> > > +{
> > > + struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
> > > + /*
> > > + * SKL+ workaround: bspec recommends we disable SAGV when we have
> > > + * more then one pipe enabled
> > > + */
> > > + if (hweight8(state->active_pipes) > 1)
> > > + return false;
> >
> > That stuff should no longer be here since we now have it done properly
> > in intel_can_eanble_sagv().
> >
> > > +
> > > + return intel_crtc_can_enable_sagv(crtc_state);
> > > +}
> > > +
> > > +static bool icl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> > > +{
> > > + return intel_crtc_can_enable_sagv(crtc_state);
> > > +}
> >
> > This looks the wrong way around. IMO intel_crtc_can_enable_sagv()
> > should rather call the skl vs. icl variants as needed. Although we
> > don't yet have the icl variant so the oerdering of the patches is
> > a bit weird.
>
> This is done so, because icl and skl checking share the same code
> to check if SAGV can be enabled, except active_pipes > 1 thing.
>
> So that icl and skl can share the same code avoiding duplicating,
> i.e if I put code from intel_crtc_can_enable_sagv to
> skl_crtc_can_enable_sagv, I will have to
> 1) either duplicate this code to icl_crtc_can_enable_sagv(if I add remaining active_pipes check to
> skl)
> 2) use skl_crtc_can_enable_sagv from icl_crtc_can_enable_sagv,
> but this active_pipes check will be still outside of this skl function,
> which I don't find nice - to me the best way is to keep all skl
> specific checks in a correspondent function.
>
> So that is why I preferred to extract some common code to some separate
> universal function which can be then used from both icl and skl functions:
> from icl it is used "as is" and from skl it is intel_crtc_can_enable_sagv
> + this active_pipes check.
>
> Currently anyway we of course have that active_pipes check in intel_can_enable_sagv
> i.e already outside of skl_crtc_can_enable_sagv(where it should be imo),
> so was your intention to leave it outside anyway?
My intention is that we eventually remove it altogeher. In the
meantime intel_can_enable_sagv() looks like the right place
for it.
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Intel-gfx] [PATCH v27 3/6] drm/i915: Add TGL+ SAGV support
2020-05-05 10:59 ` Ville Syrjälä
@ 2020-05-06 8:31 ` Lisovskiy, Stanislav
2020-05-06 9:12 ` Ville Syrjälä
0 siblings, 1 reply; 24+ messages in thread
From: Lisovskiy, Stanislav @ 2020-05-06 8:31 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Tue, May 05, 2020 at 01:59:11PM +0300, Ville Syrjälä wrote:
> On Tue, May 05, 2020 at 01:22:44PM +0300, Stanislav Lisovskiy wrote:
> > Starting from TGL we need to have a separate wm0
> > values for SAGV and non-SAGV which affects
> > how calculations are done.
> >
> > v2: Remove long lines
> > v3: Removed COLOR_PLANE enum references
> > v4, v5, v6: Fixed rebase conflict
> >
> > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 8 +-
> > .../drm/i915/display/intel_display_types.h | 3 +
> > drivers/gpu/drm/i915/intel_pm.c | 128 +++++++++++++++++-
> > 3 files changed, 130 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index fd6d63b03489..be5741cb7595 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -13961,7 +13961,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
> > /* Watermarks */
> > for (level = 0; level <= max_level; level++) {
> > if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> > - &sw_plane_wm->wm[level]))
> > + &sw_plane_wm->wm[level]) ||
> > + (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
> > + &sw_plane_wm->sagv_wm0)))
> > continue;
> >
> > drm_err(&dev_priv->drm,
> > @@ -14016,7 +14018,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
> > /* Watermarks */
> > for (level = 0; level <= max_level; level++) {
> > if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> > - &sw_plane_wm->wm[level]))
> > + &sw_plane_wm->wm[level]) ||
> > + (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
> > + &sw_plane_wm->sagv_wm0)))
> > continue;
> >
> > drm_err(&dev_priv->drm,
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 9488449e4b94..32cbbf7dddc6 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -688,11 +688,14 @@ struct skl_plane_wm {
> > struct skl_wm_level wm[8];
> > struct skl_wm_level uv_wm[8];
> > struct skl_wm_level trans_wm;
> > + struct skl_wm_level sagv_wm0;
> > + struct skl_wm_level uv_sagv_wm0;
>
> As mentioned before uv_wm is not a thing on icl+, so nuke this.
This is used in skl_plane_wm_level accessor, which is used for all
platforms, not just icl+. I remember we had agreed that for all platforms
before tgl I simply copy sagv_wm0 values from regular wm0, so that this
behaviour is unified(remember that your comment about memcpy which I changed
to assignment, see skl_compute_sagv_wm).
So if I remove it and this is called for pre-icl platforms, guess this would still
need wm_uv data?
Stan
>
> > bool is_planar;
> > };
> >
> > struct skl_pipe_wm {
> > struct skl_plane_wm planes[I915_MAX_PLANES];
> > + bool can_sagv;
>
> I would call it use_sagv_wm or somesuch to make it actually clear what
> it does.
>
> > };
> >
> > enum vlv_wm_level {
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index c7d726a656b2..1b9925b6672c 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3871,6 +3871,9 @@ static bool icl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> > return intel_crtc_can_enable_sagv(crtc_state);
> > }
> >
> > +static bool
> > +tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state);
> > +
> > bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
> > {
> > if (bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes))
> > @@ -3884,7 +3887,7 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > int ret;
> > struct intel_crtc *crtc;
> > - const struct intel_crtc_state *new_crtc_state;
> > + struct intel_crtc_state *new_crtc_state;
> > struct intel_bw_state *new_bw_state = NULL;
> > const struct intel_bw_state *old_bw_state = NULL;
> > int i;
> > @@ -3899,7 +3902,9 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> >
> > old_bw_state = intel_atomic_get_old_bw_state(state);
> >
> > - if (INTEL_GEN(dev_priv) >= 11)
> > + if (INTEL_GEN(dev_priv) >= 12)
> > + can_sagv = tgl_crtc_can_enable_sagv(new_crtc_state);
> > + else if (INTEL_GEN(dev_priv) >= 11)
> > can_sagv = icl_crtc_can_enable_sagv(new_crtc_state);
> > else
> > can_sagv = skl_crtc_can_enable_sagv(new_crtc_state);
> > @@ -3921,6 +3926,24 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > return ret;
> > }
> >
> > + for_each_new_intel_crtc_in_state(state, crtc,
> > + new_crtc_state, i) {
> > + struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal;
> > +
> > + /*
> > + * Due to drm limitation at commit state, when
> > + * changes are written the whole atomic state is
> > + * zeroed away => which prevents from using it,
> > + * so just sticking it into pipe wm state for
> > + * keeping it simple - anyway this is related to wm.
> > + * Proper way in ideal universe would be of course not
> > + * to lose parent atomic state object from child crtc_state,
> > + * and stick to OOP programming principles, which had been
> > + * scientifically proven to work.
>
> Seems like random ramblings. I'd just nuke the comment.
>
> > + */
> > + pipe_wm->can_sagv = intel_can_enable_sagv(new_bw_state);
> > + }
> > +
> > if (intel_can_enable_sagv(new_bw_state) != intel_can_enable_sagv(old_bw_state)) {
> > ret = intel_atomic_serialize_global_state(&new_bw_state->base);
> > if (ret)
> > @@ -4664,12 +4687,39 @@ skl_plane_wm_level(const struct intel_crtc_state *crtc_state,
> > int level,
> > int color_plane)
> > {
> > - const struct skl_plane_wm *wm =
> > - &crtc_state->wm.skl.optimal.planes[plane_id];
> > + const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
> > + const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
> > +
> > + if (!level) {
> > + if (pipe_wm->can_sagv)
> > + return color_plane == 0 ? &wm->sagv_wm0 : &wm->uv_sagv_wm0;
> > + }
> >
> > return color_plane == 0 ? &wm->wm[level] : &wm->uv_wm[level];
> > }
> >
> > +static bool
> > +tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> > +{
> > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > + enum plane_id plane_id;
> > +
> > + if (!crtc_state->hw.active)
> > + return true;
> > +
> > + for_each_plane_id_on_crtc(crtc, plane_id) {
> > + const struct skl_ddb_entry *plane_alloc =
> > + &crtc_state->wm.skl.plane_ddb_y[plane_id];
> > + const struct skl_plane_wm *wm =
> > + &crtc_state->wm.skl.optimal.planes[plane_id];
> > +
> > + if (skl_ddb_entry_size(plane_alloc) < wm->sagv_wm0.min_ddb_alloc)
> > + return false;
> > + }
> > +
> > + return true;
> > +}
> > +
> > static int
> > skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
> > {
> > @@ -5251,10 +5301,17 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
> > static void
> > skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
> > const struct skl_wm_params *wm_params,
> > - struct skl_wm_level *levels)
> > + struct skl_plane_wm *plane_wm,
> > + int color_plane)
> > {
> > struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> > int level, max_level = ilk_wm_max_level(dev_priv);
> > + /*
> > + * Check which kind of plane is it and based on that calculate
> > + * correspondent WM levels.
> > + */
> > + struct skl_wm_level *levels = color_plane == 1 ?
> > + plane_wm->uv_wm : plane_wm->wm;
> > struct skl_wm_level *result_prev = &levels[0];
> >
> > for (level = 0; level <= max_level; level++) {
> > @@ -5268,6 +5325,40 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
> > }
> > }
> >
> > +static void skl_compute_sagv_wm(const struct intel_crtc_state *crtc_state,
> > + const struct skl_wm_params *wm_params,
> > + struct skl_plane_wm *plane_wm,
> > + int color_plane)
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> > + struct skl_wm_level *sagv_wm = color_plane == 1 ?
> > + &plane_wm->uv_sagv_wm0 : &plane_wm->sagv_wm0;
> > + struct skl_wm_level *levels = color_plane == 1 ?
> > + plane_wm->uv_wm : plane_wm->wm;
> > +
> > + /*
> > + * For Gen12 if it is an L0 we need to also
> > + * consider sagv_block_time when calculating
> > + * L0 watermark - we will need that when making
> > + * a decision whether enable SAGV or not.
> > + * For older gens we agreed to copy L0 value for
> > + * compatibility.
> > + */
> > + if ((INTEL_GEN(dev_priv) >= 12)) {
> > + u32 latency = dev_priv->wm.skl_latency[0];
> > +
> > + latency += dev_priv->sagv_block_time_us;
> > + skl_compute_plane_wm(crtc_state, 0, latency,
> > + wm_params, &levels[0],
> > + sagv_wm);
> > + DRM_DEBUG_KMS("%d L0 blocks required for SAGV vs %d for non-SAGV\n",
> > + sagv_wm->min_ddb_alloc, levels[0].min_ddb_alloc);
> > + } else {
> > + /* Since all members are POD */
> > + *sagv_wm = levels[0];
> > + }
> > +}
> > +
> > static void skl_compute_transition_wm(const struct intel_crtc_state *crtc_state,
> > const struct skl_wm_params *wp,
> > struct skl_plane_wm *wm)
> > @@ -5344,7 +5435,8 @@ static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
> > if (ret)
> > return ret;
> >
> > - skl_compute_wm_levels(crtc_state, &wm_params, wm->wm);
> > + skl_compute_wm_levels(crtc_state, &wm_params, wm, 0);
> > + skl_compute_sagv_wm(crtc_state, &wm_params, wm, 0);
> > skl_compute_transition_wm(crtc_state, &wm_params, wm);
> >
> > return 0;
> > @@ -5366,7 +5458,8 @@ static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
> > if (ret)
> > return ret;
> >
> > - skl_compute_wm_levels(crtc_state, &wm_params, wm->uv_wm);
> > + skl_compute_wm_levels(crtc_state, &wm_params, wm, 1);
> > + skl_compute_sagv_wm(crtc_state, &wm_params, wm, 1);
> >
> > return 0;
> > }
> > @@ -5751,6 +5844,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
> > enast(new_wm->wm[7].ignore_lines), new_wm->wm[7].plane_res_l,
> > enast(new_wm->trans_wm.ignore_lines), new_wm->trans_wm.plane_res_l);
> >
> > + drm_dbg_kms(&dev_priv->drm,
> > + "[PLANE:%d:%s] sagv wm0 lines %4d -> %4d\n",
> > + plane->base.base.id, plane->base.name,
> > + old_wm->sagv_wm0.plane_res_l,
> > + new_wm->sagv_wm0.plane_res_l);
> > +
> > drm_dbg_kms(&dev_priv->drm,
> > "[PLANE:%d:%s] blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
> > " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
> > @@ -5766,6 +5865,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
> > new_wm->wm[6].plane_res_b, new_wm->wm[7].plane_res_b,
> > new_wm->trans_wm.plane_res_b);
> >
> > + drm_dbg_kms(&dev_priv->drm,
> > + "[PLANE:%d:%s] sagv wm0 blocks %4d -> %4d\n",
> > + plane->base.base.id, plane->base.name,
> > + old_wm->sagv_wm0.plane_res_b,
> > + new_wm->sagv_wm0.plane_res_b);
> > +
> > drm_dbg_kms(&dev_priv->drm,
> > "[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
> > " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
> > @@ -5780,6 +5885,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
> > new_wm->wm[4].min_ddb_alloc, new_wm->wm[5].min_ddb_alloc,
> > new_wm->wm[6].min_ddb_alloc, new_wm->wm[7].min_ddb_alloc,
> > new_wm->trans_wm.min_ddb_alloc);
> > +
> > + drm_dbg_kms(&dev_priv->drm,
> > + "[PLANE:%d:%s] sagv wm0 min ddb %4d -> %4d\n",
> > + plane->base.base.id, plane->base.name,
> > + old_wm->sagv_wm0.min_ddb_alloc,
> > + new_wm->sagv_wm0.min_ddb_alloc);
> > }
> > }
> > }
> > @@ -6072,6 +6183,9 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
> > skl_wm_level_from_reg_val(val, &wm->wm[level]);
> > }
> >
> > + memcpy(&wm->sagv_wm0, &wm->wm[0],
> > + sizeof(struct skl_wm_level));
> > +
> > if (plane_id != PLANE_CURSOR)
> > val = I915_READ(PLANE_WM_TRANS(pipe, plane_id));
> > else
> > --
> > 2.24.1.485.gad05a3d8e5
>
> --
> Ville Syrjälä
> Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Intel-gfx] [PATCH v27 2/6] drm/i915: Separate icl and skl SAGV checking
2020-05-06 8:08 ` Ville Syrjälä
@ 2020-05-06 8:43 ` Lisovskiy, Stanislav
2020-05-06 9:15 ` Ville Syrjälä
0 siblings, 1 reply; 24+ messages in thread
From: Lisovskiy, Stanislav @ 2020-05-06 8:43 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Wed, May 06, 2020 at 11:08:34AM +0300, Ville Syrjälä wrote:
> On Wed, May 06, 2020 at 10:55:44AM +0300, Lisovskiy, Stanislav wrote:
> > On Tue, May 05, 2020 at 01:42:46PM +0300, Ville Syrjälä wrote:
> > > On Tue, May 05, 2020 at 01:22:43PM +0300, Stanislav Lisovskiy wrote:
> > > > Introduce platform dependent SAGV checking in
> > > > combination with bandwidth state pipe SAGV mask.
> > > >
> > > > v2, v3, v4, v5, v6: Fix rebase conflict
> > > >
> > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/intel_pm.c | 30 ++++++++++++++++++++++++++++--
> > > > 1 file changed, 28 insertions(+), 2 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > > index da567fac7c93..c7d726a656b2 100644
> > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > @@ -3853,6 +3853,24 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state
> > > > return true;
> > > > }
> > > >
> > > > +static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> > > > +{
> > > > + struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
> > > > + /*
> > > > + * SKL+ workaround: bspec recommends we disable SAGV when we have
> > > > + * more then one pipe enabled
> > > > + */
> > > > + if (hweight8(state->active_pipes) > 1)
> > > > + return false;
> > >
> > > That stuff should no longer be here since we now have it done properly
> > > in intel_can_eanble_sagv().
> > >
> > > > +
> > > > + return intel_crtc_can_enable_sagv(crtc_state);
> > > > +}
> > > > +
> > > > +static bool icl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> > > > +{
> > > > + return intel_crtc_can_enable_sagv(crtc_state);
> > > > +}
> > >
> > > This looks the wrong way around. IMO intel_crtc_can_enable_sagv()
> > > should rather call the skl vs. icl variants as needed. Although we
> > > don't yet have the icl variant so the oerdering of the patches is
> > > a bit weird.
> >
> > This is done so, because icl and skl checking share the same code
> > to check if SAGV can be enabled, except active_pipes > 1 thing.
> >
> > So that icl and skl can share the same code avoiding duplicating,
> > i.e if I put code from intel_crtc_can_enable_sagv to
> > skl_crtc_can_enable_sagv, I will have to
> > 1) either duplicate this code to icl_crtc_can_enable_sagv(if I add remaining active_pipes check to
> > skl)
> > 2) use skl_crtc_can_enable_sagv from icl_crtc_can_enable_sagv,
> > but this active_pipes check will be still outside of this skl function,
> > which I don't find nice - to me the best way is to keep all skl
> > specific checks in a correspondent function.
> >
> > So that is why I preferred to extract some common code to some separate
> > universal function which can be then used from both icl and skl functions:
> > from icl it is used "as is" and from skl it is intel_crtc_can_enable_sagv
> > + this active_pipes check.
> >
> > Currently anyway we of course have that active_pipes check in intel_can_enable_sagv
> > i.e already outside of skl_crtc_can_enable_sagv(where it should be imo),
> > so was your intention to leave it outside anyway?
>
> My intention is that we eventually remove it altogeher. In the
> meantime intel_can_enable_sagv() looks like the right place
> for it.
Wow, you were really fast replying :) Ok, then I just leave skl_crtc_can_enable_sagv,
use it for icl and active_pipes check stays in intel_can_enable_sagv, however probably
it will now need somekind of INTEL_GEN < 11 check, I guess.
Stan
>
> --
> Ville Syrjälä
> Intel
_______________________________________________
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^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Intel-gfx] [PATCH v27 3/6] drm/i915: Add TGL+ SAGV support
2020-05-06 8:31 ` Lisovskiy, Stanislav
@ 2020-05-06 9:12 ` Ville Syrjälä
2020-05-06 12:12 ` Lisovskiy, Stanislav
0 siblings, 1 reply; 24+ messages in thread
From: Ville Syrjälä @ 2020-05-06 9:12 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx
On Wed, May 06, 2020 at 11:31:05AM +0300, Lisovskiy, Stanislav wrote:
> On Tue, May 05, 2020 at 01:59:11PM +0300, Ville Syrjälä wrote:
> > On Tue, May 05, 2020 at 01:22:44PM +0300, Stanislav Lisovskiy wrote:
> > > Starting from TGL we need to have a separate wm0
> > > values for SAGV and non-SAGV which affects
> > > how calculations are done.
> > >
> > > v2: Remove long lines
> > > v3: Removed COLOR_PLANE enum references
> > > v4, v5, v6: Fixed rebase conflict
> > >
> > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_display.c | 8 +-
> > > .../drm/i915/display/intel_display_types.h | 3 +
> > > drivers/gpu/drm/i915/intel_pm.c | 128 +++++++++++++++++-
> > > 3 files changed, 130 insertions(+), 9 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > index fd6d63b03489..be5741cb7595 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -13961,7 +13961,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
> > > /* Watermarks */
> > > for (level = 0; level <= max_level; level++) {
> > > if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > - &sw_plane_wm->wm[level]))
> > > + &sw_plane_wm->wm[level]) ||
> > > + (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > + &sw_plane_wm->sagv_wm0)))
> > > continue;
> > >
> > > drm_err(&dev_priv->drm,
> > > @@ -14016,7 +14018,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
> > > /* Watermarks */
> > > for (level = 0; level <= max_level; level++) {
> > > if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > - &sw_plane_wm->wm[level]))
> > > + &sw_plane_wm->wm[level]) ||
> > > + (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > + &sw_plane_wm->sagv_wm0)))
> > > continue;
> > >
> > > drm_err(&dev_priv->drm,
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > index 9488449e4b94..32cbbf7dddc6 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > @@ -688,11 +688,14 @@ struct skl_plane_wm {
> > > struct skl_wm_level wm[8];
> > > struct skl_wm_level uv_wm[8];
> > > struct skl_wm_level trans_wm;
> > > + struct skl_wm_level sagv_wm0;
> > > + struct skl_wm_level uv_sagv_wm0;
> >
> > As mentioned before uv_wm is not a thing on icl+, so nuke this.
>
> This is used in skl_plane_wm_level accessor, which is used for all
> platforms, not just icl+. I remember we had agreed that for all platforms
> before tgl I simply copy sagv_wm0 values from regular wm0, so that this
> behaviour is unified(remember that your comment about memcpy which I changed
> to assignment, see skl_compute_sagv_wm).
I think having that duplicated is just making things more confusing.
Also uv_wm is never used by the hardware even on pre-icl, so having
the accessor thing use it for the hw programming just doesn't make
any sense.
For the compute side I think all we should really need is
something like:
tgl_compute_sagv_wm()
{
skl_compute_wm_level(sagv_wm0, latency + whatever);
}
skl_build_plane_wm_single()
{
...
skl_compute_transition_wm();
+ if (gen >= 12)
+ tgl_compute_sagv_wm();
}
And for the progamming side we should just pick the right
wm0 based on the crtc_state->use_sagv_wm or whatever flag.
>
> So if I remove it and this is called for pre-icl platforms, guess this would still
> need wm_uv data?
>
>
> Stan
>
> >
> > > bool is_planar;
> > > };
> > >
> > > struct skl_pipe_wm {
> > > struct skl_plane_wm planes[I915_MAX_PLANES];
> > > + bool can_sagv;
> >
> > I would call it use_sagv_wm or somesuch to make it actually clear what
> > it does.
> >
> > > };
> > >
> > > enum vlv_wm_level {
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > index c7d726a656b2..1b9925b6672c 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -3871,6 +3871,9 @@ static bool icl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> > > return intel_crtc_can_enable_sagv(crtc_state);
> > > }
> > >
> > > +static bool
> > > +tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state);
> > > +
> > > bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
> > > {
> > > if (bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes))
> > > @@ -3884,7 +3887,7 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > > struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > > int ret;
> > > struct intel_crtc *crtc;
> > > - const struct intel_crtc_state *new_crtc_state;
> > > + struct intel_crtc_state *new_crtc_state;
> > > struct intel_bw_state *new_bw_state = NULL;
> > > const struct intel_bw_state *old_bw_state = NULL;
> > > int i;
> > > @@ -3899,7 +3902,9 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > >
> > > old_bw_state = intel_atomic_get_old_bw_state(state);
> > >
> > > - if (INTEL_GEN(dev_priv) >= 11)
> > > + if (INTEL_GEN(dev_priv) >= 12)
> > > + can_sagv = tgl_crtc_can_enable_sagv(new_crtc_state);
> > > + else if (INTEL_GEN(dev_priv) >= 11)
> > > can_sagv = icl_crtc_can_enable_sagv(new_crtc_state);
> > > else
> > > can_sagv = skl_crtc_can_enable_sagv(new_crtc_state);
> > > @@ -3921,6 +3926,24 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > > return ret;
> > > }
> > >
> > > + for_each_new_intel_crtc_in_state(state, crtc,
> > > + new_crtc_state, i) {
> > > + struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal;
> > > +
> > > + /*
> > > + * Due to drm limitation at commit state, when
> > > + * changes are written the whole atomic state is
> > > + * zeroed away => which prevents from using it,
> > > + * so just sticking it into pipe wm state for
> > > + * keeping it simple - anyway this is related to wm.
> > > + * Proper way in ideal universe would be of course not
> > > + * to lose parent atomic state object from child crtc_state,
> > > + * and stick to OOP programming principles, which had been
> > > + * scientifically proven to work.
> >
> > Seems like random ramblings. I'd just nuke the comment.
> >
> > > + */
> > > + pipe_wm->can_sagv = intel_can_enable_sagv(new_bw_state);
> > > + }
> > > +
> > > if (intel_can_enable_sagv(new_bw_state) != intel_can_enable_sagv(old_bw_state)) {
> > > ret = intel_atomic_serialize_global_state(&new_bw_state->base);
> > > if (ret)
> > > @@ -4664,12 +4687,39 @@ skl_plane_wm_level(const struct intel_crtc_state *crtc_state,
> > > int level,
> > > int color_plane)
> > > {
> > > - const struct skl_plane_wm *wm =
> > > - &crtc_state->wm.skl.optimal.planes[plane_id];
> > > + const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
> > > + const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
> > > +
> > > + if (!level) {
> > > + if (pipe_wm->can_sagv)
> > > + return color_plane == 0 ? &wm->sagv_wm0 : &wm->uv_sagv_wm0;
> > > + }
> > >
> > > return color_plane == 0 ? &wm->wm[level] : &wm->uv_wm[level];
> > > }
> > >
> > > +static bool
> > > +tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> > > +{
> > > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > > + enum plane_id plane_id;
> > > +
> > > + if (!crtc_state->hw.active)
> > > + return true;
> > > +
> > > + for_each_plane_id_on_crtc(crtc, plane_id) {
> > > + const struct skl_ddb_entry *plane_alloc =
> > > + &crtc_state->wm.skl.plane_ddb_y[plane_id];
> > > + const struct skl_plane_wm *wm =
> > > + &crtc_state->wm.skl.optimal.planes[plane_id];
> > > +
> > > + if (skl_ddb_entry_size(plane_alloc) < wm->sagv_wm0.min_ddb_alloc)
> > > + return false;
> > > + }
> > > +
> > > + return true;
> > > +}
> > > +
> > > static int
> > > skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
> > > {
> > > @@ -5251,10 +5301,17 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
> > > static void
> > > skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
> > > const struct skl_wm_params *wm_params,
> > > - struct skl_wm_level *levels)
> > > + struct skl_plane_wm *plane_wm,
> > > + int color_plane)
> > > {
> > > struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> > > int level, max_level = ilk_wm_max_level(dev_priv);
> > > + /*
> > > + * Check which kind of plane is it and based on that calculate
> > > + * correspondent WM levels.
> > > + */
> > > + struct skl_wm_level *levels = color_plane == 1 ?
> > > + plane_wm->uv_wm : plane_wm->wm;
> > > struct skl_wm_level *result_prev = &levels[0];
> > >
> > > for (level = 0; level <= max_level; level++) {
> > > @@ -5268,6 +5325,40 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
> > > }
> > > }
> > >
> > > +static void skl_compute_sagv_wm(const struct intel_crtc_state *crtc_state,
> > > + const struct skl_wm_params *wm_params,
> > > + struct skl_plane_wm *plane_wm,
> > > + int color_plane)
> > > +{
> > > + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> > > + struct skl_wm_level *sagv_wm = color_plane == 1 ?
> > > + &plane_wm->uv_sagv_wm0 : &plane_wm->sagv_wm0;
> > > + struct skl_wm_level *levels = color_plane == 1 ?
> > > + plane_wm->uv_wm : plane_wm->wm;
> > > +
> > > + /*
> > > + * For Gen12 if it is an L0 we need to also
> > > + * consider sagv_block_time when calculating
> > > + * L0 watermark - we will need that when making
> > > + * a decision whether enable SAGV or not.
> > > + * For older gens we agreed to copy L0 value for
> > > + * compatibility.
> > > + */
> > > + if ((INTEL_GEN(dev_priv) >= 12)) {
> > > + u32 latency = dev_priv->wm.skl_latency[0];
> > > +
> > > + latency += dev_priv->sagv_block_time_us;
> > > + skl_compute_plane_wm(crtc_state, 0, latency,
> > > + wm_params, &levels[0],
> > > + sagv_wm);
> > > + DRM_DEBUG_KMS("%d L0 blocks required for SAGV vs %d for non-SAGV\n",
> > > + sagv_wm->min_ddb_alloc, levels[0].min_ddb_alloc);
> > > + } else {
> > > + /* Since all members are POD */
> > > + *sagv_wm = levels[0];
> > > + }
> > > +}
> > > +
> > > static void skl_compute_transition_wm(const struct intel_crtc_state *crtc_state,
> > > const struct skl_wm_params *wp,
> > > struct skl_plane_wm *wm)
> > > @@ -5344,7 +5435,8 @@ static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
> > > if (ret)
> > > return ret;
> > >
> > > - skl_compute_wm_levels(crtc_state, &wm_params, wm->wm);
> > > + skl_compute_wm_levels(crtc_state, &wm_params, wm, 0);
> > > + skl_compute_sagv_wm(crtc_state, &wm_params, wm, 0);
> > > skl_compute_transition_wm(crtc_state, &wm_params, wm);
> > >
> > > return 0;
> > > @@ -5366,7 +5458,8 @@ static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
> > > if (ret)
> > > return ret;
> > >
> > > - skl_compute_wm_levels(crtc_state, &wm_params, wm->uv_wm);
> > > + skl_compute_wm_levels(crtc_state, &wm_params, wm, 1);
> > > + skl_compute_sagv_wm(crtc_state, &wm_params, wm, 1);
> > >
> > > return 0;
> > > }
> > > @@ -5751,6 +5844,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
> > > enast(new_wm->wm[7].ignore_lines), new_wm->wm[7].plane_res_l,
> > > enast(new_wm->trans_wm.ignore_lines), new_wm->trans_wm.plane_res_l);
> > >
> > > + drm_dbg_kms(&dev_priv->drm,
> > > + "[PLANE:%d:%s] sagv wm0 lines %4d -> %4d\n",
> > > + plane->base.base.id, plane->base.name,
> > > + old_wm->sagv_wm0.plane_res_l,
> > > + new_wm->sagv_wm0.plane_res_l);
> > > +
> > > drm_dbg_kms(&dev_priv->drm,
> > > "[PLANE:%d:%s] blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
> > > " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
> > > @@ -5766,6 +5865,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
> > > new_wm->wm[6].plane_res_b, new_wm->wm[7].plane_res_b,
> > > new_wm->trans_wm.plane_res_b);
> > >
> > > + drm_dbg_kms(&dev_priv->drm,
> > > + "[PLANE:%d:%s] sagv wm0 blocks %4d -> %4d\n",
> > > + plane->base.base.id, plane->base.name,
> > > + old_wm->sagv_wm0.plane_res_b,
> > > + new_wm->sagv_wm0.plane_res_b);
> > > +
> > > drm_dbg_kms(&dev_priv->drm,
> > > "[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
> > > " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
> > > @@ -5780,6 +5885,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
> > > new_wm->wm[4].min_ddb_alloc, new_wm->wm[5].min_ddb_alloc,
> > > new_wm->wm[6].min_ddb_alloc, new_wm->wm[7].min_ddb_alloc,
> > > new_wm->trans_wm.min_ddb_alloc);
> > > +
> > > + drm_dbg_kms(&dev_priv->drm,
> > > + "[PLANE:%d:%s] sagv wm0 min ddb %4d -> %4d\n",
> > > + plane->base.base.id, plane->base.name,
> > > + old_wm->sagv_wm0.min_ddb_alloc,
> > > + new_wm->sagv_wm0.min_ddb_alloc);
> > > }
> > > }
> > > }
> > > @@ -6072,6 +6183,9 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
> > > skl_wm_level_from_reg_val(val, &wm->wm[level]);
> > > }
> > >
> > > + memcpy(&wm->sagv_wm0, &wm->wm[0],
> > > + sizeof(struct skl_wm_level));
> > > +
> > > if (plane_id != PLANE_CURSOR)
> > > val = I915_READ(PLANE_WM_TRANS(pipe, plane_id));
> > > else
> > > --
> > > 2.24.1.485.gad05a3d8e5
> >
> > --
> > Ville Syrjälä
> > Intel
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Intel-gfx] [PATCH v27 2/6] drm/i915: Separate icl and skl SAGV checking
2020-05-06 8:43 ` Lisovskiy, Stanislav
@ 2020-05-06 9:15 ` Ville Syrjälä
0 siblings, 0 replies; 24+ messages in thread
From: Ville Syrjälä @ 2020-05-06 9:15 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx
On Wed, May 06, 2020 at 11:43:30AM +0300, Lisovskiy, Stanislav wrote:
> On Wed, May 06, 2020 at 11:08:34AM +0300, Ville Syrjälä wrote:
> > On Wed, May 06, 2020 at 10:55:44AM +0300, Lisovskiy, Stanislav wrote:
> > > On Tue, May 05, 2020 at 01:42:46PM +0300, Ville Syrjälä wrote:
> > > > On Tue, May 05, 2020 at 01:22:43PM +0300, Stanislav Lisovskiy wrote:
> > > > > Introduce platform dependent SAGV checking in
> > > > > combination with bandwidth state pipe SAGV mask.
> > > > >
> > > > > v2, v3, v4, v5, v6: Fix rebase conflict
> > > > >
> > > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > > > ---
> > > > > drivers/gpu/drm/i915/intel_pm.c | 30 ++++++++++++++++++++++++++++--
> > > > > 1 file changed, 28 insertions(+), 2 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > > > index da567fac7c93..c7d726a656b2 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > > @@ -3853,6 +3853,24 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state
> > > > > return true;
> > > > > }
> > > > >
> > > > > +static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> > > > > +{
> > > > > + struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
> > > > > + /*
> > > > > + * SKL+ workaround: bspec recommends we disable SAGV when we have
> > > > > + * more then one pipe enabled
> > > > > + */
> > > > > + if (hweight8(state->active_pipes) > 1)
> > > > > + return false;
> > > >
> > > > That stuff should no longer be here since we now have it done properly
> > > > in intel_can_eanble_sagv().
> > > >
> > > > > +
> > > > > + return intel_crtc_can_enable_sagv(crtc_state);
> > > > > +}
> > > > > +
> > > > > +static bool icl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> > > > > +{
> > > > > + return intel_crtc_can_enable_sagv(crtc_state);
> > > > > +}
> > > >
> > > > This looks the wrong way around. IMO intel_crtc_can_enable_sagv()
> > > > should rather call the skl vs. icl variants as needed. Although we
> > > > don't yet have the icl variant so the oerdering of the patches is
> > > > a bit weird.
> > >
> > > This is done so, because icl and skl checking share the same code
> > > to check if SAGV can be enabled, except active_pipes > 1 thing.
> > >
> > > So that icl and skl can share the same code avoiding duplicating,
> > > i.e if I put code from intel_crtc_can_enable_sagv to
> > > skl_crtc_can_enable_sagv, I will have to
> > > 1) either duplicate this code to icl_crtc_can_enable_sagv(if I add remaining active_pipes check to
> > > skl)
> > > 2) use skl_crtc_can_enable_sagv from icl_crtc_can_enable_sagv,
> > > but this active_pipes check will be still outside of this skl function,
> > > which I don't find nice - to me the best way is to keep all skl
> > > specific checks in a correspondent function.
> > >
> > > So that is why I preferred to extract some common code to some separate
> > > universal function which can be then used from both icl and skl functions:
> > > from icl it is used "as is" and from skl it is intel_crtc_can_enable_sagv
> > > + this active_pipes check.
> > >
> > > Currently anyway we of course have that active_pipes check in intel_can_enable_sagv
> > > i.e already outside of skl_crtc_can_enable_sagv(where it should be imo),
> > > so was your intention to leave it outside anyway?
> >
> > My intention is that we eventually remove it altogeher. In the
> > meantime intel_can_enable_sagv() looks like the right place
> > for it.
>
> Wow, you were really fast replying :) Ok, then I just leave skl_crtc_can_enable_sagv,
> use it for icl and active_pipes check stays in intel_can_enable_sagv, however probably
> it will now need somekind of INTEL_GEN < 11 check, I guess.
If we want to enable sagv for multi-pipe on just icl+ first, yes.
I guess we can do that. I suggest making that a standalone patch
so we can easily revert it if things blow up. We can then let that
bake for a while and follow up later with nuking the single pipe
restriction for all platforms.
--
Ville Syrjälä
Intel
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Intel-gfx] [PATCH v27 3/6] drm/i915: Add TGL+ SAGV support
2020-05-06 9:12 ` Ville Syrjälä
@ 2020-05-06 12:12 ` Lisovskiy, Stanislav
2020-05-06 13:16 ` Ville Syrjälä
0 siblings, 1 reply; 24+ messages in thread
From: Lisovskiy, Stanislav @ 2020-05-06 12:12 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Wed, May 06, 2020 at 12:12:28PM +0300, Ville Syrjälä wrote:
> On Wed, May 06, 2020 at 11:31:05AM +0300, Lisovskiy, Stanislav wrote:
> > On Tue, May 05, 2020 at 01:59:11PM +0300, Ville Syrjälä wrote:
> > > On Tue, May 05, 2020 at 01:22:44PM +0300, Stanislav Lisovskiy wrote:
> > > > Starting from TGL we need to have a separate wm0
> > > > values for SAGV and non-SAGV which affects
> > > > how calculations are done.
> > > >
> > > > v2: Remove long lines
> > > > v3: Removed COLOR_PLANE enum references
> > > > v4, v5, v6: Fixed rebase conflict
> > > >
> > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_display.c | 8 +-
> > > > .../drm/i915/display/intel_display_types.h | 3 +
> > > > drivers/gpu/drm/i915/intel_pm.c | 128 +++++++++++++++++-
> > > > 3 files changed, 130 insertions(+), 9 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > > index fd6d63b03489..be5741cb7595 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > @@ -13961,7 +13961,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
> > > > /* Watermarks */
> > > > for (level = 0; level <= max_level; level++) {
> > > > if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > > - &sw_plane_wm->wm[level]))
> > > > + &sw_plane_wm->wm[level]) ||
> > > > + (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > > + &sw_plane_wm->sagv_wm0)))
> > > > continue;
> > > >
> > > > drm_err(&dev_priv->drm,
> > > > @@ -14016,7 +14018,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
> > > > /* Watermarks */
> > > > for (level = 0; level <= max_level; level++) {
> > > > if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > > - &sw_plane_wm->wm[level]))
> > > > + &sw_plane_wm->wm[level]) ||
> > > > + (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > > + &sw_plane_wm->sagv_wm0)))
> > > > continue;
> > > >
> > > > drm_err(&dev_priv->drm,
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > index 9488449e4b94..32cbbf7dddc6 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > @@ -688,11 +688,14 @@ struct skl_plane_wm {
> > > > struct skl_wm_level wm[8];
> > > > struct skl_wm_level uv_wm[8];
> > > > struct skl_wm_level trans_wm;
> > > > + struct skl_wm_level sagv_wm0;
> > > > + struct skl_wm_level uv_sagv_wm0;
> > >
> > > As mentioned before uv_wm is not a thing on icl+, so nuke this.
> >
> > This is used in skl_plane_wm_level accessor, which is used for all
> > platforms, not just icl+. I remember we had agreed that for all platforms
> > before tgl I simply copy sagv_wm0 values from regular wm0, so that this
> > behaviour is unified(remember that your comment about memcpy which I changed
> > to assignment, see skl_compute_sagv_wm).
>
> I think having that duplicated is just making things more confusing.
> Also uv_wm is never used by the hardware even on pre-icl, so having
> the accessor thing use it for the hw programming just doesn't make
> any sense.
Problem is that we use it in skl_allocate_pipe_ddb in a few places:
blocks += wm_level->min_ddb_alloc;
blocks += wm_uv_level->min_ddb_alloc;
then those plane data rates:
rate = plane_data_rate[plane_id];
extra = min_t(u16, alloc_size,
DIV64_U64_ROUND_UP(alloc_size * rate, total_data_rate));
total[plane_id] = wm_level->min_ddb_alloc + extra;
alloc_size -= extra;
total_data_rate -= rate;
if (total_data_rate == 0)
break;
rate = uv_plane_data_rate[plane_id];
extra = min_t(u16, alloc_size,
DIV64_U64_ROUND_UP(alloc_size * rate, total_data_rate));
uv_total[plane_id] = wm_uv_level->min_ddb_alloc + extra;
So if I remove this wm_uv from skl_plane_wm_level accessor,
the logic in skl_allocate_pipe_ddb will obvisouly change?
Stan
>
> For the compute side I think all we should really need is
> something like:
>
> tgl_compute_sagv_wm()
> {
> skl_compute_wm_level(sagv_wm0, latency + whatever);
> }
>
> skl_build_plane_wm_single()
> {
> ...
> skl_compute_transition_wm();
> + if (gen >= 12)
> + tgl_compute_sagv_wm();
> }
>
> And for the progamming side we should just pick the right
> wm0 based on the crtc_state->use_sagv_wm or whatever flag.
>
> >
> > So if I remove it and this is called for pre-icl platforms, guess this would still
> > need wm_uv data?
> >
> >
> > Stan
> >
> > >
> > > > bool is_planar;
> > > > };
> > > >
> > > > struct skl_pipe_wm {
> > > > struct skl_plane_wm planes[I915_MAX_PLANES];
> > > > + bool can_sagv;
> > >
> > > I would call it use_sagv_wm or somesuch to make it actually clear what
> > > it does.
> > >
> > > > };
> > > >
> > > > enum vlv_wm_level {
> > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > > index c7d726a656b2..1b9925b6672c 100644
> > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > @@ -3871,6 +3871,9 @@ static bool icl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> > > > return intel_crtc_can_enable_sagv(crtc_state);
> > > > }
> > > >
> > > > +static bool
> > > > +tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state);
> > > > +
> > > > bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
> > > > {
> > > > if (bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes))
> > > > @@ -3884,7 +3887,7 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > > > struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > > > int ret;
> > > > struct intel_crtc *crtc;
> > > > - const struct intel_crtc_state *new_crtc_state;
> > > > + struct intel_crtc_state *new_crtc_state;
> > > > struct intel_bw_state *new_bw_state = NULL;
> > > > const struct intel_bw_state *old_bw_state = NULL;
> > > > int i;
> > > > @@ -3899,7 +3902,9 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > > >
> > > > old_bw_state = intel_atomic_get_old_bw_state(state);
> > > >
> > > > - if (INTEL_GEN(dev_priv) >= 11)
> > > > + if (INTEL_GEN(dev_priv) >= 12)
> > > > + can_sagv = tgl_crtc_can_enable_sagv(new_crtc_state);
> > > > + else if (INTEL_GEN(dev_priv) >= 11)
> > > > can_sagv = icl_crtc_can_enable_sagv(new_crtc_state);
> > > > else
> > > > can_sagv = skl_crtc_can_enable_sagv(new_crtc_state);
> > > > @@ -3921,6 +3926,24 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > > > return ret;
> > > > }
> > > >
> > > > + for_each_new_intel_crtc_in_state(state, crtc,
> > > > + new_crtc_state, i) {
> > > > + struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal;
> > > > +
> > > > + /*
> > > > + * Due to drm limitation at commit state, when
> > > > + * changes are written the whole atomic state is
> > > > + * zeroed away => which prevents from using it,
> > > > + * so just sticking it into pipe wm state for
> > > > + * keeping it simple - anyway this is related to wm.
> > > > + * Proper way in ideal universe would be of course not
> > > > + * to lose parent atomic state object from child crtc_state,
> > > > + * and stick to OOP programming principles, which had been
> > > > + * scientifically proven to work.
> > >
> > > Seems like random ramblings. I'd just nuke the comment.
> > >
> > > > + */
> > > > + pipe_wm->can_sagv = intel_can_enable_sagv(new_bw_state);
> > > > + }
> > > > +
> > > > if (intel_can_enable_sagv(new_bw_state) != intel_can_enable_sagv(old_bw_state)) {
> > > > ret = intel_atomic_serialize_global_state(&new_bw_state->base);
> > > > if (ret)
> > > > @@ -4664,12 +4687,39 @@ skl_plane_wm_level(const struct intel_crtc_state *crtc_state,
> > > > int level,
> > > > int color_plane)
> > > > {
> > > > - const struct skl_plane_wm *wm =
> > > > - &crtc_state->wm.skl.optimal.planes[plane_id];
> > > > + const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
> > > > + const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
> > > > +
> > > > + if (!level) {
> > > > + if (pipe_wm->can_sagv)
> > > > + return color_plane == 0 ? &wm->sagv_wm0 : &wm->uv_sagv_wm0;
> > > > + }
> > > >
> > > > return color_plane == 0 ? &wm->wm[level] : &wm->uv_wm[level];
> > > > }
> > > >
> > > > +static bool
> > > > +tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> > > > +{
> > > > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > > > + enum plane_id plane_id;
> > > > +
> > > > + if (!crtc_state->hw.active)
> > > > + return true;
> > > > +
> > > > + for_each_plane_id_on_crtc(crtc, plane_id) {
> > > > + const struct skl_ddb_entry *plane_alloc =
> > > > + &crtc_state->wm.skl.plane_ddb_y[plane_id];
> > > > + const struct skl_plane_wm *wm =
> > > > + &crtc_state->wm.skl.optimal.planes[plane_id];
> > > > +
> > > > + if (skl_ddb_entry_size(plane_alloc) < wm->sagv_wm0.min_ddb_alloc)
> > > > + return false;
> > > > + }
> > > > +
> > > > + return true;
> > > > +}
> > > > +
> > > > static int
> > > > skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
> > > > {
> > > > @@ -5251,10 +5301,17 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
> > > > static void
> > > > skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
> > > > const struct skl_wm_params *wm_params,
> > > > - struct skl_wm_level *levels)
> > > > + struct skl_plane_wm *plane_wm,
> > > > + int color_plane)
> > > > {
> > > > struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> > > > int level, max_level = ilk_wm_max_level(dev_priv);
> > > > + /*
> > > > + * Check which kind of plane is it and based on that calculate
> > > > + * correspondent WM levels.
> > > > + */
> > > > + struct skl_wm_level *levels = color_plane == 1 ?
> > > > + plane_wm->uv_wm : plane_wm->wm;
> > > > struct skl_wm_level *result_prev = &levels[0];
> > > >
> > > > for (level = 0; level <= max_level; level++) {
> > > > @@ -5268,6 +5325,40 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
> > > > }
> > > > }
> > > >
> > > > +static void skl_compute_sagv_wm(const struct intel_crtc_state *crtc_state,
> > > > + const struct skl_wm_params *wm_params,
> > > > + struct skl_plane_wm *plane_wm,
> > > > + int color_plane)
> > > > +{
> > > > + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> > > > + struct skl_wm_level *sagv_wm = color_plane == 1 ?
> > > > + &plane_wm->uv_sagv_wm0 : &plane_wm->sagv_wm0;
> > > > + struct skl_wm_level *levels = color_plane == 1 ?
> > > > + plane_wm->uv_wm : plane_wm->wm;
> > > > +
> > > > + /*
> > > > + * For Gen12 if it is an L0 we need to also
> > > > + * consider sagv_block_time when calculating
> > > > + * L0 watermark - we will need that when making
> > > > + * a decision whether enable SAGV or not.
> > > > + * For older gens we agreed to copy L0 value for
> > > > + * compatibility.
> > > > + */
> > > > + if ((INTEL_GEN(dev_priv) >= 12)) {
> > > > + u32 latency = dev_priv->wm.skl_latency[0];
> > > > +
> > > > + latency += dev_priv->sagv_block_time_us;
> > > > + skl_compute_plane_wm(crtc_state, 0, latency,
> > > > + wm_params, &levels[0],
> > > > + sagv_wm);
> > > > + DRM_DEBUG_KMS("%d L0 blocks required for SAGV vs %d for non-SAGV\n",
> > > > + sagv_wm->min_ddb_alloc, levels[0].min_ddb_alloc);
> > > > + } else {
> > > > + /* Since all members are POD */
> > > > + *sagv_wm = levels[0];
> > > > + }
> > > > +}
> > > > +
> > > > static void skl_compute_transition_wm(const struct intel_crtc_state *crtc_state,
> > > > const struct skl_wm_params *wp,
> > > > struct skl_plane_wm *wm)
> > > > @@ -5344,7 +5435,8 @@ static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
> > > > if (ret)
> > > > return ret;
> > > >
> > > > - skl_compute_wm_levels(crtc_state, &wm_params, wm->wm);
> > > > + skl_compute_wm_levels(crtc_state, &wm_params, wm, 0);
> > > > + skl_compute_sagv_wm(crtc_state, &wm_params, wm, 0);
> > > > skl_compute_transition_wm(crtc_state, &wm_params, wm);
> > > >
> > > > return 0;
> > > > @@ -5366,7 +5458,8 @@ static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
> > > > if (ret)
> > > > return ret;
> > > >
> > > > - skl_compute_wm_levels(crtc_state, &wm_params, wm->uv_wm);
> > > > + skl_compute_wm_levels(crtc_state, &wm_params, wm, 1);
> > > > + skl_compute_sagv_wm(crtc_state, &wm_params, wm, 1);
> > > >
> > > > return 0;
> > > > }
> > > > @@ -5751,6 +5844,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
> > > > enast(new_wm->wm[7].ignore_lines), new_wm->wm[7].plane_res_l,
> > > > enast(new_wm->trans_wm.ignore_lines), new_wm->trans_wm.plane_res_l);
> > > >
> > > > + drm_dbg_kms(&dev_priv->drm,
> > > > + "[PLANE:%d:%s] sagv wm0 lines %4d -> %4d\n",
> > > > + plane->base.base.id, plane->base.name,
> > > > + old_wm->sagv_wm0.plane_res_l,
> > > > + new_wm->sagv_wm0.plane_res_l);
> > > > +
> > > > drm_dbg_kms(&dev_priv->drm,
> > > > "[PLANE:%d:%s] blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
> > > > " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
> > > > @@ -5766,6 +5865,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
> > > > new_wm->wm[6].plane_res_b, new_wm->wm[7].plane_res_b,
> > > > new_wm->trans_wm.plane_res_b);
> > > >
> > > > + drm_dbg_kms(&dev_priv->drm,
> > > > + "[PLANE:%d:%s] sagv wm0 blocks %4d -> %4d\n",
> > > > + plane->base.base.id, plane->base.name,
> > > > + old_wm->sagv_wm0.plane_res_b,
> > > > + new_wm->sagv_wm0.plane_res_b);
> > > > +
> > > > drm_dbg_kms(&dev_priv->drm,
> > > > "[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
> > > > " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
> > > > @@ -5780,6 +5885,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
> > > > new_wm->wm[4].min_ddb_alloc, new_wm->wm[5].min_ddb_alloc,
> > > > new_wm->wm[6].min_ddb_alloc, new_wm->wm[7].min_ddb_alloc,
> > > > new_wm->trans_wm.min_ddb_alloc);
> > > > +
> > > > + drm_dbg_kms(&dev_priv->drm,
> > > > + "[PLANE:%d:%s] sagv wm0 min ddb %4d -> %4d\n",
> > > > + plane->base.base.id, plane->base.name,
> > > > + old_wm->sagv_wm0.min_ddb_alloc,
> > > > + new_wm->sagv_wm0.min_ddb_alloc);
> > > > }
> > > > }
> > > > }
> > > > @@ -6072,6 +6183,9 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
> > > > skl_wm_level_from_reg_val(val, &wm->wm[level]);
> > > > }
> > > >
> > > > + memcpy(&wm->sagv_wm0, &wm->wm[0],
> > > > + sizeof(struct skl_wm_level));
> > > > +
> > > > if (plane_id != PLANE_CURSOR)
> > > > val = I915_READ(PLANE_WM_TRANS(pipe, plane_id));
> > > > else
> > > > --
> > > > 2.24.1.485.gad05a3d8e5
> > >
> > > --
> > > Ville Syrjälä
> > > Intel
>
> --
> Ville Syrjälä
> Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Intel-gfx] [PATCH v27 3/6] drm/i915: Add TGL+ SAGV support
2020-05-06 12:12 ` Lisovskiy, Stanislav
@ 2020-05-06 13:16 ` Ville Syrjälä
2020-05-06 13:42 ` Lisovskiy, Stanislav
0 siblings, 1 reply; 24+ messages in thread
From: Ville Syrjälä @ 2020-05-06 13:16 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx
On Wed, May 06, 2020 at 03:12:10PM +0300, Lisovskiy, Stanislav wrote:
> On Wed, May 06, 2020 at 12:12:28PM +0300, Ville Syrjälä wrote:
> > On Wed, May 06, 2020 at 11:31:05AM +0300, Lisovskiy, Stanislav wrote:
> > > On Tue, May 05, 2020 at 01:59:11PM +0300, Ville Syrjälä wrote:
> > > > On Tue, May 05, 2020 at 01:22:44PM +0300, Stanislav Lisovskiy wrote:
> > > > > Starting from TGL we need to have a separate wm0
> > > > > values for SAGV and non-SAGV which affects
> > > > > how calculations are done.
> > > > >
> > > > > v2: Remove long lines
> > > > > v3: Removed COLOR_PLANE enum references
> > > > > v4, v5, v6: Fixed rebase conflict
> > > > >
> > > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > > > ---
> > > > > drivers/gpu/drm/i915/display/intel_display.c | 8 +-
> > > > > .../drm/i915/display/intel_display_types.h | 3 +
> > > > > drivers/gpu/drm/i915/intel_pm.c | 128 +++++++++++++++++-
> > > > > 3 files changed, 130 insertions(+), 9 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > index fd6d63b03489..be5741cb7595 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > @@ -13961,7 +13961,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
> > > > > /* Watermarks */
> > > > > for (level = 0; level <= max_level; level++) {
> > > > > if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > > > - &sw_plane_wm->wm[level]))
> > > > > + &sw_plane_wm->wm[level]) ||
> > > > > + (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > > > + &sw_plane_wm->sagv_wm0)))
> > > > > continue;
> > > > >
> > > > > drm_err(&dev_priv->drm,
> > > > > @@ -14016,7 +14018,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
> > > > > /* Watermarks */
> > > > > for (level = 0; level <= max_level; level++) {
> > > > > if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > > > - &sw_plane_wm->wm[level]))
> > > > > + &sw_plane_wm->wm[level]) ||
> > > > > + (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > > > + &sw_plane_wm->sagv_wm0)))
> > > > > continue;
> > > > >
> > > > > drm_err(&dev_priv->drm,
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > index 9488449e4b94..32cbbf7dddc6 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > @@ -688,11 +688,14 @@ struct skl_plane_wm {
> > > > > struct skl_wm_level wm[8];
> > > > > struct skl_wm_level uv_wm[8];
> > > > > struct skl_wm_level trans_wm;
> > > > > + struct skl_wm_level sagv_wm0;
> > > > > + struct skl_wm_level uv_sagv_wm0;
> > > >
> > > > As mentioned before uv_wm is not a thing on icl+, so nuke this.
> > >
> > > This is used in skl_plane_wm_level accessor, which is used for all
> > > platforms, not just icl+. I remember we had agreed that for all platforms
> > > before tgl I simply copy sagv_wm0 values from regular wm0, so that this
> > > behaviour is unified(remember that your comment about memcpy which I changed
> > > to assignment, see skl_compute_sagv_wm).
> >
> > I think having that duplicated is just making things more confusing.
> > Also uv_wm is never used by the hardware even on pre-icl, so having
> > the accessor thing use it for the hw programming just doesn't make
> > any sense.
>
> Problem is that we use it in skl_allocate_pipe_ddb in a few places:
>
> blocks += wm_level->min_ddb_alloc;
> blocks += wm_uv_level->min_ddb_alloc;
I don't think we should need any accessor in there. If we do
what I suggested earlier, which I think was something like
(can't find the mail anymore unfortunately):
for reverse wm levels {
blocks = sum(wm[level] blocks for all planes) +
sum(uv_wm[level] blocks for all planes)
...
if (block <= alloc_size)
break;
}
if (level < 0)
fail;
blocks_sagv = sum(sagv_wm blocks for all planes)
if (blocks_sagv > blocks && blocks_sagv <= alloc_size) {
blocks = blocks_sagv;
use_sagv_wm = true;
} else {
use_sagv_wm = false;
}
alloc_size -= blocks;
for_each_plane_id() {
total = use_sagv_wm ? sagv_wm.min_ddb_alloc :
wm[level].min_ddb_alloc;
...
}
>
> then those plane data rates:
>
> rate = plane_data_rate[plane_id];
> extra = min_t(u16, alloc_size,
> DIV64_U64_ROUND_UP(alloc_size * rate, total_data_rate));
> total[plane_id] = wm_level->min_ddb_alloc + extra;
> alloc_size -= extra;
> total_data_rate -= rate;
>
> if (total_data_rate == 0)
> break;
>
> rate = uv_plane_data_rate[plane_id];
> extra = min_t(u16, alloc_size,
> DIV64_U64_ROUND_UP(alloc_size * rate, total_data_rate));
>
> uv_total[plane_id] = wm_uv_level->min_ddb_alloc + extra;
>
> So if I remove this wm_uv from skl_plane_wm_level accessor,
> the logic in skl_allocate_pipe_ddb will obvisouly change?
>
>
> Stan
>
>
> >
> > For the compute side I think all we should really need is
> > something like:
> >
> > tgl_compute_sagv_wm()
> > {
> > skl_compute_wm_level(sagv_wm0, latency + whatever);
> > }
> >
> > skl_build_plane_wm_single()
> > {
> > ...
> > skl_compute_transition_wm();
> > + if (gen >= 12)
> > + tgl_compute_sagv_wm();
> > }
> >
> > And for the progamming side we should just pick the right
> > wm0 based on the crtc_state->use_sagv_wm or whatever flag.
> >
> > >
> > > So if I remove it and this is called for pre-icl platforms, guess this would still
> > > need wm_uv data?
> > >
> > >
> > > Stan
> > >
> > > >
> > > > > bool is_planar;
> > > > > };
> > > > >
> > > > > struct skl_pipe_wm {
> > > > > struct skl_plane_wm planes[I915_MAX_PLANES];
> > > > > + bool can_sagv;
> > > >
> > > > I would call it use_sagv_wm or somesuch to make it actually clear what
> > > > it does.
> > > >
> > > > > };
> > > > >
> > > > > enum vlv_wm_level {
> > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > > > index c7d726a656b2..1b9925b6672c 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > > @@ -3871,6 +3871,9 @@ static bool icl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> > > > > return intel_crtc_can_enable_sagv(crtc_state);
> > > > > }
> > > > >
> > > > > +static bool
> > > > > +tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state);
> > > > > +
> > > > > bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
> > > > > {
> > > > > if (bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes))
> > > > > @@ -3884,7 +3887,7 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > > > > struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > > > > int ret;
> > > > > struct intel_crtc *crtc;
> > > > > - const struct intel_crtc_state *new_crtc_state;
> > > > > + struct intel_crtc_state *new_crtc_state;
> > > > > struct intel_bw_state *new_bw_state = NULL;
> > > > > const struct intel_bw_state *old_bw_state = NULL;
> > > > > int i;
> > > > > @@ -3899,7 +3902,9 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > > > >
> > > > > old_bw_state = intel_atomic_get_old_bw_state(state);
> > > > >
> > > > > - if (INTEL_GEN(dev_priv) >= 11)
> > > > > + if (INTEL_GEN(dev_priv) >= 12)
> > > > > + can_sagv = tgl_crtc_can_enable_sagv(new_crtc_state);
> > > > > + else if (INTEL_GEN(dev_priv) >= 11)
> > > > > can_sagv = icl_crtc_can_enable_sagv(new_crtc_state);
> > > > > else
> > > > > can_sagv = skl_crtc_can_enable_sagv(new_crtc_state);
> > > > > @@ -3921,6 +3926,24 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > > > > return ret;
> > > > > }
> > > > >
> > > > > + for_each_new_intel_crtc_in_state(state, crtc,
> > > > > + new_crtc_state, i) {
> > > > > + struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal;
> > > > > +
> > > > > + /*
> > > > > + * Due to drm limitation at commit state, when
> > > > > + * changes are written the whole atomic state is
> > > > > + * zeroed away => which prevents from using it,
> > > > > + * so just sticking it into pipe wm state for
> > > > > + * keeping it simple - anyway this is related to wm.
> > > > > + * Proper way in ideal universe would be of course not
> > > > > + * to lose parent atomic state object from child crtc_state,
> > > > > + * and stick to OOP programming principles, which had been
> > > > > + * scientifically proven to work.
> > > >
> > > > Seems like random ramblings. I'd just nuke the comment.
> > > >
> > > > > + */
> > > > > + pipe_wm->can_sagv = intel_can_enable_sagv(new_bw_state);
> > > > > + }
> > > > > +
> > > > > if (intel_can_enable_sagv(new_bw_state) != intel_can_enable_sagv(old_bw_state)) {
> > > > > ret = intel_atomic_serialize_global_state(&new_bw_state->base);
> > > > > if (ret)
> > > > > @@ -4664,12 +4687,39 @@ skl_plane_wm_level(const struct intel_crtc_state *crtc_state,
> > > > > int level,
> > > > > int color_plane)
> > > > > {
> > > > > - const struct skl_plane_wm *wm =
> > > > > - &crtc_state->wm.skl.optimal.planes[plane_id];
> > > > > + const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
> > > > > + const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
> > > > > +
> > > > > + if (!level) {
> > > > > + if (pipe_wm->can_sagv)
> > > > > + return color_plane == 0 ? &wm->sagv_wm0 : &wm->uv_sagv_wm0;
> > > > > + }
> > > > >
> > > > > return color_plane == 0 ? &wm->wm[level] : &wm->uv_wm[level];
> > > > > }
> > > > >
> > > > > +static bool
> > > > > +tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> > > > > +{
> > > > > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > > > > + enum plane_id plane_id;
> > > > > +
> > > > > + if (!crtc_state->hw.active)
> > > > > + return true;
> > > > > +
> > > > > + for_each_plane_id_on_crtc(crtc, plane_id) {
> > > > > + const struct skl_ddb_entry *plane_alloc =
> > > > > + &crtc_state->wm.skl.plane_ddb_y[plane_id];
> > > > > + const struct skl_plane_wm *wm =
> > > > > + &crtc_state->wm.skl.optimal.planes[plane_id];
> > > > > +
> > > > > + if (skl_ddb_entry_size(plane_alloc) < wm->sagv_wm0.min_ddb_alloc)
> > > > > + return false;
> > > > > + }
> > > > > +
> > > > > + return true;
> > > > > +}
> > > > > +
> > > > > static int
> > > > > skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
> > > > > {
> > > > > @@ -5251,10 +5301,17 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
> > > > > static void
> > > > > skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
> > > > > const struct skl_wm_params *wm_params,
> > > > > - struct skl_wm_level *levels)
> > > > > + struct skl_plane_wm *plane_wm,
> > > > > + int color_plane)
> > > > > {
> > > > > struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> > > > > int level, max_level = ilk_wm_max_level(dev_priv);
> > > > > + /*
> > > > > + * Check which kind of plane is it and based on that calculate
> > > > > + * correspondent WM levels.
> > > > > + */
> > > > > + struct skl_wm_level *levels = color_plane == 1 ?
> > > > > + plane_wm->uv_wm : plane_wm->wm;
> > > > > struct skl_wm_level *result_prev = &levels[0];
> > > > >
> > > > > for (level = 0; level <= max_level; level++) {
> > > > > @@ -5268,6 +5325,40 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
> > > > > }
> > > > > }
> > > > >
> > > > > +static void skl_compute_sagv_wm(const struct intel_crtc_state *crtc_state,
> > > > > + const struct skl_wm_params *wm_params,
> > > > > + struct skl_plane_wm *plane_wm,
> > > > > + int color_plane)
> > > > > +{
> > > > > + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> > > > > + struct skl_wm_level *sagv_wm = color_plane == 1 ?
> > > > > + &plane_wm->uv_sagv_wm0 : &plane_wm->sagv_wm0;
> > > > > + struct skl_wm_level *levels = color_plane == 1 ?
> > > > > + plane_wm->uv_wm : plane_wm->wm;
> > > > > +
> > > > > + /*
> > > > > + * For Gen12 if it is an L0 we need to also
> > > > > + * consider sagv_block_time when calculating
> > > > > + * L0 watermark - we will need that when making
> > > > > + * a decision whether enable SAGV or not.
> > > > > + * For older gens we agreed to copy L0 value for
> > > > > + * compatibility.
> > > > > + */
> > > > > + if ((INTEL_GEN(dev_priv) >= 12)) {
> > > > > + u32 latency = dev_priv->wm.skl_latency[0];
> > > > > +
> > > > > + latency += dev_priv->sagv_block_time_us;
> > > > > + skl_compute_plane_wm(crtc_state, 0, latency,
> > > > > + wm_params, &levels[0],
> > > > > + sagv_wm);
> > > > > + DRM_DEBUG_KMS("%d L0 blocks required for SAGV vs %d for non-SAGV\n",
> > > > > + sagv_wm->min_ddb_alloc, levels[0].min_ddb_alloc);
> > > > > + } else {
> > > > > + /* Since all members are POD */
> > > > > + *sagv_wm = levels[0];
> > > > > + }
> > > > > +}
> > > > > +
> > > > > static void skl_compute_transition_wm(const struct intel_crtc_state *crtc_state,
> > > > > const struct skl_wm_params *wp,
> > > > > struct skl_plane_wm *wm)
> > > > > @@ -5344,7 +5435,8 @@ static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
> > > > > if (ret)
> > > > > return ret;
> > > > >
> > > > > - skl_compute_wm_levels(crtc_state, &wm_params, wm->wm);
> > > > > + skl_compute_wm_levels(crtc_state, &wm_params, wm, 0);
> > > > > + skl_compute_sagv_wm(crtc_state, &wm_params, wm, 0);
> > > > > skl_compute_transition_wm(crtc_state, &wm_params, wm);
> > > > >
> > > > > return 0;
> > > > > @@ -5366,7 +5458,8 @@ static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
> > > > > if (ret)
> > > > > return ret;
> > > > >
> > > > > - skl_compute_wm_levels(crtc_state, &wm_params, wm->uv_wm);
> > > > > + skl_compute_wm_levels(crtc_state, &wm_params, wm, 1);
> > > > > + skl_compute_sagv_wm(crtc_state, &wm_params, wm, 1);
> > > > >
> > > > > return 0;
> > > > > }
> > > > > @@ -5751,6 +5844,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
> > > > > enast(new_wm->wm[7].ignore_lines), new_wm->wm[7].plane_res_l,
> > > > > enast(new_wm->trans_wm.ignore_lines), new_wm->trans_wm.plane_res_l);
> > > > >
> > > > > + drm_dbg_kms(&dev_priv->drm,
> > > > > + "[PLANE:%d:%s] sagv wm0 lines %4d -> %4d\n",
> > > > > + plane->base.base.id, plane->base.name,
> > > > > + old_wm->sagv_wm0.plane_res_l,
> > > > > + new_wm->sagv_wm0.plane_res_l);
> > > > > +
> > > > > drm_dbg_kms(&dev_priv->drm,
> > > > > "[PLANE:%d:%s] blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
> > > > > " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
> > > > > @@ -5766,6 +5865,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
> > > > > new_wm->wm[6].plane_res_b, new_wm->wm[7].plane_res_b,
> > > > > new_wm->trans_wm.plane_res_b);
> > > > >
> > > > > + drm_dbg_kms(&dev_priv->drm,
> > > > > + "[PLANE:%d:%s] sagv wm0 blocks %4d -> %4d\n",
> > > > > + plane->base.base.id, plane->base.name,
> > > > > + old_wm->sagv_wm0.plane_res_b,
> > > > > + new_wm->sagv_wm0.plane_res_b);
> > > > > +
> > > > > drm_dbg_kms(&dev_priv->drm,
> > > > > "[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
> > > > > " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
> > > > > @@ -5780,6 +5885,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
> > > > > new_wm->wm[4].min_ddb_alloc, new_wm->wm[5].min_ddb_alloc,
> > > > > new_wm->wm[6].min_ddb_alloc, new_wm->wm[7].min_ddb_alloc,
> > > > > new_wm->trans_wm.min_ddb_alloc);
> > > > > +
> > > > > + drm_dbg_kms(&dev_priv->drm,
> > > > > + "[PLANE:%d:%s] sagv wm0 min ddb %4d -> %4d\n",
> > > > > + plane->base.base.id, plane->base.name,
> > > > > + old_wm->sagv_wm0.min_ddb_alloc,
> > > > > + new_wm->sagv_wm0.min_ddb_alloc);
> > > > > }
> > > > > }
> > > > > }
> > > > > @@ -6072,6 +6183,9 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
> > > > > skl_wm_level_from_reg_val(val, &wm->wm[level]);
> > > > > }
> > > > >
> > > > > + memcpy(&wm->sagv_wm0, &wm->wm[0],
> > > > > + sizeof(struct skl_wm_level));
> > > > > +
> > > > > if (plane_id != PLANE_CURSOR)
> > > > > val = I915_READ(PLANE_WM_TRANS(pipe, plane_id));
> > > > > else
> > > > > --
> > > > > 2.24.1.485.gad05a3d8e5
> > > >
> > > > --
> > > > Ville Syrjälä
> > > > Intel
> >
> > --
> > Ville Syrjälä
> > Intel
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Intel-gfx] [PATCH v27 3/6] drm/i915: Add TGL+ SAGV support
2020-05-06 13:16 ` Ville Syrjälä
@ 2020-05-06 13:42 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 24+ messages in thread
From: Lisovskiy, Stanislav @ 2020-05-06 13:42 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Wed, May 06, 2020 at 04:16:36PM +0300, Ville Syrjälä wrote:
> On Wed, May 06, 2020 at 03:12:10PM +0300, Lisovskiy, Stanislav wrote:
> > On Wed, May 06, 2020 at 12:12:28PM +0300, Ville Syrjälä wrote:
> > > On Wed, May 06, 2020 at 11:31:05AM +0300, Lisovskiy, Stanislav wrote:
> > > > On Tue, May 05, 2020 at 01:59:11PM +0300, Ville Syrjälä wrote:
> > > > > On Tue, May 05, 2020 at 01:22:44PM +0300, Stanislav Lisovskiy wrote:
> > > > > > Starting from TGL we need to have a separate wm0
> > > > > > values for SAGV and non-SAGV which affects
> > > > > > how calculations are done.
> > > > > >
> > > > > > v2: Remove long lines
> > > > > > v3: Removed COLOR_PLANE enum references
> > > > > > v4, v5, v6: Fixed rebase conflict
> > > > > >
> > > > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > > > > ---
> > > > > > drivers/gpu/drm/i915/display/intel_display.c | 8 +-
> > > > > > .../drm/i915/display/intel_display_types.h | 3 +
> > > > > > drivers/gpu/drm/i915/intel_pm.c | 128 +++++++++++++++++-
> > > > > > 3 files changed, 130 insertions(+), 9 deletions(-)
> > > > > >
> > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > > index fd6d63b03489..be5741cb7595 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > > @@ -13961,7 +13961,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
> > > > > > /* Watermarks */
> > > > > > for (level = 0; level <= max_level; level++) {
> > > > > > if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > > > > - &sw_plane_wm->wm[level]))
> > > > > > + &sw_plane_wm->wm[level]) ||
> > > > > > + (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > > > > + &sw_plane_wm->sagv_wm0)))
> > > > > > continue;
> > > > > >
> > > > > > drm_err(&dev_priv->drm,
> > > > > > @@ -14016,7 +14018,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
> > > > > > /* Watermarks */
> > > > > > for (level = 0; level <= max_level; level++) {
> > > > > > if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > > > > - &sw_plane_wm->wm[level]))
> > > > > > + &sw_plane_wm->wm[level]) ||
> > > > > > + (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > > > > + &sw_plane_wm->sagv_wm0)))
> > > > > > continue;
> > > > > >
> > > > > > drm_err(&dev_priv->drm,
> > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > > index 9488449e4b94..32cbbf7dddc6 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > > @@ -688,11 +688,14 @@ struct skl_plane_wm {
> > > > > > struct skl_wm_level wm[8];
> > > > > > struct skl_wm_level uv_wm[8];
> > > > > > struct skl_wm_level trans_wm;
> > > > > > + struct skl_wm_level sagv_wm0;
> > > > > > + struct skl_wm_level uv_sagv_wm0;
> > > > >
> > > > > As mentioned before uv_wm is not a thing on icl+, so nuke this.
> > > >
> > > > This is used in skl_plane_wm_level accessor, which is used for all
> > > > platforms, not just icl+. I remember we had agreed that for all platforms
> > > > before tgl I simply copy sagv_wm0 values from regular wm0, so that this
> > > > behaviour is unified(remember that your comment about memcpy which I changed
> > > > to assignment, see skl_compute_sagv_wm).
> > >
> > > I think having that duplicated is just making things more confusing.
> > > Also uv_wm is never used by the hardware even on pre-icl, so having
> > > the accessor thing use it for the hw programming just doesn't make
> > > any sense.
> >
> > Problem is that we use it in skl_allocate_pipe_ddb in a few places:
> >
> > blocks += wm_level->min_ddb_alloc;
> > blocks += wm_uv_level->min_ddb_alloc;
>
> I don't think we should need any accessor in there. If we do
> what I suggested earlier, which I think was something like
> (can't find the mail anymore unfortunately):
>
> for reverse wm levels {
> blocks = sum(wm[level] blocks for all planes) +
> sum(uv_wm[level] blocks for all planes)
> ...
> if (block <= alloc_size)
> break;
> }
>
> if (level < 0)
> fail;
>
> blocks_sagv = sum(sagv_wm blocks for all planes)
> if (blocks_sagv > blocks && blocks_sagv <= alloc_size) {
> blocks = blocks_sagv;
> use_sagv_wm = true;
> } else {
> use_sagv_wm = false;
> }
> alloc_size -= blocks;
>
> for_each_plane_id() {
> total = use_sagv_wm ? sagv_wm.min_ddb_alloc :
> wm[level].min_ddb_alloc;
> ...
> }
>
>
It is actually almost same behaviour now:
skl_compute_ddb->skl_sllocate_pipe_ddb is now invoked
before we call intel_compute_sagv_mask, which means
that use_sagv_wm is set to false, so it will be just
transparent leading to same wm->wm[level], wm->uv_wm[level]
accesses as done now.
Then in intel_compute_sagv_mask we calculate if each plane
ddb entry is big enough to fit SAGV min_ddb_alloc and set
use_sagv_wm bit in a pipe_wm struct.
So the only difference here is that use_sagv_wm bit is set
in intel_compute_sagv_mask and not skl_allocate_pipe_ddb,
which seems logical imo and anyway logic would be the same.
This accessor itself is then conveniently used in skl_write_plane
and skl_write_cursor_wm and others, providing proper wm level(otherwise
there would be duplicated condition everywhere).
So should I throw away skl_plane_wm_accessor completely?
Because we anyway use wm->uv_wm in skl_allocate_pipe_ddb
and the logic is otherwise same.
Stan
>
> >
> > then those plane data rates:
> >
> > rate = plane_data_rate[plane_id];
> > extra = min_t(u16, alloc_size,
> > DIV64_U64_ROUND_UP(alloc_size * rate, total_data_rate));
> > total[plane_id] = wm_level->min_ddb_alloc + extra;
> > alloc_size -= extra;
> > total_data_rate -= rate;
> >
> > if (total_data_rate == 0)
> > break;
> >
> > rate = uv_plane_data_rate[plane_id];
> > extra = min_t(u16, alloc_size,
> > DIV64_U64_ROUND_UP(alloc_size * rate, total_data_rate));
> >
> > uv_total[plane_id] = wm_uv_level->min_ddb_alloc + extra;
> >
> > So if I remove this wm_uv from skl_plane_wm_level accessor,
> > the logic in skl_allocate_pipe_ddb will obvisouly change?
> >
> >
> > Stan
> >
> >
> > >
> > > For the compute side I think all we should really need is
> > > something like:
> > >
> > > tgl_compute_sagv_wm()
> > > {
> > > skl_compute_wm_level(sagv_wm0, latency + whatever);
> > > }
> > >
> > > skl_build_plane_wm_single()
> > > {
> > > ...
> > > skl_compute_transition_wm();
> > > + if (gen >= 12)
> > > + tgl_compute_sagv_wm();
> > > }
> > >
> > > And for the progamming side we should just pick the right
> > > wm0 based on the crtc_state->use_sagv_wm or whatever flag.
> > >
> > > >
> > > > So if I remove it and this is called for pre-icl platforms, guess this would still
> > > > need wm_uv data?
> > > >
> > > >
> > > > Stan
> > > >
> > > > >
> > > > > > bool is_planar;
> > > > > > };
> > > > > >
> > > > > > struct skl_pipe_wm {
> > > > > > struct skl_plane_wm planes[I915_MAX_PLANES];
> > > > > > + bool can_sagv;
> > > > >
> > > > > I would call it use_sagv_wm or somesuch to make it actually clear what
> > > > > it does.
> > > > >
> > > > > > };
> > > > > >
> > > > > > enum vlv_wm_level {
> > > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > > > > index c7d726a656b2..1b9925b6672c 100644
> > > > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > > > @@ -3871,6 +3871,9 @@ static bool icl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> > > > > > return intel_crtc_can_enable_sagv(crtc_state);
> > > > > > }
> > > > > >
> > > > > > +static bool
> > > > > > +tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state);
> > > > > > +
> > > > > > bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
> > > > > > {
> > > > > > if (bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes))
> > > > > > @@ -3884,7 +3887,7 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > > > > > struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > > > > > int ret;
> > > > > > struct intel_crtc *crtc;
> > > > > > - const struct intel_crtc_state *new_crtc_state;
> > > > > > + struct intel_crtc_state *new_crtc_state;
> > > > > > struct intel_bw_state *new_bw_state = NULL;
> > > > > > const struct intel_bw_state *old_bw_state = NULL;
> > > > > > int i;
> > > > > > @@ -3899,7 +3902,9 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > > > > >
> > > > > > old_bw_state = intel_atomic_get_old_bw_state(state);
> > > > > >
> > > > > > - if (INTEL_GEN(dev_priv) >= 11)
> > > > > > + if (INTEL_GEN(dev_priv) >= 12)
> > > > > > + can_sagv = tgl_crtc_can_enable_sagv(new_crtc_state);
> > > > > > + else if (INTEL_GEN(dev_priv) >= 11)
> > > > > > can_sagv = icl_crtc_can_enable_sagv(new_crtc_state);
> > > > > > else
> > > > > > can_sagv = skl_crtc_can_enable_sagv(new_crtc_state);
> > > > > > @@ -3921,6 +3926,24 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > > > > > return ret;
> > > > > > }
> > > > > >
> > > > > > + for_each_new_intel_crtc_in_state(state, crtc,
> > > > > > + new_crtc_state, i) {
> > > > > > + struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal;
> > > > > > +
> > > > > > + /*
> > > > > > + * Due to drm limitation at commit state, when
> > > > > > + * changes are written the whole atomic state is
> > > > > > + * zeroed away => which prevents from using it,
> > > > > > + * so just sticking it into pipe wm state for
> > > > > > + * keeping it simple - anyway this is related to wm.
> > > > > > + * Proper way in ideal universe would be of course not
> > > > > > + * to lose parent atomic state object from child crtc_state,
> > > > > > + * and stick to OOP programming principles, which had been
> > > > > > + * scientifically proven to work.
> > > > >
> > > > > Seems like random ramblings. I'd just nuke the comment.
> > > > >
> > > > > > + */
> > > > > > + pipe_wm->can_sagv = intel_can_enable_sagv(new_bw_state);
> > > > > > + }
> > > > > > +
> > > > > > if (intel_can_enable_sagv(new_bw_state) != intel_can_enable_sagv(old_bw_state)) {
> > > > > > ret = intel_atomic_serialize_global_state(&new_bw_state->base);
> > > > > > if (ret)
> > > > > > @@ -4664,12 +4687,39 @@ skl_plane_wm_level(const struct intel_crtc_state *crtc_state,
> > > > > > int level,
> > > > > > int color_plane)
> > > > > > {
> > > > > > - const struct skl_plane_wm *wm =
> > > > > > - &crtc_state->wm.skl.optimal.planes[plane_id];
> > > > > > + const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
> > > > > > + const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
> > > > > > +
> > > > > > + if (!level) {
> > > > > > + if (pipe_wm->can_sagv)
> > > > > > + return color_plane == 0 ? &wm->sagv_wm0 : &wm->uv_sagv_wm0;
> > > > > > + }
> > > > > >
> > > > > > return color_plane == 0 ? &wm->wm[level] : &wm->uv_wm[level];
> > > > > > }
> > > > > >
> > > > > > +static bool
> > > > > > +tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> > > > > > +{
> > > > > > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > > > > > + enum plane_id plane_id;
> > > > > > +
> > > > > > + if (!crtc_state->hw.active)
> > > > > > + return true;
> > > > > > +
> > > > > > + for_each_plane_id_on_crtc(crtc, plane_id) {
> > > > > > + const struct skl_ddb_entry *plane_alloc =
> > > > > > + &crtc_state->wm.skl.plane_ddb_y[plane_id];
> > > > > > + const struct skl_plane_wm *wm =
> > > > > > + &crtc_state->wm.skl.optimal.planes[plane_id];
> > > > > > +
> > > > > > + if (skl_ddb_entry_size(plane_alloc) < wm->sagv_wm0.min_ddb_alloc)
> > > > > > + return false;
> > > > > > + }
> > > > > > +
> > > > > > + return true;
> > > > > > +}
> > > > > > +
> > > > > > static int
> > > > > > skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
> > > > > > {
> > > > > > @@ -5251,10 +5301,17 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
> > > > > > static void
> > > > > > skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
> > > > > > const struct skl_wm_params *wm_params,
> > > > > > - struct skl_wm_level *levels)
> > > > > > + struct skl_plane_wm *plane_wm,
> > > > > > + int color_plane)
> > > > > > {
> > > > > > struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> > > > > > int level, max_level = ilk_wm_max_level(dev_priv);
> > > > > > + /*
> > > > > > + * Check which kind of plane is it and based on that calculate
> > > > > > + * correspondent WM levels.
> > > > > > + */
> > > > > > + struct skl_wm_level *levels = color_plane == 1 ?
> > > > > > + plane_wm->uv_wm : plane_wm->wm;
> > > > > > struct skl_wm_level *result_prev = &levels[0];
> > > > > >
> > > > > > for (level = 0; level <= max_level; level++) {
> > > > > > @@ -5268,6 +5325,40 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
> > > > > > }
> > > > > > }
> > > > > >
> > > > > > +static void skl_compute_sagv_wm(const struct intel_crtc_state *crtc_state,
> > > > > > + const struct skl_wm_params *wm_params,
> > > > > > + struct skl_plane_wm *plane_wm,
> > > > > > + int color_plane)
> > > > > > +{
> > > > > > + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> > > > > > + struct skl_wm_level *sagv_wm = color_plane == 1 ?
> > > > > > + &plane_wm->uv_sagv_wm0 : &plane_wm->sagv_wm0;
> > > > > > + struct skl_wm_level *levels = color_plane == 1 ?
> > > > > > + plane_wm->uv_wm : plane_wm->wm;
> > > > > > +
> > > > > > + /*
> > > > > > + * For Gen12 if it is an L0 we need to also
> > > > > > + * consider sagv_block_time when calculating
> > > > > > + * L0 watermark - we will need that when making
> > > > > > + * a decision whether enable SAGV or not.
> > > > > > + * For older gens we agreed to copy L0 value for
> > > > > > + * compatibility.
> > > > > > + */
> > > > > > + if ((INTEL_GEN(dev_priv) >= 12)) {
> > > > > > + u32 latency = dev_priv->wm.skl_latency[0];
> > > > > > +
> > > > > > + latency += dev_priv->sagv_block_time_us;
> > > > > > + skl_compute_plane_wm(crtc_state, 0, latency,
> > > > > > + wm_params, &levels[0],
> > > > > > + sagv_wm);
> > > > > > + DRM_DEBUG_KMS("%d L0 blocks required for SAGV vs %d for non-SAGV\n",
> > > > > > + sagv_wm->min_ddb_alloc, levels[0].min_ddb_alloc);
> > > > > > + } else {
> > > > > > + /* Since all members are POD */
> > > > > > + *sagv_wm = levels[0];
> > > > > > + }
> > > > > > +}
> > > > > > +
> > > > > > static void skl_compute_transition_wm(const struct intel_crtc_state *crtc_state,
> > > > > > const struct skl_wm_params *wp,
> > > > > > struct skl_plane_wm *wm)
> > > > > > @@ -5344,7 +5435,8 @@ static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
> > > > > > if (ret)
> > > > > > return ret;
> > > > > >
> > > > > > - skl_compute_wm_levels(crtc_state, &wm_params, wm->wm);
> > > > > > + skl_compute_wm_levels(crtc_state, &wm_params, wm, 0);
> > > > > > + skl_compute_sagv_wm(crtc_state, &wm_params, wm, 0);
> > > > > > skl_compute_transition_wm(crtc_state, &wm_params, wm);
> > > > > >
> > > > > > return 0;
> > > > > > @@ -5366,7 +5458,8 @@ static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
> > > > > > if (ret)
> > > > > > return ret;
> > > > > >
> > > > > > - skl_compute_wm_levels(crtc_state, &wm_params, wm->uv_wm);
> > > > > > + skl_compute_wm_levels(crtc_state, &wm_params, wm, 1);
> > > > > > + skl_compute_sagv_wm(crtc_state, &wm_params, wm, 1);
> > > > > >
> > > > > > return 0;
> > > > > > }
> > > > > > @@ -5751,6 +5844,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
> > > > > > enast(new_wm->wm[7].ignore_lines), new_wm->wm[7].plane_res_l,
> > > > > > enast(new_wm->trans_wm.ignore_lines), new_wm->trans_wm.plane_res_l);
> > > > > >
> > > > > > + drm_dbg_kms(&dev_priv->drm,
> > > > > > + "[PLANE:%d:%s] sagv wm0 lines %4d -> %4d\n",
> > > > > > + plane->base.base.id, plane->base.name,
> > > > > > + old_wm->sagv_wm0.plane_res_l,
> > > > > > + new_wm->sagv_wm0.plane_res_l);
> > > > > > +
> > > > > > drm_dbg_kms(&dev_priv->drm,
> > > > > > "[PLANE:%d:%s] blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
> > > > > > " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
> > > > > > @@ -5766,6 +5865,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
> > > > > > new_wm->wm[6].plane_res_b, new_wm->wm[7].plane_res_b,
> > > > > > new_wm->trans_wm.plane_res_b);
> > > > > >
> > > > > > + drm_dbg_kms(&dev_priv->drm,
> > > > > > + "[PLANE:%d:%s] sagv wm0 blocks %4d -> %4d\n",
> > > > > > + plane->base.base.id, plane->base.name,
> > > > > > + old_wm->sagv_wm0.plane_res_b,
> > > > > > + new_wm->sagv_wm0.plane_res_b);
> > > > > > +
> > > > > > drm_dbg_kms(&dev_priv->drm,
> > > > > > "[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
> > > > > > " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
> > > > > > @@ -5780,6 +5885,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
> > > > > > new_wm->wm[4].min_ddb_alloc, new_wm->wm[5].min_ddb_alloc,
> > > > > > new_wm->wm[6].min_ddb_alloc, new_wm->wm[7].min_ddb_alloc,
> > > > > > new_wm->trans_wm.min_ddb_alloc);
> > > > > > +
> > > > > > + drm_dbg_kms(&dev_priv->drm,
> > > > > > + "[PLANE:%d:%s] sagv wm0 min ddb %4d -> %4d\n",
> > > > > > + plane->base.base.id, plane->base.name,
> > > > > > + old_wm->sagv_wm0.min_ddb_alloc,
> > > > > > + new_wm->sagv_wm0.min_ddb_alloc);
> > > > > > }
> > > > > > }
> > > > > > }
> > > > > > @@ -6072,6 +6183,9 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
> > > > > > skl_wm_level_from_reg_val(val, &wm->wm[level]);
> > > > > > }
> > > > > >
> > > > > > + memcpy(&wm->sagv_wm0, &wm->wm[0],
> > > > > > + sizeof(struct skl_wm_level));
> > > > > > +
> > > > > > if (plane_id != PLANE_CURSOR)
> > > > > > val = I915_READ(PLANE_WM_TRANS(pipe, plane_id));
> > > > > > else
> > > > > > --
> > > > > > 2.24.1.485.gad05a3d8e5
> > > > >
> > > > > --
> > > > > Ville Syrjälä
> > > > > Intel
> > >
> > > --
> > > Ville Syrjälä
> > > Intel
>
> --
> Ville Syrjälä
> Intel
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^ permalink raw reply [flat|nested] 24+ messages in thread
end of thread, other threads:[~2020-05-06 13:47 UTC | newest]
Thread overview: 24+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-05-05 10:22 [Intel-gfx] [PATCH v27 0/6] SAGV support for Gen12+ Stanislav Lisovskiy
2020-05-05 10:22 ` [Intel-gfx] [PATCH v27 1/6] drm/i915: Introduce skl_plane_wm_level accessor Stanislav Lisovskiy
2020-05-05 10:22 ` [Intel-gfx] [PATCH v27 2/6] drm/i915: Separate icl and skl SAGV checking Stanislav Lisovskiy
2020-05-05 10:42 ` Ville Syrjälä
2020-05-05 11:01 ` Ville Syrjälä
2020-05-05 20:37 ` Lisovskiy, Stanislav
2020-05-06 7:31 ` Ville Syrjälä
2020-05-06 7:55 ` Lisovskiy, Stanislav
2020-05-06 8:08 ` Ville Syrjälä
2020-05-06 8:43 ` Lisovskiy, Stanislav
2020-05-06 9:15 ` Ville Syrjälä
2020-05-05 10:22 ` [Intel-gfx] [PATCH v27 3/6] drm/i915: Add TGL+ SAGV support Stanislav Lisovskiy
2020-05-05 10:59 ` Ville Syrjälä
2020-05-06 8:31 ` Lisovskiy, Stanislav
2020-05-06 9:12 ` Ville Syrjälä
2020-05-06 12:12 ` Lisovskiy, Stanislav
2020-05-06 13:16 ` Ville Syrjälä
2020-05-06 13:42 ` Lisovskiy, Stanislav
2020-05-05 10:22 ` [Intel-gfx] [PATCH v27 4/6] drm/i915: Added required new PCode commands Stanislav Lisovskiy
2020-05-05 11:04 ` Ville Syrjälä
2020-05-05 10:22 ` [Intel-gfx] [PATCH v27 5/6] drm/i915: Restrict qgv points which don't have enough bandwidth Stanislav Lisovskiy
2020-05-05 10:22 ` [Intel-gfx] [PATCH v27 6/6] drm/i915: Enable SAGV support for Gen12 Stanislav Lisovskiy
2020-05-05 13:46 ` [Intel-gfx] ✓ Fi.CI.BAT: success for SAGV support for Gen12+ (rev35) Patchwork
2020-05-06 1:01 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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