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From: Christoph Hellwig <hch@lst.de>
To: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Christoph Hellwig <hch@lst.de>,
	Andrew Morton <akpm@linux-foundation.org>,
	Arnd Bergmann <arnd@arndb.de>,
	Roman Zippel <zippel@linux-m68k.org>,
	Jessica Yu <jeyu@kernel.org>, Michal Simek <monstr@monstr.eu>,
	the arch/x86 maintainers <x86@kernel.org>,
	alpha <linux-alpha@vger.kernel.org>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	Linux ARM <linux-arm-kernel@lists.infradead.org>,
	linux-c6x-dev@linux-c6x.org,
	"open list:QUALCOMM HEXAGON..." <linux-hexagon@vger.kernel.org>,
	"linux-ia64@vger.kernel.org" <linux-ia64@vger.kernel.org>,
	linux-m68k <linux-m68k@lists.linux-m68k.org>,
	"open list:BROADCOM NVRAM DRIVER" <linux-mips@vger.kernel.org>,
	Openrisc <openrisc@lists.librecores.org>,
	linuxppc-dev <linuxppc-dev@lists.ozlabs.org>,
	linux-riscv@lists.infr
Subject: Re: [PATCH 31/31] module: move the set_fs hack for flush_icache_range to m68k
Date: Mon, 11 May 2020 16:37:44 +0000	[thread overview]
Message-ID: <20200511163744.GB32228@lst.de> (raw)
In-Reply-To: <CAMuHMdW1S91i3x0unNcJnypHse7ifynGb4dZcVhJaemR3GH1Pg@mail.gmail.com>

On Mon, May 11, 2020 at 05:24:30PM +0200, Geert Uytterhoeven wrote:
> > Btw, do you know what part of flush_icache_range relied on set_fs?
> > Do any of the m68k maintainers have an idea how to handle that in
> > a nicer way when we can split the implementations?
> 
> arch/m68k/mm/cache.c:virt_to_phys_slow()
> 
> All instructions that look up addresses in the page tables look at the
> source/destination function codes (SFC/DFC) to know if they have to use
> the supervisor or user page tables.
> So the actual implementation is the same: set_fs() merely configures
> SFC/DFC, to select the address space to use.

So instead of the magic instructions could we use the normal kernel
virt to phys helpers instead of switching the addresses space?  Something
like this patch on top of the series:

diff --git a/arch/m68k/mm/cache.c b/arch/m68k/mm/cache.c
index 5ecb3310e8745..5a861a14c1e69 100644
--- a/arch/m68k/mm/cache.c
+++ b/arch/m68k/mm/cache.c
@@ -71,47 +71,87 @@ static unsigned long virt_to_phys_slow(unsigned long vaddr)
 	return 0;
 }
 
-/* Push n pages at kernel virtual address and clear the icache */
-/* RZ: use cpush %bc instead of cpush %dc, cinv %ic */
-void flush_icache_user_range(unsigned long address, unsigned long endaddr)
+static inline void coldfire_flush_icache_range(unsigned long start,
+		unsigned long end)
 {
-	if (CPU_IS_COLDFIRE) {
-		unsigned long start, end;
-		start = address & ICACHE_SET_MASK;
-		end = endaddr & ICACHE_SET_MASK;
-		if (start > end) {
-			flush_cf_icache(0, end);
-			end = ICACHE_MAX_ADDR;
-		}
-		flush_cf_icache(start, end);
-	} else if (CPU_IS_040_OR_060) {
-		address &= PAGE_MASK;
-
-		do {
-			asm volatile ("nop\n\t"
-				      ".chip 68040\n\t"
-				      "cpushp %%bc,(%0)\n\t"
-				      ".chip 68k"
-				      : : "a" (virt_to_phys_slow(address)));
-			address += PAGE_SIZE;
-		} while (address < endaddr);
-	} else {
-		unsigned long tmp;
-		asm volatile ("movec %%cacr,%0\n\t"
-			      "orw %1,%0\n\t"
-			      "movec %0,%%cacr"
-			      : "=&d" (tmp)
-			      : "di" (FLUSH_I));
+	start &= ICACHE_SET_MASK;
+	end &= ICACHE_SET_MASK;
+
+	if (start > end) {
+		flush_cf_icache(0, end);
+		end = ICACHE_MAX_ADDR;
 	}
+	flush_cf_icache(start, end);
+}
+
+static inline void mc68040_flush_icache_user_range(unsigned long start,
+		unsigned long end)
+{
+	start &= PAGE_MASK;
+
+	do {
+		asm volatile ("nop\n\t"
+			      ".chip 68040\n\t"
+			      "cpushp %%bc,(%0)\n\t"
+			      ".chip 68k"
+			      : : "a" (virt_to_phys_slow(start)));
+		start += PAGE_SIZE;
+	} while (start < end);
+}
+
+static inline void mc68020_flush_icache_range(unsigned long start,
+		unsigned long end)
+{
+	unsigned long tmp;
+
+	asm volatile ("movec %%cacr,%0\n\t"
+		      "orw %1,%0\n\t"
+		      "movec %0,%%cacr"
+		      : "=&d" (tmp)
+		      : "di" (FLUSH_I));
+}
+
+void flush_icache_user_range(unsigned long start, unsigned long end)
+{
+	if (CPU_IS_COLDFIRE)
+		coldfire_flush_icache_range(start, end);
+	else if (CPU_IS_040_OR_060)
+		mc68040_flush_icache_user_range(start, end);
+	else
+		mc68020_flush_icache_range(start, end);
 }
 
-void flush_icache_range(unsigned long address, unsigned long endaddr)
+static inline void mc68040_flush_icache_range(unsigned long start,
+		unsigned long end)
 {
-	mm_segment_t old_fs = get_fs();
+	start &= PAGE_MASK;
+
+	do {
+		void *vaddr = (void *)start;
+		phys_addr_t paddr;
+
+		if (is_vmalloc_addr(vaddr))
+			paddr = page_to_phys(vmalloc_to_page(vaddr));
+		else
+			paddr = virt_to_phys(vaddr);
+
+		asm volatile ("nop\n\t"
+			      ".chip 68040\n\t"
+			      "cpushp %%bc,(%0)\n\t"
+			      ".chip 68k"
+			      : : "a" (paddr));
+		start += PAGE_SIZE;
+	} while (start < end);
+}
 
-	set_fs(KERNEL_DS);
-	flush_icache_user_range(address, endaddr);
-	set_fs(old_fs);
+void flush_icache_range(unsigned long start, unsigned long end)
+{
+	if (CPU_IS_COLDFIRE)
+		coldfire_flush_icache_range(start, end);
+	else if (CPU_IS_040_OR_060)
+		mc68040_flush_icache_range(start, end);
+	else
+		mc68020_flush_icache_range(start, end);
 }
 EXPORT_SYMBOL(flush_icache_range);
 

WARNING: multiple messages have this Message-ID
From: Christoph Hellwig <hch@lst.de>
To: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Christoph Hellwig <hch@lst.de>,
	Andrew Morton <akpm@linux-foundation.org>,
	Arnd Bergmann <arnd@arndb.de>,
	Roman Zippel <zippel@linux-m68k.org>,
	Jessica Yu <jeyu@kernel.org>, Michal Simek <monstr@monstr.eu>,
	the arch/x86 maintainers <x86@kernel.org>,
	alpha <linux-alpha@vger.kernel.org>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	Linux ARM <linux-arm-kernel@lists.infradead.org>,
	linux-c6x-dev@linux-c6x.org,
	"open list:QUALCOMM HEXAGON..." <linux-hexagon@vger.kernel.org>,
	"linux-ia64@vger.kernel.org" <linux-ia64@vger.kernel.org>,
	linux-m68k <linux-m68k@lists.linux-m68k.org>,
	"open list:BROADCOM NVRAM DRIVER" <linux-mips@vger.kernel.org>,
	Openrisc <openrisc@lists.librecores.org>,
	linuxppc-dev <linuxppc-dev@lists.ozlabs.org>,
	linux-riscv@lists.infradead.org,
	Linux-sh list <linux-sh@vger.kernel.org>,
	sparclinux <sparclinux@vger.kernel.org>,
	Linux-Arch <linux-arch@vger.kernel.org>,
	Linux MM <linux-mm@kvack.org>,
	linux-um <linux-um@lists.infradead.org>,
	"open list:TENSILICA XTENSA PORT (xtensa)" 
	<linux-xtensa@linux-xtensa.org>,
	Linux FS Devel <linux-fsdevel@vger.kernel.org>
Subject: Re: [PATCH 31/31] module: move the set_fs hack for flush_icache_range to m68k
Date: Mon, 11 May 2020 18:37:44 +0200	[thread overview]
Message-ID: <20200511163744.GB32228@lst.de> (raw)
In-Reply-To: <CAMuHMdW1S91i3x0unNcJnypHse7ifynGb4dZcVhJaemR3GH1Pg@mail.gmail.com>

On Mon, May 11, 2020 at 05:24:30PM +0200, Geert Uytterhoeven wrote:
> > Btw, do you know what part of flush_icache_range relied on set_fs?
> > Do any of the m68k maintainers have an idea how to handle that in
> > a nicer way when we can split the implementations?
> 
> arch/m68k/mm/cache.c:virt_to_phys_slow()
> 
> All instructions that look up addresses in the page tables look at the
> source/destination function codes (SFC/DFC) to know if they have to use
> the supervisor or user page tables.
> So the actual implementation is the same: set_fs() merely configures
> SFC/DFC, to select the address space to use.

So instead of the magic instructions could we use the normal kernel
virt to phys helpers instead of switching the addresses space?  Something
like this patch on top of the series:

diff --git a/arch/m68k/mm/cache.c b/arch/m68k/mm/cache.c
index 5ecb3310e8745..5a861a14c1e69 100644
--- a/arch/m68k/mm/cache.c
+++ b/arch/m68k/mm/cache.c
@@ -71,47 +71,87 @@ static unsigned long virt_to_phys_slow(unsigned long vaddr)
 	return 0;
 }
 
-/* Push n pages at kernel virtual address and clear the icache */
-/* RZ: use cpush %bc instead of cpush %dc, cinv %ic */
-void flush_icache_user_range(unsigned long address, unsigned long endaddr)
+static inline void coldfire_flush_icache_range(unsigned long start,
+		unsigned long end)
 {
-	if (CPU_IS_COLDFIRE) {
-		unsigned long start, end;
-		start = address & ICACHE_SET_MASK;
-		end = endaddr & ICACHE_SET_MASK;
-		if (start > end) {
-			flush_cf_icache(0, end);
-			end = ICACHE_MAX_ADDR;
-		}
-		flush_cf_icache(start, end);
-	} else if (CPU_IS_040_OR_060) {
-		address &= PAGE_MASK;
-
-		do {
-			asm volatile ("nop\n\t"
-				      ".chip 68040\n\t"
-				      "cpushp %%bc,(%0)\n\t"
-				      ".chip 68k"
-				      : : "a" (virt_to_phys_slow(address)));
-			address += PAGE_SIZE;
-		} while (address < endaddr);
-	} else {
-		unsigned long tmp;
-		asm volatile ("movec %%cacr,%0\n\t"
-			      "orw %1,%0\n\t"
-			      "movec %0,%%cacr"
-			      : "=&d" (tmp)
-			      : "di" (FLUSH_I));
+	start &= ICACHE_SET_MASK;
+	end &= ICACHE_SET_MASK;
+
+	if (start > end) {
+		flush_cf_icache(0, end);
+		end = ICACHE_MAX_ADDR;
 	}
+	flush_cf_icache(start, end);
+}
+
+static inline void mc68040_flush_icache_user_range(unsigned long start,
+		unsigned long end)
+{
+	start &= PAGE_MASK;
+
+	do {
+		asm volatile ("nop\n\t"
+			      ".chip 68040\n\t"
+			      "cpushp %%bc,(%0)\n\t"
+			      ".chip 68k"
+			      : : "a" (virt_to_phys_slow(start)));
+		start += PAGE_SIZE;
+	} while (start < end);
+}
+
+static inline void mc68020_flush_icache_range(unsigned long start,
+		unsigned long end)
+{
+	unsigned long tmp;
+
+	asm volatile ("movec %%cacr,%0\n\t"
+		      "orw %1,%0\n\t"
+		      "movec %0,%%cacr"
+		      : "=&d" (tmp)
+		      : "di" (FLUSH_I));
+}
+
+void flush_icache_user_range(unsigned long start, unsigned long end)
+{
+	if (CPU_IS_COLDFIRE)
+		coldfire_flush_icache_range(start, end);
+	else if (CPU_IS_040_OR_060)
+		mc68040_flush_icache_user_range(start, end);
+	else
+		mc68020_flush_icache_range(start, end);
 }
 
-void flush_icache_range(unsigned long address, unsigned long endaddr)
+static inline void mc68040_flush_icache_range(unsigned long start,
+		unsigned long end)
 {
-	mm_segment_t old_fs = get_fs();
+	start &= PAGE_MASK;
+
+	do {
+		void *vaddr = (void *)start;
+		phys_addr_t paddr;
+
+		if (is_vmalloc_addr(vaddr))
+			paddr = page_to_phys(vmalloc_to_page(vaddr));
+		else
+			paddr = virt_to_phys(vaddr);
+
+		asm volatile ("nop\n\t"
+			      ".chip 68040\n\t"
+			      "cpushp %%bc,(%0)\n\t"
+			      ".chip 68k"
+			      : : "a" (paddr));
+		start += PAGE_SIZE;
+	} while (start < end);
+}
 
-	set_fs(KERNEL_DS);
-	flush_icache_user_range(address, endaddr);
-	set_fs(old_fs);
+void flush_icache_range(unsigned long start, unsigned long end)
+{
+	if (CPU_IS_COLDFIRE)
+		coldfire_flush_icache_range(start, end);
+	else if (CPU_IS_040_OR_060)
+		mc68040_flush_icache_range(start, end);
+	else
+		mc68020_flush_icache_range(start, end);
 }
 EXPORT_SYMBOL(flush_icache_range);
 

WARNING: multiple messages have this Message-ID
From: Christoph Hellwig <hch@lst.de>
To: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Christoph Hellwig <hch@lst.de>,
	Andrew Morton <akpm@linux-foundation.org>,
	Arnd Bergmann <arnd@arndb.de>,
	Roman Zippel <zippel@linux-m68k.org>,
	Jessica Yu <jeyu@kernel.org>, Michal Simek <monstr@monstr.eu>,
	the arch/x86 maintainers <x86@kernel.org>,
	alpha <linux-alpha@vger.kernel.org>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	Linux ARM <linux-arm-kernel@lists.infradead.org>,
	linux-c6x-dev@linux-c6x.org,
	"open list:QUALCOMM HEXAGON..." <linux-hexagon@vger.kernel.org>,
	"linux-ia64@vger.kernel.org" <linux-ia64@vger.kernel.org>,
	linux-m68k <linux-m68k@lists.linux-m68k.org>,
	"open list:BROADCOM NVRAM DRIVER" <linux-mips@vger.kernel.org>,
	Openrisc <openrisc@lists.librecores.org>,
	linuxppc-dev <linuxppc-dev@lists.ozlabs.org>,
	linux-riscv@lists.infr
Subject: Re: [PATCH 31/31] module: move the set_fs hack for flush_icache_range to m68k
Date: Mon, 11 May 2020 18:37:44 +0200	[thread overview]
Message-ID: <20200511163744.GB32228@lst.de> (raw)
In-Reply-To: <CAMuHMdW1S91i3x0unNcJnypHse7ifynGb4dZcVhJaemR3GH1Pg@mail.gmail.com>

On Mon, May 11, 2020 at 05:24:30PM +0200, Geert Uytterhoeven wrote:
> > Btw, do you know what part of flush_icache_range relied on set_fs?
> > Do any of the m68k maintainers have an idea how to handle that in
> > a nicer way when we can split the implementations?
> 
> arch/m68k/mm/cache.c:virt_to_phys_slow()
> 
> All instructions that look up addresses in the page tables look at the
> source/destination function codes (SFC/DFC) to know if they have to use
> the supervisor or user page tables.
> So the actual implementation is the same: set_fs() merely configures
> SFC/DFC, to select the address space to use.

So instead of the magic instructions could we use the normal kernel
virt to phys helpers instead of switching the addresses space?  Something
like this patch on top of the series:

diff --git a/arch/m68k/mm/cache.c b/arch/m68k/mm/cache.c
index 5ecb3310e8745..5a861a14c1e69 100644
--- a/arch/m68k/mm/cache.c
+++ b/arch/m68k/mm/cache.c
@@ -71,47 +71,87 @@ static unsigned long virt_to_phys_slow(unsigned long vaddr)
 	return 0;
 }
 
-/* Push n pages at kernel virtual address and clear the icache */
-/* RZ: use cpush %bc instead of cpush %dc, cinv %ic */
-void flush_icache_user_range(unsigned long address, unsigned long endaddr)
+static inline void coldfire_flush_icache_range(unsigned long start,
+		unsigned long end)
 {
-	if (CPU_IS_COLDFIRE) {
-		unsigned long start, end;
-		start = address & ICACHE_SET_MASK;
-		end = endaddr & ICACHE_SET_MASK;
-		if (start > end) {
-			flush_cf_icache(0, end);
-			end = ICACHE_MAX_ADDR;
-		}
-		flush_cf_icache(start, end);
-	} else if (CPU_IS_040_OR_060) {
-		address &= PAGE_MASK;
-
-		do {
-			asm volatile ("nop\n\t"
-				      ".chip 68040\n\t"
-				      "cpushp %%bc,(%0)\n\t"
-				      ".chip 68k"
-				      : : "a" (virt_to_phys_slow(address)));
-			address += PAGE_SIZE;
-		} while (address < endaddr);
-	} else {
-		unsigned long tmp;
-		asm volatile ("movec %%cacr,%0\n\t"
-			      "orw %1,%0\n\t"
-			      "movec %0,%%cacr"
-			      : "=&d" (tmp)
-			      : "di" (FLUSH_I));
+	start &= ICACHE_SET_MASK;
+	end &= ICACHE_SET_MASK;
+
+	if (start > end) {
+		flush_cf_icache(0, end);
+		end = ICACHE_MAX_ADDR;
 	}
+	flush_cf_icache(start, end);
+}
+
+static inline void mc68040_flush_icache_user_range(unsigned long start,
+		unsigned long end)
+{
+	start &= PAGE_MASK;
+
+	do {
+		asm volatile ("nop\n\t"
+			      ".chip 68040\n\t"
+			      "cpushp %%bc,(%0)\n\t"
+			      ".chip 68k"
+			      : : "a" (virt_to_phys_slow(start)));
+		start += PAGE_SIZE;
+	} while (start < end);
+}
+
+static inline void mc68020_flush_icache_range(unsigned long start,
+		unsigned long end)
+{
+	unsigned long tmp;
+
+	asm volatile ("movec %%cacr,%0\n\t"
+		      "orw %1,%0\n\t"
+		      "movec %0,%%cacr"
+		      : "=&d" (tmp)
+		      : "di" (FLUSH_I));
+}
+
+void flush_icache_user_range(unsigned long start, unsigned long end)
+{
+	if (CPU_IS_COLDFIRE)
+		coldfire_flush_icache_range(start, end);
+	else if (CPU_IS_040_OR_060)
+		mc68040_flush_icache_user_range(start, end);
+	else
+		mc68020_flush_icache_range(start, end);
 }
 
-void flush_icache_range(unsigned long address, unsigned long endaddr)
+static inline void mc68040_flush_icache_range(unsigned long start,
+		unsigned long end)
 {
-	mm_segment_t old_fs = get_fs();
+	start &= PAGE_MASK;
+
+	do {
+		void *vaddr = (void *)start;
+		phys_addr_t paddr;
+
+		if (is_vmalloc_addr(vaddr))
+			paddr = page_to_phys(vmalloc_to_page(vaddr));
+		else
+			paddr = virt_to_phys(vaddr);
+
+		asm volatile ("nop\n\t"
+			      ".chip 68040\n\t"
+			      "cpushp %%bc,(%0)\n\t"
+			      ".chip 68k"
+			      : : "a" (paddr));
+		start += PAGE_SIZE;
+	} while (start < end);
+}
 
-	set_fs(KERNEL_DS);
-	flush_icache_user_range(address, endaddr);
-	set_fs(old_fs);
+void flush_icache_range(unsigned long start, unsigned long end)
+{
+	if (CPU_IS_COLDFIRE)
+		coldfire_flush_icache_range(start, end);
+	else if (CPU_IS_040_OR_060)
+		mc68040_flush_icache_range(start, end);
+	else
+		mc68020_flush_icache_range(start, end);
 }
 EXPORT_SYMBOL(flush_icache_range);
 

WARNING: multiple messages have this Message-ID
From: Christoph Hellwig <hch@lst.de>
To: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Christoph Hellwig <hch@lst.de>,
	Andrew Morton <akpm@linux-foundation.org>,
	Arnd Bergmann <arnd@arndb.de>,
	Roman Zippel <zippel@linux-m68k.org>,
	Jessica Yu <jeyu@kernel.org>, Michal Simek <monstr@monstr.eu>,
	the arch/x86 maintainers <x86@kernel.org>,
	alpha <linux-alpha@vger.kernel.org>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	Linux ARM <linux-arm-kernel@lists.infradead.org>,
	linux-c6x-dev@linux-c6x.org,
	"open list:QUALCOMM HEXAGON..." <linux-hexagon@vger.kernel.org>,
	"linux-ia64@vger.kernel.org" <linux-ia64@vger.kernel.org>,
	linux-m68k <linux-m68k@lists.linux-m68k.org>,
	"open list:BROADCOM NVRAM DRIVER" <linux-mips@vger.kernel.org>,
	Openrisc <openrisc@lists.librecores.org>,
	linuxppc-dev <linuxppc-dev@lists.ozlabs.org>,
	linux-riscv@lists.infradead.org,
	Linux-sh list <linux-sh@vger.kernel.org>,
	sparclinux <sparclinux@vger.kernel.org>,
	Linux-Arch <linux-arch@vger.kernel.org>,
	Linux MM <linux-mm@kvack.org>,
	linux-um <linux-um@lists.infradead.org>,
	"open list:TENSILICA XTENSA PORT (xtensa)"
	<linux-xtensa@linux-xtensa.org>,
	Linux FS Devel <linux-fsdevel@vger.kernel.org>
Subject: Re: [PATCH 31/31] module: move the set_fs hack for flush_icache_range to m68k
Date: Mon, 11 May 2020 18:37:44 +0200	[thread overview]
Message-ID: <20200511163744.GB32228@lst.de> (raw)
Message-ID: <20200511163744.tCNgyuk_pepjQSgbVsKCeE2QDpiSYQ9y5NzdgHl52Ww@z> (raw)
In-Reply-To: <CAMuHMdW1S91i3x0unNcJnypHse7ifynGb4dZcVhJaemR3GH1Pg@mail.gmail.com>

On Mon, May 11, 2020 at 05:24:30PM +0200, Geert Uytterhoeven wrote:
> > Btw, do you know what part of flush_icache_range relied on set_fs?
> > Do any of the m68k maintainers have an idea how to handle that in
> > a nicer way when we can split the implementations?
> 
> arch/m68k/mm/cache.c:virt_to_phys_slow()
> 
> All instructions that look up addresses in the page tables look at the
> source/destination function codes (SFC/DFC) to know if they have to use
> the supervisor or user page tables.
> So the actual implementation is the same: set_fs() merely configures
> SFC/DFC, to select the address space to use.

So instead of the magic instructions could we use the normal kernel
virt to phys helpers instead of switching the addresses space?  Something
like this patch on top of the series:

diff --git a/arch/m68k/mm/cache.c b/arch/m68k/mm/cache.c
index 5ecb3310e8745..5a861a14c1e69 100644
--- a/arch/m68k/mm/cache.c
+++ b/arch/m68k/mm/cache.c
@@ -71,47 +71,87 @@ static unsigned long virt_to_phys_slow(unsigned long vaddr)
 	return 0;
 }
 
-/* Push n pages at kernel virtual address and clear the icache */
-/* RZ: use cpush %bc instead of cpush %dc, cinv %ic */
-void flush_icache_user_range(unsigned long address, unsigned long endaddr)
+static inline void coldfire_flush_icache_range(unsigned long start,
+		unsigned long end)
 {
-	if (CPU_IS_COLDFIRE) {
-		unsigned long start, end;
-		start = address & ICACHE_SET_MASK;
-		end = endaddr & ICACHE_SET_MASK;
-		if (start > end) {
-			flush_cf_icache(0, end);
-			end = ICACHE_MAX_ADDR;
-		}
-		flush_cf_icache(start, end);
-	} else if (CPU_IS_040_OR_060) {
-		address &= PAGE_MASK;
-
-		do {
-			asm volatile ("nop\n\t"
-				      ".chip 68040\n\t"
-				      "cpushp %%bc,(%0)\n\t"
-				      ".chip 68k"
-				      : : "a" (virt_to_phys_slow(address)));
-			address += PAGE_SIZE;
-		} while (address < endaddr);
-	} else {
-		unsigned long tmp;
-		asm volatile ("movec %%cacr,%0\n\t"
-			      "orw %1,%0\n\t"
-			      "movec %0,%%cacr"
-			      : "=&d" (tmp)
-			      : "di" (FLUSH_I));
+	start &= ICACHE_SET_MASK;
+	end &= ICACHE_SET_MASK;
+
+	if (start > end) {
+		flush_cf_icache(0, end);
+		end = ICACHE_MAX_ADDR;
 	}
+	flush_cf_icache(start, end);
+}
+
+static inline void mc68040_flush_icache_user_range(unsigned long start,
+		unsigned long end)
+{
+	start &= PAGE_MASK;
+
+	do {
+		asm volatile ("nop\n\t"
+			      ".chip 68040\n\t"
+			      "cpushp %%bc,(%0)\n\t"
+			      ".chip 68k"
+			      : : "a" (virt_to_phys_slow(start)));
+		start += PAGE_SIZE;
+	} while (start < end);
+}
+
+static inline void mc68020_flush_icache_range(unsigned long start,
+		unsigned long end)
+{
+	unsigned long tmp;
+
+	asm volatile ("movec %%cacr,%0\n\t"
+		      "orw %1,%0\n\t"
+		      "movec %0,%%cacr"
+		      : "=&d" (tmp)
+		      : "di" (FLUSH_I));
+}
+
+void flush_icache_user_range(unsigned long start, unsigned long end)
+{
+	if (CPU_IS_COLDFIRE)
+		coldfire_flush_icache_range(start, end);
+	else if (CPU_IS_040_OR_060)
+		mc68040_flush_icache_user_range(start, end);
+	else
+		mc68020_flush_icache_range(start, end);
 }
 
-void flush_icache_range(unsigned long address, unsigned long endaddr)
+static inline void mc68040_flush_icache_range(unsigned long start,
+		unsigned long end)
 {
-	mm_segment_t old_fs = get_fs();
+	start &= PAGE_MASK;
+
+	do {
+		void *vaddr = (void *)start;
+		phys_addr_t paddr;
+
+		if (is_vmalloc_addr(vaddr))
+			paddr = page_to_phys(vmalloc_to_page(vaddr));
+		else
+			paddr = virt_to_phys(vaddr);
+
+		asm volatile ("nop\n\t"
+			      ".chip 68040\n\t"
+			      "cpushp %%bc,(%0)\n\t"
+			      ".chip 68k"
+			      : : "a" (paddr));
+		start += PAGE_SIZE;
+	} while (start < end);
+}
 
-	set_fs(KERNEL_DS);
-	flush_icache_user_range(address, endaddr);
-	set_fs(old_fs);
+void flush_icache_range(unsigned long start, unsigned long end)
+{
+	if (CPU_IS_COLDFIRE)
+		coldfire_flush_icache_range(start, end);
+	else if (CPU_IS_040_OR_060)
+		mc68040_flush_icache_range(start, end);
+	else
+		mc68020_flush_icache_range(start, end);
 }
 EXPORT_SYMBOL(flush_icache_range);
 

WARNING: multiple messages have this Message-ID
From: Christoph Hellwig <hch@lst.de>
To: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: "linux-ia64@vger.kernel.org" <linux-ia64@vger.kernel.org>,
	Linux-sh list <linux-sh@vger.kernel.org>,
	Roman Zippel <zippel@linux-m68k.org>,
	"open list:BROADCOM NVRAM DRIVER" <linux-mips@vger.kernel.org>,
	Linux MM <linux-mm@kvack.org>,
	sparclinux <sparclinux@vger.kernel.org>,
	linux-riscv@lists.infradead.org, Christoph Hellwig <hch@lst.de>,
	Linux-Arch <linux-arch@vger.kernel.org>,
	linux-c6x-dev@linux-c6x.org,
	"open list:QUALCOMM HEXAGON..." <linux-hexagon@vger.kernel.org>,
	the arch/x86 maintainers <x86@kernel.org>,
	"open list:TENSILICA XTENSA PORT \(xtensa\)"
	<linux-xtensa@linux-xtensa.org>, Arnd Bergmann <arnd@arndb.de>,
	Jessica Yu <jeyu@kernel.org>,
	linux-um <linux-um@lists.infradead.org>,
	linux-m68k <linux-m68k@lists.linux-m68k.org>,
	Openrisc <openrisc@lists.librecores.org>,
	Linux ARM <linux-arm-kernel@lists.infradead.org>,
	Michal Simek <monstr@monstr.eu>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	alpha <linux-alpha@vger.kernel.org>,
	Linux FS Devel <linux-fsdevel@vger.kernel.org>,
	Andrew Morton <akpm@linux-foundation.org>,
	linuxppc-dev <linuxppc-dev@lists.ozlabs.org>
Subject: Re: [PATCH 31/31] module: move the set_fs hack for flush_icache_range to m68k
Date: Mon, 11 May 2020 18:37:44 +0200	[thread overview]
Message-ID: <20200511163744.GB32228@lst.de> (raw)
In-Reply-To: <CAMuHMdW1S91i3x0unNcJnypHse7ifynGb4dZcVhJaemR3GH1Pg@mail.gmail.com>

On Mon, May 11, 2020 at 05:24:30PM +0200, Geert Uytterhoeven wrote:
> > Btw, do you know what part of flush_icache_range relied on set_fs?
> > Do any of the m68k maintainers have an idea how to handle that in
> > a nicer way when we can split the implementations?
> 
> arch/m68k/mm/cache.c:virt_to_phys_slow()
> 
> All instructions that look up addresses in the page tables look at the
> source/destination function codes (SFC/DFC) to know if they have to use
> the supervisor or user page tables.
> So the actual implementation is the same: set_fs() merely configures
> SFC/DFC, to select the address space to use.

So instead of the magic instructions could we use the normal kernel
virt to phys helpers instead of switching the addresses space?  Something
like this patch on top of the series:

diff --git a/arch/m68k/mm/cache.c b/arch/m68k/mm/cache.c
index 5ecb3310e8745..5a861a14c1e69 100644
--- a/arch/m68k/mm/cache.c
+++ b/arch/m68k/mm/cache.c
@@ -71,47 +71,87 @@ static unsigned long virt_to_phys_slow(unsigned long vaddr)
 	return 0;
 }
 
-/* Push n pages at kernel virtual address and clear the icache */
-/* RZ: use cpush %bc instead of cpush %dc, cinv %ic */
-void flush_icache_user_range(unsigned long address, unsigned long endaddr)
+static inline void coldfire_flush_icache_range(unsigned long start,
+		unsigned long end)
 {
-	if (CPU_IS_COLDFIRE) {
-		unsigned long start, end;
-		start = address & ICACHE_SET_MASK;
-		end = endaddr & ICACHE_SET_MASK;
-		if (start > end) {
-			flush_cf_icache(0, end);
-			end = ICACHE_MAX_ADDR;
-		}
-		flush_cf_icache(start, end);
-	} else if (CPU_IS_040_OR_060) {
-		address &= PAGE_MASK;
-
-		do {
-			asm volatile ("nop\n\t"
-				      ".chip 68040\n\t"
-				      "cpushp %%bc,(%0)\n\t"
-				      ".chip 68k"
-				      : : "a" (virt_to_phys_slow(address)));
-			address += PAGE_SIZE;
-		} while (address < endaddr);
-	} else {
-		unsigned long tmp;
-		asm volatile ("movec %%cacr,%0\n\t"
-			      "orw %1,%0\n\t"
-			      "movec %0,%%cacr"
-			      : "=&d" (tmp)
-			      : "di" (FLUSH_I));
+	start &= ICACHE_SET_MASK;
+	end &= ICACHE_SET_MASK;
+
+	if (start > end) {
+		flush_cf_icache(0, end);
+		end = ICACHE_MAX_ADDR;
 	}
+	flush_cf_icache(start, end);
+}
+
+static inline void mc68040_flush_icache_user_range(unsigned long start,
+		unsigned long end)
+{
+	start &= PAGE_MASK;
+
+	do {
+		asm volatile ("nop\n\t"
+			      ".chip 68040\n\t"
+			      "cpushp %%bc,(%0)\n\t"
+			      ".chip 68k"
+			      : : "a" (virt_to_phys_slow(start)));
+		start += PAGE_SIZE;
+	} while (start < end);
+}
+
+static inline void mc68020_flush_icache_range(unsigned long start,
+		unsigned long end)
+{
+	unsigned long tmp;
+
+	asm volatile ("movec %%cacr,%0\n\t"
+		      "orw %1,%0\n\t"
+		      "movec %0,%%cacr"
+		      : "=&d" (tmp)
+		      : "di" (FLUSH_I));
+}
+
+void flush_icache_user_range(unsigned long start, unsigned long end)
+{
+	if (CPU_IS_COLDFIRE)
+		coldfire_flush_icache_range(start, end);
+	else if (CPU_IS_040_OR_060)
+		mc68040_flush_icache_user_range(start, end);
+	else
+		mc68020_flush_icache_range(start, end);
 }
 
-void flush_icache_range(unsigned long address, unsigned long endaddr)
+static inline void mc68040_flush_icache_range(unsigned long start,
+		unsigned long end)
 {
-	mm_segment_t old_fs = get_fs();
+	start &= PAGE_MASK;
+
+	do {
+		void *vaddr = (void *)start;
+		phys_addr_t paddr;
+
+		if (is_vmalloc_addr(vaddr))
+			paddr = page_to_phys(vmalloc_to_page(vaddr));
+		else
+			paddr = virt_to_phys(vaddr);
+
+		asm volatile ("nop\n\t"
+			      ".chip 68040\n\t"
+			      "cpushp %%bc,(%0)\n\t"
+			      ".chip 68k"
+			      : : "a" (paddr));
+		start += PAGE_SIZE;
+	} while (start < end);
+}
 
-	set_fs(KERNEL_DS);
-	flush_icache_user_range(address, endaddr);
-	set_fs(old_fs);
+void flush_icache_range(unsigned long start, unsigned long end)
+{
+	if (CPU_IS_COLDFIRE)
+		coldfire_flush_icache_range(start, end);
+	else if (CPU_IS_040_OR_060)
+		mc68040_flush_icache_range(start, end);
+	else
+		mc68020_flush_icache_range(start, end);
 }
 EXPORT_SYMBOL(flush_icache_range);
 


WARNING: multiple messages have this Message-ID
From: Christoph Hellwig <hch@lst.de>
To: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: "linux-ia64@vger.kernel.org" <linux-ia64@vger.kernel.org>,
	Linux-sh list <linux-sh@vger.kernel.org>,
	Roman Zippel <zippel@linux-m68k.org>,
	"open list:BROADCOM NVRAM DRIVER" <linux-mips@vger.kernel.org>,
	Linux MM <linux-mm@kvack.org>,
	sparclinux <sparclinux@vger.kernel.org>,
	linux-riscv@lists.infradead.org, Christoph Hellwig <hch@lst.de>,
	Linux-Arch <linux-arch@vger.kernel.org>,
	linux-c6x-dev@linux-c6x.org,
	"open list:QUALCOMM HEXAGON..." <linux-hexagon@vger.kernel.org>,
	the arch/x86 maintainers <x86@kernel.org>,
	"open list:TENSILICA XTENSA PORT \(xtensa\)"
	<linux-xtensa@linux-xtensa.org>, Arnd Bergmann <arnd@arndb.de>,
	Jessica Yu <jeyu@kernel.org>,
	linux-um <linux-um@lists.infradead.org>,
	linux-m68k <linux-m68k@lists.linux-m68k.org>,
	Openrisc <openrisc@lists.librecores.org>,
	Linux ARM <linux-arm-kernel@lists.infradead.org>,
	Michal Simek <monstr@monstr.eu>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	alpha <linux-alpha@vger.kernel.org>,
	Linux FS Devel <linux-fsdevel@vger.kernel.org>,
	Andrew Morton <akpm@linux-foundation.org>,
	linuxppc-dev <linuxppc-dev@lists.ozlabs.org>
Subject: Re: [PATCH 31/31] module: move the set_fs hack for flush_icache_range to m68k
Date: Mon, 11 May 2020 18:37:44 +0200	[thread overview]
Message-ID: <20200511163744.GB32228@lst.de> (raw)
In-Reply-To: <CAMuHMdW1S91i3x0unNcJnypHse7ifynGb4dZcVhJaemR3GH1Pg@mail.gmail.com>

On Mon, May 11, 2020 at 05:24:30PM +0200, Geert Uytterhoeven wrote:
> > Btw, do you know what part of flush_icache_range relied on set_fs?
> > Do any of the m68k maintainers have an idea how to handle that in
> > a nicer way when we can split the implementations?
> 
> arch/m68k/mm/cache.c:virt_to_phys_slow()
> 
> All instructions that look up addresses in the page tables look at the
> source/destination function codes (SFC/DFC) to know if they have to use
> the supervisor or user page tables.
> So the actual implementation is the same: set_fs() merely configures
> SFC/DFC, to select the address space to use.

So instead of the magic instructions could we use the normal kernel
virt to phys helpers instead of switching the addresses space?  Something
like this patch on top of the series:

diff --git a/arch/m68k/mm/cache.c b/arch/m68k/mm/cache.c
index 5ecb3310e8745..5a861a14c1e69 100644
--- a/arch/m68k/mm/cache.c
+++ b/arch/m68k/mm/cache.c
@@ -71,47 +71,87 @@ static unsigned long virt_to_phys_slow(unsigned long vaddr)
 	return 0;
 }
 
-/* Push n pages at kernel virtual address and clear the icache */
-/* RZ: use cpush %bc instead of cpush %dc, cinv %ic */
-void flush_icache_user_range(unsigned long address, unsigned long endaddr)
+static inline void coldfire_flush_icache_range(unsigned long start,
+		unsigned long end)
 {
-	if (CPU_IS_COLDFIRE) {
-		unsigned long start, end;
-		start = address & ICACHE_SET_MASK;
-		end = endaddr & ICACHE_SET_MASK;
-		if (start > end) {
-			flush_cf_icache(0, end);
-			end = ICACHE_MAX_ADDR;
-		}
-		flush_cf_icache(start, end);
-	} else if (CPU_IS_040_OR_060) {
-		address &= PAGE_MASK;
-
-		do {
-			asm volatile ("nop\n\t"
-				      ".chip 68040\n\t"
-				      "cpushp %%bc,(%0)\n\t"
-				      ".chip 68k"
-				      : : "a" (virt_to_phys_slow(address)));
-			address += PAGE_SIZE;
-		} while (address < endaddr);
-	} else {
-		unsigned long tmp;
-		asm volatile ("movec %%cacr,%0\n\t"
-			      "orw %1,%0\n\t"
-			      "movec %0,%%cacr"
-			      : "=&d" (tmp)
-			      : "di" (FLUSH_I));
+	start &= ICACHE_SET_MASK;
+	end &= ICACHE_SET_MASK;
+
+	if (start > end) {
+		flush_cf_icache(0, end);
+		end = ICACHE_MAX_ADDR;
 	}
+	flush_cf_icache(start, end);
+}
+
+static inline void mc68040_flush_icache_user_range(unsigned long start,
+		unsigned long end)
+{
+	start &= PAGE_MASK;
+
+	do {
+		asm volatile ("nop\n\t"
+			      ".chip 68040\n\t"
+			      "cpushp %%bc,(%0)\n\t"
+			      ".chip 68k"
+			      : : "a" (virt_to_phys_slow(start)));
+		start += PAGE_SIZE;
+	} while (start < end);
+}
+
+static inline void mc68020_flush_icache_range(unsigned long start,
+		unsigned long end)
+{
+	unsigned long tmp;
+
+	asm volatile ("movec %%cacr,%0\n\t"
+		      "orw %1,%0\n\t"
+		      "movec %0,%%cacr"
+		      : "=&d" (tmp)
+		      : "di" (FLUSH_I));
+}
+
+void flush_icache_user_range(unsigned long start, unsigned long end)
+{
+	if (CPU_IS_COLDFIRE)
+		coldfire_flush_icache_range(start, end);
+	else if (CPU_IS_040_OR_060)
+		mc68040_flush_icache_user_range(start, end);
+	else
+		mc68020_flush_icache_range(start, end);
 }
 
-void flush_icache_range(unsigned long address, unsigned long endaddr)
+static inline void mc68040_flush_icache_range(unsigned long start,
+		unsigned long end)
 {
-	mm_segment_t old_fs = get_fs();
+	start &= PAGE_MASK;
+
+	do {
+		void *vaddr = (void *)start;
+		phys_addr_t paddr;
+
+		if (is_vmalloc_addr(vaddr))
+			paddr = page_to_phys(vmalloc_to_page(vaddr));
+		else
+			paddr = virt_to_phys(vaddr);
+
+		asm volatile ("nop\n\t"
+			      ".chip 68040\n\t"
+			      "cpushp %%bc,(%0)\n\t"
+			      ".chip 68k"
+			      : : "a" (paddr));
+		start += PAGE_SIZE;
+	} while (start < end);
+}
 
-	set_fs(KERNEL_DS);
-	flush_icache_user_range(address, endaddr);
-	set_fs(old_fs);
+void flush_icache_range(unsigned long start, unsigned long end)
+{
+	if (CPU_IS_COLDFIRE)
+		coldfire_flush_icache_range(start, end);
+	else if (CPU_IS_040_OR_060)
+		mc68040_flush_icache_range(start, end);
+	else
+		mc68020_flush_icache_range(start, end);
 }
 EXPORT_SYMBOL(flush_icache_range);
 

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

WARNING: multiple messages have this Message-ID
From: Christoph Hellwig <hch@lst.de>
To: openrisc@lists.librecores.org
Subject: [OpenRISC] [PATCH 31/31] module: move the set_fs hack for flush_icache_range to m68k
Date: Mon, 11 May 2020 18:37:44 +0200	[thread overview]
Message-ID: <20200511163744.GB32228@lst.de> (raw)
In-Reply-To: <CAMuHMdW1S91i3x0unNcJnypHse7ifynGb4dZcVhJaemR3GH1Pg@mail.gmail.com>

On Mon, May 11, 2020 at 05:24:30PM +0200, Geert Uytterhoeven wrote:
> > Btw, do you know what part of flush_icache_range relied on set_fs?
> > Do any of the m68k maintainers have an idea how to handle that in
> > a nicer way when we can split the implementations?
> 
> arch/m68k/mm/cache.c:virt_to_phys_slow()
> 
> All instructions that look up addresses in the page tables look at the
> source/destination function codes (SFC/DFC) to know if they have to use
> the supervisor or user page tables.
> So the actual implementation is the same: set_fs() merely configures
> SFC/DFC, to select the address space to use.

So instead of the magic instructions could we use the normal kernel
virt to phys helpers instead of switching the addresses space?  Something
like this patch on top of the series:

diff --git a/arch/m68k/mm/cache.c b/arch/m68k/mm/cache.c
index 5ecb3310e8745..5a861a14c1e69 100644
--- a/arch/m68k/mm/cache.c
+++ b/arch/m68k/mm/cache.c
@@ -71,47 +71,87 @@ static unsigned long virt_to_phys_slow(unsigned long vaddr)
 	return 0;
 }
 
-/* Push n pages at kernel virtual address and clear the icache */
-/* RZ: use cpush %bc instead of cpush %dc, cinv %ic */
-void flush_icache_user_range(unsigned long address, unsigned long endaddr)
+static inline void coldfire_flush_icache_range(unsigned long start,
+		unsigned long end)
 {
-	if (CPU_IS_COLDFIRE) {
-		unsigned long start, end;
-		start = address & ICACHE_SET_MASK;
-		end = endaddr & ICACHE_SET_MASK;
-		if (start > end) {
-			flush_cf_icache(0, end);
-			end = ICACHE_MAX_ADDR;
-		}
-		flush_cf_icache(start, end);
-	} else if (CPU_IS_040_OR_060) {
-		address &= PAGE_MASK;
-
-		do {
-			asm volatile ("nop\n\t"
-				      ".chip 68040\n\t"
-				      "cpushp %%bc,(%0)\n\t"
-				      ".chip 68k"
-				      : : "a" (virt_to_phys_slow(address)));
-			address += PAGE_SIZE;
-		} while (address < endaddr);
-	} else {
-		unsigned long tmp;
-		asm volatile ("movec %%cacr,%0\n\t"
-			      "orw %1,%0\n\t"
-			      "movec %0,%%cacr"
-			      : "=&d" (tmp)
-			      : "di" (FLUSH_I));
+	start &= ICACHE_SET_MASK;
+	end &= ICACHE_SET_MASK;
+
+	if (start > end) {
+		flush_cf_icache(0, end);
+		end = ICACHE_MAX_ADDR;
 	}
+	flush_cf_icache(start, end);
+}
+
+static inline void mc68040_flush_icache_user_range(unsigned long start,
+		unsigned long end)
+{
+	start &= PAGE_MASK;
+
+	do {
+		asm volatile ("nop\n\t"
+			      ".chip 68040\n\t"
+			      "cpushp %%bc,(%0)\n\t"
+			      ".chip 68k"
+			      : : "a" (virt_to_phys_slow(start)));
+		start += PAGE_SIZE;
+	} while (start < end);
+}
+
+static inline void mc68020_flush_icache_range(unsigned long start,
+		unsigned long end)
+{
+	unsigned long tmp;
+
+	asm volatile ("movec %%cacr,%0\n\t"
+		      "orw %1,%0\n\t"
+		      "movec %0,%%cacr"
+		      : "=&d" (tmp)
+		      : "di" (FLUSH_I));
+}
+
+void flush_icache_user_range(unsigned long start, unsigned long end)
+{
+	if (CPU_IS_COLDFIRE)
+		coldfire_flush_icache_range(start, end);
+	else if (CPU_IS_040_OR_060)
+		mc68040_flush_icache_user_range(start, end);
+	else
+		mc68020_flush_icache_range(start, end);
 }
 
-void flush_icache_range(unsigned long address, unsigned long endaddr)
+static inline void mc68040_flush_icache_range(unsigned long start,
+		unsigned long end)
 {
-	mm_segment_t old_fs = get_fs();
+	start &= PAGE_MASK;
+
+	do {
+		void *vaddr = (void *)start;
+		phys_addr_t paddr;
+
+		if (is_vmalloc_addr(vaddr))
+			paddr = page_to_phys(vmalloc_to_page(vaddr));
+		else
+			paddr = virt_to_phys(vaddr);
+
+		asm volatile ("nop\n\t"
+			      ".chip 68040\n\t"
+			      "cpushp %%bc,(%0)\n\t"
+			      ".chip 68k"
+			      : : "a" (paddr));
+		start += PAGE_SIZE;
+	} while (start < end);
+}
 
-	set_fs(KERNEL_DS);
-	flush_icache_user_range(address, endaddr);
-	set_fs(old_fs);
+void flush_icache_range(unsigned long start, unsigned long end)
+{
+	if (CPU_IS_COLDFIRE)
+		coldfire_flush_icache_range(start, end);
+	else if (CPU_IS_040_OR_060)
+		mc68040_flush_icache_range(start, end);
+	else
+		mc68020_flush_icache_range(start, end);
 }
 EXPORT_SYMBOL(flush_icache_range);
 

  reply	other threads:[~2020-05-11 16:37 UTC|newest]

Thread overview: 279+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-10  7:54 sort out the flush_icache_range mess Christoph Hellwig
2020-05-10  7:54 ` [OpenRISC] " Christoph Hellwig
2020-05-10  7:54 ` Christoph Hellwig
2020-05-10  7:54 ` Christoph Hellwig
2020-05-10  7:54 ` Christoph Hellwig
2020-05-10  7:54 ` [PATCH 01/31] arm: fix the flush_icache_range arguments in set_fiq_handler Christoph Hellwig
2020-05-10  7:54   ` [OpenRISC] " Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-10  7:54 ` [PATCH 02/31] arm64: fix the flush_icache_range arguments in machine_kexec Christoph Hellwig
2020-05-10  7:54   ` [OpenRISC] " Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-11  7:51   ` Will Deacon
2020-05-11  7:51     ` [OpenRISC] " Will Deacon
2020-05-11  7:51     ` Will Deacon
2020-05-11  7:51     ` Will Deacon
2020-05-11  7:51     ` Will Deacon
2020-05-11 11:00     ` Catalin Marinas
2020-05-11 11:00       ` [OpenRISC] " Catalin Marinas
2020-05-11 11:00       ` Catalin Marinas
2020-05-11 11:00       ` Catalin Marinas
2020-05-11 11:00       ` Catalin Marinas
2020-05-11 15:15       ` Christoph Hellwig
2020-05-11 15:15         ` [OpenRISC] " Christoph Hellwig
2020-05-11 15:15         ` Christoph Hellwig
2020-05-11 15:15         ` Christoph Hellwig
2020-05-11 15:15         ` Christoph Hellwig
2020-05-11 15:15         ` Christoph Hellwig
2020-05-10  7:54 ` [PATCH 03/31] MIPS: unexport __flush_icache_user_range Christoph Hellwig
2020-05-10  7:54   ` [OpenRISC] " Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-11 16:01   ` Thomas Bogendoerfer
2020-05-11 16:01     ` [OpenRISC] " Thomas Bogendoerfer
2020-05-11 16:01     ` Thomas Bogendoerfer
2020-05-11 16:01     ` Thomas Bogendoerfer
2020-05-11 16:01     ` Thomas Bogendoerfer
2020-05-10  7:54 ` [PATCH 04/31] nds32: unexport flush_icache_page Christoph Hellwig
2020-05-10  7:54   ` [OpenRISC] " Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-10  7:54 ` [PATCH 05/31] powerpc: unexport flush_icache_user_range Christoph Hellwig
2020-05-10  7:54   ` [OpenRISC] " Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-10  7:54 ` [PATCH 06/31] unicore32: remove flush_cache_user_range Christoph Hellwig
2020-05-10  7:54   ` [OpenRISC] " Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-10  7:54 ` [PATCH 07/31] asm-generic: fix the inclusion guards for cacheflush.h Christoph Hellwig
2020-05-10  7:54   ` [OpenRISC] " Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-10  7:54 ` [PATCH 08/31] asm-generic: don't include <linux/mm.h> in cacheflush.h Christoph Hellwig
2020-05-10  7:54   ` [OpenRISC] " Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-10  7:54 ` [PATCH 09/31] asm-generic: improve the flush_dcache_page stub Christoph Hellwig
2020-05-10  7:54   ` [OpenRISC] " Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-10  7:54 ` [PATCH 10/31] alpha: use asm-generic/cacheflush.h Christoph Hellwig
2020-05-10  7:54   ` [OpenRISC] " Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-10  7:54 ` [PATCH 11/31] arm64: " Christoph Hellwig
2020-05-10  7:54   ` [OpenRISC] " Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-10  7:54 ` [PATCH 12/31] c6x: " Christoph Hellwig
2020-05-10  7:54   ` [OpenRISC] " Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-10  7:54 ` [PATCH 13/31] hexagon: " Christoph Hellwig
2020-05-10  7:54   ` [OpenRISC] " Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-10  7:54 ` [PATCH 14/31] ia64: " Christoph Hellwig
2020-05-10  7:54   ` [OpenRISC] " Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-10  7:54 ` [PATCH 15/31] microblaze: " Christoph Hellwig
2020-05-10  7:54   ` [OpenRISC] " Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-10  7:54 ` [PATCH 16/31] m68knommu: " Christoph Hellwig
2020-05-10  7:54   ` [OpenRISC] " Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-12 14:44   ` Greg Ungerer
2020-05-12 14:44     ` [OpenRISC] " Greg Ungerer
2020-05-12 14:44     ` Greg Ungerer
2020-05-12 14:44     ` Greg Ungerer
2020-05-12 14:44     ` Greg Ungerer
2020-05-10  7:54 ` [PATCH 17/31] openrisc: " Christoph Hellwig
2020-05-10  7:54   ` [OpenRISC] " Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-10  7:54 ` [PATCH 18/31] powerpc: " Christoph Hellwig
2020-05-10  7:54   ` [OpenRISC] " Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-10  7:54 ` [PATCH 19/31] riscv: " Christoph Hellwig
2020-05-10  7:54   ` [OpenRISC] " Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-12 23:00   ` Palmer Dabbelt
2020-05-12 23:00     ` [OpenRISC] " Palmer Dabbelt
2020-05-12 23:00     ` Palmer Dabbelt
2020-05-12 23:00     ` Palmer Dabbelt
2020-05-12 23:00     ` Palmer Dabbelt
2020-05-13  6:23     ` Christoph Hellwig
2020-05-13  6:23       ` [OpenRISC] " Christoph Hellwig
2020-05-13  6:23       ` Christoph Hellwig
2020-05-13  6:23       ` Christoph Hellwig
2020-05-13  6:23       ` Christoph Hellwig
2020-05-10  7:54 ` [PATCH 20/31] arm,sparc,unicore32: remove flush_icache_user_range Christoph Hellwig
2020-05-10  7:54   ` [OpenRISC] [PATCH 20/31] arm, sparc, unicore32: " Christoph Hellwig
2020-05-10  7:54   ` [PATCH 20/31] arm,sparc,unicore32: " Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-10  7:54   ` Christoph Hellwig
2020-05-10  7:55 ` [PATCH 21/31] mm: rename flush_icache_user_range to flush_icache_user_page Christoph Hellwig
2020-05-10  7:55   ` [OpenRISC] " Christoph Hellwig
2020-05-10  7:55   ` Christoph Hellwig
2020-05-10  7:55   ` Christoph Hellwig
2020-05-10  7:55   ` Christoph Hellwig
2020-05-11  7:36   ` Geert Uytterhoeven
2020-05-11  7:36     ` [OpenRISC] " Geert Uytterhoeven
2020-05-11  7:36     ` Geert Uytterhoeven
2020-05-11  7:36     ` Geert Uytterhoeven
2020-05-11  7:36     ` Geert Uytterhoeven
2020-05-11  7:36     ` Geert Uytterhoeven
2020-05-11  7:36     ` Geert Uytterhoeven
2020-05-11  7:36     ` Geert Uytterhoeven
2020-05-10  7:55 ` [PATCH 22/31] asm-generic: add a flush_icache_user_range stub Christoph Hellwig
2020-05-10  7:55   ` [OpenRISC] " Christoph Hellwig
2020-05-10  7:55   ` Christoph Hellwig
2020-05-10  7:55   ` Christoph Hellwig
2020-05-10  7:55   ` Christoph Hellwig
2020-05-10  7:55 ` [PATCH 23/31] sh: implement flush_icache_user_range Christoph Hellwig
2020-05-10  7:55   ` [OpenRISC] " Christoph Hellwig
2020-05-10  7:55   ` Christoph Hellwig
2020-05-10  7:55   ` Christoph Hellwig
2020-05-10  7:55   ` Christoph Hellwig
2020-05-10  7:55 ` [PATCH 24/31] xtensa: " Christoph Hellwig
2020-05-10  7:55   ` [OpenRISC] " Christoph Hellwig
2020-05-10  7:55   ` Christoph Hellwig
2020-05-10  7:55   ` Christoph Hellwig
2020-05-10  7:55   ` Christoph Hellwig
2020-05-10  7:55 ` [PATCH 25/31] arm: rename flush_cache_user_range to flush_icache_user_range Christoph Hellwig
2020-05-10  7:55   ` [OpenRISC] " Christoph Hellwig
2020-05-10  7:55   ` Christoph Hellwig
2020-05-10  7:55   ` Christoph Hellwig
2020-05-10  7:55   ` Christoph Hellwig
2020-05-10  7:55 ` [PATCH 26/31] m68k: implement flush_icache_user_range Christoph Hellwig
2020-05-10  7:55   ` [OpenRISC] " Christoph Hellwig
2020-05-10  7:55   ` Christoph Hellwig
2020-05-10  7:55   ` Christoph Hellwig
2020-05-10  7:55   ` Christoph Hellwig
2020-05-11  7:38   ` Geert Uytterhoeven
2020-05-11  7:38     ` [OpenRISC] " Geert Uytterhoeven
2020-05-11  7:38     ` Geert Uytterhoeven
2020-05-11  7:38     ` Geert Uytterhoeven
2020-05-11  7:38     ` Geert Uytterhoeven
2020-05-11  7:38     ` Geert Uytterhoeven
2020-05-11  7:38     ` Geert Uytterhoeven
2020-05-11  7:38     ` Geert Uytterhoeven
2020-05-10  7:55 ` [PATCH 27/31] exec: only build read_code when needed Christoph Hellwig
2020-05-10  7:55   ` [OpenRISC] " Christoph Hellwig
2020-05-10  7:55   ` Christoph Hellwig
2020-05-10  7:55   ` Christoph Hellwig
2020-05-10  7:55   ` Christoph Hellwig
2020-05-10  7:55 ` [PATCH 28/31] exec: use flush_icache_user_range in read_code Christoph Hellwig
2020-05-10  7:55   ` [OpenRISC] " Christoph Hellwig
2020-05-10  7:55   ` Christoph Hellwig
2020-05-10  7:55   ` Christoph Hellwig
2020-05-10  7:55   ` Christoph Hellwig
2020-05-10  7:55 ` [PATCH 29/31] binfmt_flat: use flush_icache_user_range Christoph Hellwig
2020-05-10  7:55   ` [OpenRISC] " Christoph Hellwig
2020-05-10  7:55   ` Christoph Hellwig
2020-05-10  7:55   ` Christoph Hellwig
2020-05-10  7:55   ` Christoph Hellwig
2020-05-12 14:46   ` Greg Ungerer
2020-05-12 14:46     ` [OpenRISC] " Greg Ungerer
2020-05-12 14:46     ` Greg Ungerer
2020-05-12 14:46     ` Greg Ungerer
2020-05-12 14:46     ` Greg Ungerer
2020-05-10  7:55 ` [PATCH 30/31] nommu: use flush_icache_user_range in brk and mmap Christoph Hellwig
2020-05-10  7:55   ` [OpenRISC] " Christoph Hellwig
2020-05-10  7:55   ` Christoph Hellwig
2020-05-10  7:55   ` Christoph Hellwig
2020-05-10  7:55   ` Christoph Hellwig
2020-05-10  7:55 ` [PATCH 31/31] module: move the set_fs hack for flush_icache_range to m68k Christoph Hellwig
2020-05-10  7:55   ` [OpenRISC] " Christoph Hellwig
2020-05-10  7:55   ` Christoph Hellwig
2020-05-10  7:55   ` Christoph Hellwig
2020-05-10  7:55   ` Christoph Hellwig
2020-05-11  7:40   ` Geert Uytterhoeven
2020-05-11  7:40     ` [OpenRISC] " Geert Uytterhoeven
2020-05-11  7:40     ` Geert Uytterhoeven
2020-05-11  7:40     ` Geert Uytterhoeven
2020-05-11  7:40     ` Geert Uytterhoeven
2020-05-11  7:40     ` Geert Uytterhoeven
2020-05-11  7:40     ` Geert Uytterhoeven
2020-05-11  7:40     ` Geert Uytterhoeven
2020-05-11 15:11     ` Christoph Hellwig
2020-05-11 15:11       ` [OpenRISC] " Christoph Hellwig
2020-05-11 15:11       ` Christoph Hellwig
2020-05-11 15:11       ` Christoph Hellwig
2020-05-11 15:11       ` Christoph Hellwig
2020-05-11 15:11       ` Christoph Hellwig
2020-05-11 15:11       ` Christoph Hellwig
2020-05-11 15:24       ` Geert Uytterhoeven
2020-05-11 15:24         ` [OpenRISC] " Geert Uytterhoeven
2020-05-11 15:24         ` Geert Uytterhoeven
2020-05-11 15:24         ` Geert Uytterhoeven
2020-05-11 15:24         ` Geert Uytterhoeven
2020-05-11 15:24         ` Geert Uytterhoeven
2020-05-11 15:24         ` Geert Uytterhoeven
2020-05-11 15:24         ` Geert Uytterhoeven
2020-05-11 16:37         ` Christoph Hellwig [this message]
2020-05-11 16:37           ` [OpenRISC] " Christoph Hellwig
2020-05-11 16:37           ` Christoph Hellwig
2020-05-11 16:37           ` Christoph Hellwig
2020-05-11 16:37           ` Christoph Hellwig
2020-05-11 16:37           ` Christoph Hellwig
2020-05-11 16:37           ` Christoph Hellwig
2020-05-11  7:46 ` sort out the flush_icache_range mess Geert Uytterhoeven
2020-05-11  7:46   ` [OpenRISC] " Geert Uytterhoeven
2020-05-11  7:46   ` Geert Uytterhoeven
2020-05-11  7:46   ` Geert Uytterhoeven
2020-05-11  7:46   ` Geert Uytterhoeven
2020-05-11  7:46   ` Geert Uytterhoeven
2020-05-11  7:46   ` Geert Uytterhoeven
2020-05-11  7:46   ` Geert Uytterhoeven
2020-05-11 15:13   ` Christoph Hellwig
2020-05-11 15:13     ` [OpenRISC] " Christoph Hellwig
2020-05-11 15:13     ` Christoph Hellwig
2020-05-11 15:13     ` Christoph Hellwig
2020-05-11 15:13     ` Christoph Hellwig
2020-05-11 15:13     ` Christoph Hellwig
2020-05-11 15:13     ` Christoph Hellwig
2020-05-11 15:25     ` Geert Uytterhoeven
2020-05-11 15:25       ` [OpenRISC] " Geert Uytterhoeven
2020-05-11 15:25       ` Geert Uytterhoeven
2020-05-11 15:25       ` Geert Uytterhoeven
2020-05-11 15:25       ` Geert Uytterhoeven
2020-05-11 15:25       ` Geert Uytterhoeven
2020-05-11 15:25       ` Geert Uytterhoeven
2020-05-11 15:25       ` Geert Uytterhoeven
2020-05-11 16:35       ` Christoph Hellwig
2020-05-11 16:35         ` [OpenRISC] " Christoph Hellwig
2020-05-11 16:35         ` Christoph Hellwig
2020-05-11 16:35         ` Christoph Hellwig
2020-05-11 16:35         ` Christoph Hellwig
2020-05-11 16:35         ` Christoph Hellwig
2020-05-11 16:35         ` Christoph Hellwig

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