From: Sylwester Nawrocki <s.nawrocki@samsung.com>
To: u-boot@lists.denx.de
Subject: [PATCH v3 7/9] pci: Add some PCI Express capability register offset definitions
Date: Tue, 12 May 2020 20:47:14 +0200 [thread overview]
Message-ID: <20200512184716.2869-8-s.nawrocki@samsung.com> (raw)
In-Reply-To: <20200512184716.2869-1-s.nawrocki@samsung.com>
Add PCI Express capability definitions required by the Broadcom
STB PCIe controller driver.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
---
Changes since v2:
- added Current Link Speed defines.
Changes since v1:
- none.
Changes since RFC:
- ensure the entries are added in order, sorted by ascending
address values.
---
include/pci.h | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/include/pci.h b/include/pci.h
index dfdbb32..ff5f620 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -479,11 +479,20 @@
#define PCI_EXP_DEVCTL 8 /* Device Control */
#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */
#define PCI_EXP_LNKCAP 12 /* Link Capabilities */
+#define PCI_EXP_LNKCAP_SLS 0x0000000f /* Supported Link Speeds */
+#define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */
#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */
#define PCI_EXP_LNKSTA 18 /* Link Status */
+#define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */
+#define PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 /* Current Link Speed 2.5GT/s */
+#define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */
+#define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */
+#define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */
+#define PCI_EXP_LNKSTA_NLW_SHIFT 4 /* start of NLW mask in link status */
#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */
#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */
#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */
+#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */
/* Include the ID list */
--
2.7.4
next prev parent reply other threads:[~2020-05-12 18:47 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20200512184724eucas1p24bb9730834234cebf5061a614c2c8c54@eucas1p2.samsung.com>
2020-05-12 18:47 ` [PATCH v3 0/9] USB host support for Raspberry Pi 4 board (64-bit) Sylwester Nawrocki
[not found] ` <CGME20200512184740eucas1p2912f07b9e34cc769604d641adb0e13c9@eucas1p2.samsung.com>
2020-05-12 18:47 ` [PATCH v3 1/9] usb: xhci: Add missing cache flush in the scratchpad array initialization Sylwester Nawrocki
[not found] ` <CGME20200512184743eucas1p28e9d93ba5e46ed900a88bf0bf85fda58@eucas1p2.samsung.com>
2020-05-12 18:47 ` [PATCH v3 2/9] usb: xhci: Use only 32-bit accesses in xhci_writeq/xhci_readq Sylwester Nawrocki
[not found] ` <CGME20200512184747eucas1p25ed7fb872416271dd34806ccfb4197e5@eucas1p2.samsung.com>
2020-05-12 18:47 ` [PATCH v3 3/9] pci: Move some PCIe register offset definitions to a common header Sylwester Nawrocki
[not found] ` <CGME20200512184829eucas1p10c67592f9af7879f51eee9bff8fa76d7@eucas1p1.samsung.com>
2020-05-12 18:47 ` [PATCH v3 4/9] rpi4: shorten a mapping for the DRAM Sylwester Nawrocki
[not found] ` <CGME20200512184830eucas1p198b1439122e2da299c563726fe17f9ef@eucas1p1.samsung.com>
2020-05-12 18:47 ` [PATCH v3 5/9] rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM 64bit) Sylwester Nawrocki
[not found] ` <CGME20200512184832eucas1p1b75fca7f5ed42e3cb38f98410f51f1ad@eucas1p1.samsung.com>
2020-05-12 18:47 ` [PATCH v3 6/9] linux/bitfield.h: Add primitives for manipulating bitfields both in host- and fixed-endian Sylwester Nawrocki
[not found] ` <CGME20200512190442eucas1p278509fbc3a5d4bc7303797e5b8b284d6@eucas1p2.samsung.com>
2020-05-12 19:04 ` [RESEND PATCH " Sylwester Nawrocki
[not found] ` <CGME20200512184836eucas1p2f357a332cd99d6e287a74405d75c0985@eucas1p2.samsung.com>
2020-05-12 18:47 ` Sylwester Nawrocki [this message]
[not found] ` <CGME20200512184838eucas1p249588f9ee76dcb5a10209fcb7de01fae@eucas1p2.samsung.com>
2020-05-12 18:47 ` [PATCH v3 8/9] pci: Add driver for Broadcom BCM2711 SoC PCIe controller Sylwester Nawrocki
[not found] ` <CGME20200512184842eucas1p1b2edc2128ddf134553805db77451648f@eucas1p1.samsung.com>
2020-05-12 18:47 ` [PATCH v3 9/9] configs: Enable support for the XHCI controller on RPI4 board (ARM 64-bit) Sylwester Nawrocki
2020-05-13 9:21 ` Sylwester Nawrocki
2020-05-24 18:30 ` Matthias Brugger
2020-05-25 9:25 ` Sylwester Nawrocki
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