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From: Matt Roper <matthew.d.roper@intel.com>
To: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v3 07/15] drm/i915/rkl: Update TGP's pin mapping when paired with RKL
Date: Thu, 4 Jun 2020 16:18:49 -0700	[thread overview]
Message-ID: <20200604231849.GE3023929@mdroper-desk1.amr.corp.intel.com> (raw)
In-Reply-To: <20200604182919.GB6112@intel.com>

On Thu, Jun 04, 2020 at 09:29:19PM +0300, Ville Syrjälä wrote:
> On Wed, Jun 03, 2020 at 02:15:21PM -0700, Matt Roper wrote:
> > When TGP is paired with RKL it uses a different HPD pin mapping than
> > when paired with TGL.
> > 
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_irq.c | 15 ++++++++++++++-
> >  1 file changed, 14 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> > index 490574669eaa..f3ea81a17352 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -167,6 +167,17 @@ static const u32 hpd_tgp[HPD_NUM_PINS] = {
> >  	[HPD_PORT_I] = SDE_TC_HOTPLUG_ICP(PORT_TC6),
> >  };
> >  
> > +/*
> > + * TGP when paired with RKL has different pin mappings than when paired
> > + * with TGL.
> > + */
> > +static const u32 hpd_rkl_tgp[HPD_NUM_PINS] = {
> > +	[HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PORT_A),
> > +	[HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PORT_B),
> > +	[HPD_PORT_C] = SDE_TC_HOTPLUG_ICP(PORT_TC1),
> > +	[HPD_PORT_D] = SDE_TC_HOTPLUG_ICP(PORT_TC2),
> > +};
> 
> Hmm. So basically it looks like we'd want to pick the hpd_pin
> based on the DDI rather than the PHY on this platform?

I may be misinterpreting the table on bspec 49181, but I *think* it
looks like we use the DDI when paired with a TGP PCH and the PHY when
paired with CMP PCH.  So if I just set the hpd_pin based on the DDI,
then I think that will break the CMP-based systems (although I haven't
tested on one of those, so I'm not 100% sure).


Matt

> 
> OK, I guess we need to remap somehow. The question is
> whether we want to do it before or after selecting hpd_pin...
> I think we would want to do it before, as otherwise the
> long_detect() stuff won't work right AFAICS. Or am I
> missing something?
> 
> Side note: we should probably convert the long_detect()
> switches to arrays just like we have for the isr bits here.
> Would potentially avoid having to touch that code every time
> they tweak these thinhs in hw.
> 
> And in fact it looks like icp already has all the same hpd
> pins as tgp, so I'm thinking we should just s/hpd_tgp/hpd_icp/
> and for icl/jsl we should remap hpd_pin as well. Oh and the
> mcc case would just need a slightly different mapping of
> port C -> HPD_PORT_D (aka. tc1).
> 
> This way all the hpd[] arrays and whatnot would just be based
> on the actual pch type and not based on what it happens to be
> paired with.
> 
> Anwyays, most of that is out of scope for this rkl stuff, so
> I guess for now just add a bit of logic to remap hpd_pin for rkl?
> 
> > +
> >  static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
> >  {
> >  	struct i915_hotplug *hpd = &dev_priv->hotplug;
> > @@ -196,7 +207,9 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
> >  	if (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv))
> >  		return;
> >  
> > -	if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv))
> > +	if (HAS_PCH_TGP(dev_priv) && IS_ROCKETLAKE(dev_priv))
> > +		hpd->pch_hpd = hpd_rkl_tgp;
> > +	else if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv))
> >  		hpd->pch_hpd = hpd_tgp;
> >  	else if (HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv))
> >  		hpd->pch_hpd = hpd_icp;
> > -- 
> > 2.24.1
> 
> -- 
> Ville Syrjälä
> Intel

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2020-06-04 23:18 UTC|newest]

Thread overview: 41+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-03 21:15 [Intel-gfx] [PATCH v3 00/15] Remaining RKL patches Matt Roper
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 01/15] drm/i915/rkl: Set transcoder mask properly Matt Roper
2020-06-04 15:34   ` Ville Syrjälä
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 02/15] drm/i915/rkl: Program BW_BUDDY0 registers instead of BW_BUDDY1/2 Matt Roper
2020-06-03 22:34   ` Aditya Swarup
2020-06-03 23:12     ` Matt Roper
2020-06-04  1:18       ` Aditya Swarup
2020-06-04 17:01   ` Ville Syrjälä
2020-06-04 22:12     ` Matt Roper
2020-06-05 11:43       ` Ville Syrjälä
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 03/15] drm/i915/rkl: RKL has no MBUS_ABOX_CTL{1, 2} Matt Roper
2020-06-04 18:31   ` Ville Syrjälä
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 04/15] drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout Matt Roper
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 05/15] drm/i915/rkl: Setup ports/phys Matt Roper
2020-06-04 17:09   ` Ville Syrjälä
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 06/15] drm/i915/rkl: provide port/phy mapping for vbt Matt Roper
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 07/15] drm/i915/rkl: Update TGP's pin mapping when paired with RKL Matt Roper
2020-06-04 18:29   ` Ville Syrjälä
2020-06-04 23:18     ` Matt Roper [this message]
2020-06-05 11:52       ` Ville Syrjälä
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 08/15] drm/i915/rkl: Add DDC pin mapping Matt Roper
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 09/15] drm/i915/rkl: Don't try to access transcoder D Matt Roper
2020-06-04 16:55   ` Ville Syrjälä
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 10/15] drm/i915/rkl: Don't try to read out DSI transcoders Matt Roper
2020-06-04 16:59   ` Ville Syrjälä
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 11/15] drm/i915/rkl: Handle comp master/slave relationships for PHYs Matt Roper
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 12/15] drm/i915/rkl: Add DPLL4 support Matt Roper
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 13/15] drm/i915/rkl: Handle HTI Matt Roper
2020-06-04 16:59   ` Ville Syrjälä
2020-06-04 22:55     ` Matt Roper
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 14/15] drm/i915/rkl: Disable PSR2 Matt Roper
2020-06-04 17:41   ` Rodrigo Vivi
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 15/15] drm/i915/rkl: Add initial workarounds Matt Roper
2020-06-03 22:02 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Remaining RKL patches Patchwork
2020-06-03 22:03 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-06-03 22:23 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-06-04  8:34 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-06-04 16:39   ` Matt Roper
2020-06-05 22:11     ` Chris Wilson
2020-06-06  3:21       ` Matt Roper
2020-06-06  9:01         ` Chris Wilson

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