* [Intel-gfx] [PATCH v2 01/32] drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout
2020-06-18 0:42 [Intel-gfx] [PATCH v2 00/32] Introduce DG1 Lucas De Marchi
@ 2020-06-18 0:42 ` Lucas De Marchi
2020-06-23 23:40 ` Souza, Jose
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 02/32] drm/i915/rkl: Add DPLL4 support Lucas De Marchi
` (33 subsequent siblings)
34 siblings, 1 reply; 48+ messages in thread
From: Lucas De Marchi @ 2020-06-18 0:42 UTC (permalink / raw)
To: intel-gfx
From: Matt Roper <matthew.d.roper@intel.com>
RKL uses a slightly different bit layout for the DPCLKA_CFGCR0 register.
v2:
- Fix inverted mask application when updating ICL_DPCLKA_CFGCR0
- Checkpatch style fixes
Bspec: 50287
Cc: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 18 +++++++++++++++---
drivers/gpu/drm/i915/display/intel_display.c | 15 ++++++++++++---
drivers/gpu/drm/i915/i915_reg.h | 6 ++++++
3 files changed, 33 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index ca7bb2294d2b6..8790f221dc77c 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2770,7 +2770,9 @@ hsw_set_signal_levels(struct intel_dp *intel_dp)
static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
enum phy phy)
{
- if (intel_phy_is_combo(dev_priv, phy)) {
+ if (IS_ROCKETLAKE(dev_priv)) {
+ return RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
+ } else if (intel_phy_is_combo(dev_priv, phy)) {
return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
} else if (intel_phy_is_tc(dev_priv, phy)) {
enum tc_port tc_port = intel_port_to_tc(dev_priv,
@@ -2797,6 +2799,16 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder,
(val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);
if (intel_phy_is_combo(dev_priv, phy)) {
+ u32 mask, sel;
+
+ if (IS_ROCKETLAKE(dev_priv)) {
+ mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+ sel = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
+ } else {
+ mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+ sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
+ }
+
/*
* Even though this register references DDIs, note that we
* want to pass the PHY rather than the port (DDI). For
@@ -2807,8 +2819,8 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder,
* Clock Select chooses the PLL for both DDIA and DDID and
* drives port A in all cases."
*/
- val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
- val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
+ val &= ~mask;
+ val |= sel;
intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 7457813ef2733..6c2bb3354b869 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -10785,9 +10785,18 @@ static void icl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
u32 temp;
if (intel_phy_is_combo(dev_priv, phy)) {
- temp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0) &
- ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
- id = temp >> ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
+ u32 mask, shift;
+
+ if (IS_ROCKETLAKE(dev_priv)) {
+ mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+ shift = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
+ } else {
+ mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+ shift = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
+ }
+
+ temp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0) & mask;
+ id = temp >> shift;
port_dpll_id = ICL_PORT_DPLL_DEFAULT;
} else if (intel_phy_is_tc(dev_priv, phy)) {
u32 clk_sel = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f09120cac89aa..45bda5819abd0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10195,12 +10195,18 @@ enum skl_power_gate {
#define ICL_DPCLKA_CFGCR0 _MMIO(0x164280)
#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24))
+#define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10)
#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < PORT_TC4 ? \
(tc_port) + 12 : \
(tc_port) - PORT_TC4 + 21))
#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2)
#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
+#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) _PICK(phy, 0, 2, 4, 27)
+#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) \
+ (3 << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
+#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) \
+ ((pll) << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
/* CNL PLL */
#define DPLL0_ENABLE 0x46010
--
2.26.2
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^ permalink raw reply related [flat|nested] 48+ messages in thread* Re: [Intel-gfx] [PATCH v2 01/32] drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 01/32] drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout Lucas De Marchi
@ 2020-06-23 23:40 ` Souza, Jose
0 siblings, 0 replies; 48+ messages in thread
From: Souza, Jose @ 2020-06-23 23:40 UTC (permalink / raw)
To: intel-gfx, De Marchi, Lucas
On Wed, 2020-06-17 at 17:42 -0700, Lucas De Marchi wrote:
> From: Matt Roper <matthew.d.roper@intel.com>
>
> RKL uses a slightly different bit layout for the DPCLKA_CFGCR0 register.
>
> v2:
> - Fix inverted mask application when updating ICL_DPCLKA_CFGCR0
> - Checkpatch style fixes
>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> Bspec: 50287
> Cc: Aditya Swarup <aditya.swarup@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 18 +++++++++++++++---
> drivers/gpu/drm/i915/display/intel_display.c | 15 ++++++++++++---
> drivers/gpu/drm/i915/i915_reg.h | 6 ++++++
> 3 files changed, 33 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index ca7bb2294d2b6..8790f221dc77c 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2770,7 +2770,9 @@ hsw_set_signal_levels(struct intel_dp *intel_dp)
> static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
> enum phy phy)
> {
> - if (intel_phy_is_combo(dev_priv, phy)) {
> + if (IS_ROCKETLAKE(dev_priv)) {
> + return RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
> + } else if (intel_phy_is_combo(dev_priv, phy)) {
> return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
> } else if (intel_phy_is_tc(dev_priv, phy)) {
> enum tc_port tc_port = intel_port_to_tc(dev_priv,
> @@ -2797,6 +2799,16 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder,
> (val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);
>
> if (intel_phy_is_combo(dev_priv, phy)) {
> + u32 mask, sel;
> +
> + if (IS_ROCKETLAKE(dev_priv)) {
> + mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
> + sel = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
> + } else {
> + mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
> + sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
> + }
> +
> /*
> * Even though this register references DDIs, note that we
> * want to pass the PHY rather than the port (DDI). For
> @@ -2807,8 +2819,8 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder,
> * Clock Select chooses the PLL for both DDIA and DDID and
> * drives port A in all cases."
> */
> - val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
> - val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
> + val &= ~mask;
> + val |= sel;
> intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
> intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 7457813ef2733..6c2bb3354b869 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -10785,9 +10785,18 @@ static void icl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
> u32 temp;
>
> if (intel_phy_is_combo(dev_priv, phy)) {
> - temp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0) &
> - ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
> - id = temp >> ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
> + u32 mask, shift;
> +
> + if (IS_ROCKETLAKE(dev_priv)) {
> + mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
> + shift = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
> + } else {
> + mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
> + shift = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
> + }
> +
> + temp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0) & mask;
> + id = temp >> shift;
> port_dpll_id = ICL_PORT_DPLL_DEFAULT;
> } else if (intel_phy_is_tc(dev_priv, phy)) {
> u32 clk_sel = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f09120cac89aa..45bda5819abd0 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10195,12 +10195,18 @@ enum skl_power_gate {
>
> #define ICL_DPCLKA_CFGCR0 _MMIO(0x164280)
> #define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24))
> +#define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10)
> #define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < PORT_TC4 ? \
> (tc_port) + 12 : \
> (tc_port) - PORT_TC4 + 21))
> #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2)
> #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
> #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
> +#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) _PICK(phy, 0, 2, 4, 27)
> +#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) \
> + (3 << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
> +#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) \
> + ((pll) << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
>
> /* CNL PLL */
> #define DPLL0_ENABLE 0x46010
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^ permalink raw reply [flat|nested] 48+ messages in thread
* [Intel-gfx] [PATCH v2 02/32] drm/i915/rkl: Add DPLL4 support
2020-06-18 0:42 [Intel-gfx] [PATCH v2 00/32] Introduce DG1 Lucas De Marchi
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 01/32] drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout Lucas De Marchi
@ 2020-06-18 0:42 ` Lucas De Marchi
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 03/32] drm/i915/rkl: Handle HTI Lucas De Marchi
` (32 subsequent siblings)
34 siblings, 0 replies; 48+ messages in thread
From: Lucas De Marchi @ 2020-06-18 0:42 UTC (permalink / raw)
To: intel-gfx
From: Matt Roper <matthew.d.roper@intel.com>
Rocket Lake has a third DPLL (called 'DPLL4') that must be used to
enable a third display. Unlike EHL's variant of DPLL4, the RKL variant
behaves the same as DPLL0/1. And despite its name, the DPLL4 registers
are offset as if it were DPLL2.
To allow the TGL register selectors like TGL_DPLL_CFGCR0 to be used
seamlessly on all gen12 platforms, we set the non-MG PLL ID's to match
how the registers are laid out: DPLL0, DPLL1, DPLL4 (RKL-only), TBT.
This means just renumbering TBT to be ID '3' rather than being another
ID '2' like DPLL4. With this change, we can build our register
selectors with _MMIO_PLL rather than _MMIO_PLL3 since the register
offsets are evenly-spaced. MGPLL's don't need any specific ID's
(they're just used to translate back to a tc_port), so we let them float
at the top of the enum.
v2:
- Add new .update_ref_clks() hook.
v3:
- Renumber TBT PLL to '3' and switch _MMIO_PLL3 to _MMIO_PLL (Lucas)
Bspec: 49202
Bspec: 49443
Bspec: 50288
Bspec: 50289
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 29 +++++++++++++++++--
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 14 ++++-----
drivers/gpu/drm/i915/i915_reg.h | 15 +++-------
3 files changed, 37 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index b45185b80bec5..b5f4d4cef682b 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3506,13 +3506,19 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state,
return false;
}
- if (IS_ELKHARTLAKE(dev_priv) && port != PORT_A)
+ if (IS_ROCKETLAKE(dev_priv)) {
dpll_mask =
BIT(DPLL_ID_EHL_DPLL4) |
BIT(DPLL_ID_ICL_DPLL1) |
BIT(DPLL_ID_ICL_DPLL0);
- else
+ } else if (IS_ELKHARTLAKE(dev_priv) && port != PORT_A) {
+ dpll_mask =
+ BIT(DPLL_ID_EHL_DPLL4) |
+ BIT(DPLL_ID_ICL_DPLL1) |
+ BIT(DPLL_ID_ICL_DPLL0);
+ } else {
dpll_mask = BIT(DPLL_ID_ICL_DPLL1) | BIT(DPLL_ID_ICL_DPLL0);
+ }
port_dpll->pll = intel_find_shared_dpll(state, crtc,
&port_dpll->hw_state,
@@ -4275,6 +4281,21 @@ static const struct intel_dpll_mgr tgl_pll_mgr = {
.dump_hw_state = icl_dump_hw_state,
};
+static const struct dpll_info rkl_plls[] = {
+ { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
+ { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
+ { "DPLL 4", &combo_pll_funcs, DPLL_ID_EHL_DPLL4, 0 },
+ { },
+};
+
+static const struct intel_dpll_mgr rkl_pll_mgr = {
+ .dpll_info = rkl_plls,
+ .get_dplls = icl_get_dplls,
+ .put_dplls = icl_put_dplls,
+ .update_ref_clks = icl_update_dpll_ref_clks,
+ .dump_hw_state = icl_dump_hw_state,
+};
+
/**
* intel_shared_dpll_init - Initialize shared DPLLs
* @dev: drm device
@@ -4288,7 +4309,9 @@ void intel_shared_dpll_init(struct drm_device *dev)
const struct dpll_info *dpll_info;
int i;
- if (INTEL_GEN(dev_priv) >= 12)
+ if (IS_ROCKETLAKE(dev_priv))
+ dpll_mgr = &rkl_pll_mgr;
+ else if (INTEL_GEN(dev_priv) >= 12)
dpll_mgr = &tgl_pll_mgr;
else if (IS_ELKHARTLAKE(dev_priv))
dpll_mgr = &ehl_pll_mgr;
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 5d9a2bc371e7c..49367847bfb55 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -125,35 +125,35 @@ enum intel_dpll_id {
/**
* @DPLL_ID_ICL_TBTPLL: ICL/TGL TBT PLL
*/
- DPLL_ID_ICL_TBTPLL = 2,
+ DPLL_ID_ICL_TBTPLL = 3,
/**
* @DPLL_ID_ICL_MGPLL1: ICL MG PLL 1 port 1 (C),
* TGL TC PLL 1 port 1 (TC1)
*/
- DPLL_ID_ICL_MGPLL1 = 3,
+ DPLL_ID_ICL_MGPLL1,
/**
* @DPLL_ID_ICL_MGPLL2: ICL MG PLL 1 port 2 (D)
* TGL TC PLL 1 port 2 (TC2)
*/
- DPLL_ID_ICL_MGPLL2 = 4,
+ DPLL_ID_ICL_MGPLL2,
/**
* @DPLL_ID_ICL_MGPLL3: ICL MG PLL 1 port 3 (E)
* TGL TC PLL 1 port 3 (TC3)
*/
- DPLL_ID_ICL_MGPLL3 = 5,
+ DPLL_ID_ICL_MGPLL3,
/**
* @DPLL_ID_ICL_MGPLL4: ICL MG PLL 1 port 4 (F)
* TGL TC PLL 1 port 4 (TC4)
*/
- DPLL_ID_ICL_MGPLL4 = 6,
+ DPLL_ID_ICL_MGPLL4,
/**
* @DPLL_ID_TGL_MGPLL5: TGL TC PLL port 5 (TC5)
*/
- DPLL_ID_TGL_MGPLL5 = 7,
+ DPLL_ID_TGL_MGPLL5,
/**
* @DPLL_ID_TGL_MGPLL6: TGL TC PLL port 6 (TC6)
*/
- DPLL_ID_TGL_MGPLL6 = 8,
+ DPLL_ID_TGL_MGPLL6,
};
#define I915_NUM_PLLS 9
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 45bda5819abd0..34f8698ac3aa6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -242,7 +242,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
#define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
#define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
-#define _MMIO_PLL3(pll, a, b, c) _MMIO(_PICK(pll, a, b, c))
/*
* Device info offset array based helpers for groups of registers with unevenly
@@ -10427,19 +10426,13 @@ enum skl_power_gate {
#define _TGL_DPLL0_CFGCR0 0x164284
#define _TGL_DPLL1_CFGCR0 0x16428C
-/* TODO: add DPLL4 */
-#define _TGL_TBTPLL_CFGCR0 0x16429C
-#define TGL_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
- _TGL_DPLL1_CFGCR0, \
- _TGL_TBTPLL_CFGCR0)
+#define TGL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR0, \
+ _TGL_DPLL1_CFGCR0)
#define _TGL_DPLL0_CFGCR1 0x164288
#define _TGL_DPLL1_CFGCR1 0x164290
-/* TODO: add DPLL4 */
-#define _TGL_TBTPLL_CFGCR1 0x1642A0
-#define TGL_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
- _TGL_DPLL1_CFGCR1, \
- _TGL_TBTPLL_CFGCR1)
+#define TGL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \
+ _TGL_DPLL1_CFGCR1)
#define _DKL_PHY1_BASE 0x168000
#define _DKL_PHY2_BASE 0x169000
--
2.26.2
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^ permalink raw reply related [flat|nested] 48+ messages in thread* [Intel-gfx] [PATCH v2 03/32] drm/i915/rkl: Handle HTI
2020-06-18 0:42 [Intel-gfx] [PATCH v2 00/32] Introduce DG1 Lucas De Marchi
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 01/32] drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout Lucas De Marchi
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 02/32] drm/i915/rkl: Add DPLL4 support Lucas De Marchi
@ 2020-06-18 0:42 ` Lucas De Marchi
2020-06-23 23:56 ` Souza, Jose
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 04/32] drm/i915/rkl: Add initial workarounds Lucas De Marchi
` (31 subsequent siblings)
34 siblings, 1 reply; 48+ messages in thread
From: Lucas De Marchi @ 2020-06-18 0:42 UTC (permalink / raw)
To: intel-gfx
From: Matt Roper <matthew.d.roper@intel.com>
If HTI (also sometimes called HDPORT) is enabled at startup, it may be
using some of the PHYs and DPLLs making them unavailable for general
usage. Let's read out the HDPORT_STATE register and avoid making use of
resources that HTI is already using.
v2:
- Fix minor checkpatch warnings
Bspec: 49189
Bspec: 53707
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 30 ++++++++++++++++---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 21 +++++++++++++
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 1 +
drivers/gpu/drm/i915/i915_drv.h | 3 ++
drivers/gpu/drm/i915/i915_reg.h | 6 ++++
5 files changed, 57 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 6c2bb3354b869..f16512eddc587 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -46,6 +46,7 @@
#include "display/intel_ddi.h"
#include "display/intel_dp.h"
#include "display/intel_dp_mst.h"
+#include "display/intel_dpll_mgr.h"
#include "display/intel_dsi.h"
#include "display/intel_dvo.h"
#include "display/intel_gmbus.h"
@@ -16814,6 +16815,13 @@ static void intel_pps_init(struct drm_i915_private *dev_priv)
intel_pps_unlock_regs_wa(dev_priv);
}
+static bool hti_uses_phy(u32 hdport_state, enum phy phy)
+{
+ return hdport_state & HDPORT_ENABLED &&
+ (hdport_state & HDPORT_PHY_USED_DP(phy) ||
+ hdport_state & HDPORT_PHY_USED_HDMI(phy));
+}
+
static void intel_setup_outputs(struct drm_i915_private *dev_priv)
{
struct intel_encoder *encoder;
@@ -16825,10 +16833,22 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
return;
if (IS_ROCKETLAKE(dev_priv)) {
- intel_ddi_init(dev_priv, PORT_A);
- intel_ddi_init(dev_priv, PORT_B);
- intel_ddi_init(dev_priv, PORT_D); /* DDI TC1 */
- intel_ddi_init(dev_priv, PORT_E); /* DDI TC2 */
+ /*
+ * If HTI (aka HDPORT) is enabled at boot, it may have taken
+ * over some of the PHYs and made them unavailable to the
+ * driver. In that case we should skip initializing the
+ * corresponding outputs.
+ */
+ u32 hdport_state = intel_de_read(dev_priv, HDPORT_STATE);
+
+ if (!hti_uses_phy(hdport_state, PHY_A))
+ intel_ddi_init(dev_priv, PORT_A);
+ if (!hti_uses_phy(hdport_state, PHY_B))
+ intel_ddi_init(dev_priv, PORT_B);
+ if (!hti_uses_phy(hdport_state, PHY_C))
+ intel_ddi_init(dev_priv, PORT_D); /* DDI TC1 */
+ if (!hti_uses_phy(hdport_state, PHY_D))
+ intel_ddi_init(dev_priv, PORT_E); /* DDI TC2 */
} else if (INTEL_GEN(dev_priv) >= 12) {
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
@@ -18376,6 +18396,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
intel_dpll_readout_hw_state(dev_priv);
+ dev_priv->hti_pll_mask = intel_get_hti_plls(dev_priv);
+
for_each_intel_encoder(dev, encoder) {
pipe = 0;
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index b5f4d4cef682b..6f59f9ec453bf 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -265,6 +265,24 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
mutex_unlock(&dev_priv->dpll.lock);
}
+/*
+ * HTI (aka HDPORT) may be using some of the platform's PLL's, making them
+ * unavailable for use.
+ */
+u32 intel_get_hti_plls(struct drm_i915_private *dev_priv)
+{
+ u32 hdport_state;
+
+ if (!IS_ROCKETLAKE(dev_priv))
+ return 0;
+
+ hdport_state = intel_de_read(dev_priv, HDPORT_STATE);
+ if (!(hdport_state & HDPORT_ENABLED))
+ return 0;
+
+ return REG_FIELD_GET(HDPORT_DPLL_USED_MASK, hdport_state);
+}
+
static struct intel_shared_dpll *
intel_find_shared_dpll(struct intel_atomic_state *state,
const struct intel_crtc *crtc,
@@ -280,6 +298,9 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
drm_WARN_ON(&dev_priv->drm, dpll_mask & ~(BIT(I915_NUM_PLLS) - 1));
+ /* Eliminate DPLLs from consideration if reserved by HTI */
+ dpll_mask &= ~dev_priv->hti_pll_mask;
+
for_each_set_bit(i, &dpll_mask, I915_NUM_PLLS) {
pll = &dev_priv->dpll.shared_dplls[i];
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 49367847bfb55..edcc43f4670ff 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -390,6 +390,7 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state);
void intel_shared_dpll_init(struct drm_device *dev);
void intel_dpll_readout_hw_state(struct drm_i915_private *dev_priv);
void intel_dpll_sanitize_state(struct drm_i915_private *dev_priv);
+u32 intel_get_hti_plls(struct drm_i915_private *dev_priv);
void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
const struct intel_dpll_hw_state *hw_state);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5649f8e502fef..b836032fa0deb 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1037,6 +1037,9 @@ struct drm_i915_private {
struct intel_l3_parity l3_parity;
+ /* Mask of PLLs reserved for use by HTI and unavailable to driver. */
+ u32 hti_pll_mask;
+
/*
* edram size in MB.
* Cannot be determined by PCIID. You must always read a register.
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 34f8698ac3aa6..34b2ec04ccd86 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2908,6 +2908,12 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define MBUS_BBOX_CTL_S1 _MMIO(0x45040)
#define MBUS_BBOX_CTL_S2 _MMIO(0x45044)
+#define HDPORT_STATE _MMIO(0x45050)
+#define HDPORT_DPLL_USED_MASK REG_GENMASK(14, 12)
+#define HDPORT_PHY_USED_DP(phy) REG_BIT(2 * (phy) + 2)
+#define HDPORT_PHY_USED_HDMI(phy) REG_BIT(2 * (phy) + 1)
+#define HDPORT_ENABLED REG_BIT(0)
+
/* Make render/texture TLB fetches lower priorty than associated data
* fetches. This is not turned on by default
*/
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 48+ messages in thread* Re: [Intel-gfx] [PATCH v2 03/32] drm/i915/rkl: Handle HTI
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 03/32] drm/i915/rkl: Handle HTI Lucas De Marchi
@ 2020-06-23 23:56 ` Souza, Jose
0 siblings, 0 replies; 48+ messages in thread
From: Souza, Jose @ 2020-06-23 23:56 UTC (permalink / raw)
To: intel-gfx, De Marchi, Lucas
On Wed, 2020-06-17 at 17:42 -0700, Lucas De Marchi wrote:
> From: Matt Roper <matthew.d.roper@intel.com>
>
> If HTI (also sometimes called HDPORT) is enabled at startup, it may be
> using some of the PHYs and DPLLs making them unavailable for general
> usage. Let's read out the HDPORT_STATE register and avoid making use of
> resources that HTI is already using.
>
> v2:
> - Fix minor checkpatch warnings
>
> Bspec: 49189
> Bspec: 53707
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 30 ++++++++++++++++---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 21 +++++++++++++
> drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 1 +
> drivers/gpu/drm/i915/i915_drv.h | 3 ++
> drivers/gpu/drm/i915/i915_reg.h | 6 ++++
> 5 files changed, 57 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 6c2bb3354b869..f16512eddc587 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -46,6 +46,7 @@
> #include "display/intel_ddi.h"
> #include "display/intel_dp.h"
> #include "display/intel_dp_mst.h"
> +#include "display/intel_dpll_mgr.h"
> #include "display/intel_dsi.h"
> #include "display/intel_dvo.h"
> #include "display/intel_gmbus.h"
> @@ -16814,6 +16815,13 @@ static void intel_pps_init(struct drm_i915_private *dev_priv)
> intel_pps_unlock_regs_wa(dev_priv);
> }
>
> +static bool hti_uses_phy(u32 hdport_state, enum phy phy)
> +{
> + return hdport_state & HDPORT_ENABLED &&
> + (hdport_state & HDPORT_PHY_USED_DP(phy) ||
> + hdport_state & HDPORT_PHY_USED_HDMI(phy));
> +}
> +
> static void intel_setup_outputs(struct drm_i915_private *dev_priv)
> {
> struct intel_encoder *encoder;
> @@ -16825,10 +16833,22 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
> return;
>
> if (IS_ROCKETLAKE(dev_priv)) {
> - intel_ddi_init(dev_priv, PORT_A);
> - intel_ddi_init(dev_priv, PORT_B);
> - intel_ddi_init(dev_priv, PORT_D); /* DDI TC1 */
> - intel_ddi_init(dev_priv, PORT_E); /* DDI TC2 */
> + /*
> + * If HTI (aka HDPORT) is enabled at boot, it may have taken
> + * over some of the PHYs and made them unavailable to the
> + * driver. In that case we should skip initializing the
> + * corresponding outputs.
> + */
> + u32 hdport_state = intel_de_read(dev_priv, HDPORT_STATE);
> +
> + if (!hti_uses_phy(hdport_state, PHY_A))
> + intel_ddi_init(dev_priv, PORT_A);
> + if (!hti_uses_phy(hdport_state, PHY_B))
> + intel_ddi_init(dev_priv, PORT_B);
> + if (!hti_uses_phy(hdport_state, PHY_C))
> + intel_ddi_init(dev_priv, PORT_D); /* DDI TC1 */
> + if (!hti_uses_phy(hdport_state, PHY_D))
> + intel_ddi_init(dev_priv, PORT_E); /* DDI TC2 */
> } else if (INTEL_GEN(dev_priv) >= 12) {
> intel_ddi_init(dev_priv, PORT_A);
> intel_ddi_init(dev_priv, PORT_B);
> @@ -18376,6 +18396,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
>
> intel_dpll_readout_hw_state(dev_priv);
>
> + dev_priv->hti_pll_mask = intel_get_hti_plls(dev_priv);
Why not do this in intel_shared_dpll_init()?
> +
> for_each_intel_encoder(dev, encoder) {
> pipe = 0;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index b5f4d4cef682b..6f59f9ec453bf 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -265,6 +265,24 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
> mutex_unlock(&dev_priv->dpll.lock);
> }
>
> +/*
> + * HTI (aka HDPORT) may be using some of the platform's PLL's, making them
> + * unavailable for use.
> + */
> +u32 intel_get_hti_plls(struct drm_i915_private *dev_priv)
No need to export this function, check above.
> +{
> + u32 hdport_state;
> +
> + if (!IS_ROCKETLAKE(dev_priv))
> + return 0;
> +
> + hdport_state = intel_de_read(dev_priv, HDPORT_STATE);
> + if (!(hdport_state & HDPORT_ENABLED))
> + return 0;
> +
> + return REG_FIELD_GET(HDPORT_DPLL_USED_MASK, hdport_state);
> +}
> +
> static struct intel_shared_dpll *
> intel_find_shared_dpll(struct intel_atomic_state *state,
> const struct intel_crtc *crtc,
> @@ -280,6 +298,9 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
>
> drm_WARN_ON(&dev_priv->drm, dpll_mask & ~(BIT(I915_NUM_PLLS) - 1));
>
> + /* Eliminate DPLLs from consideration if reserved by HTI */
> + dpll_mask &= ~dev_priv->hti_pll_mask;
This should be done in icl_get_combo_phy_dpll() for RKL only.
> +
> for_each_set_bit(i, &dpll_mask, I915_NUM_PLLS) {
> pll = &dev_priv->dpll.shared_dplls[i];
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index 49367847bfb55..edcc43f4670ff 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -390,6 +390,7 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state);
> void intel_shared_dpll_init(struct drm_device *dev);
> void intel_dpll_readout_hw_state(struct drm_i915_private *dev_priv);
> void intel_dpll_sanitize_state(struct drm_i915_private *dev_priv);
> +u32 intel_get_hti_plls(struct drm_i915_private *dev_priv);
>
> void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
> const struct intel_dpll_hw_state *hw_state);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 5649f8e502fef..b836032fa0deb 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1037,6 +1037,9 @@ struct drm_i915_private {
>
> struct intel_l3_parity l3_parity;
>
> + /* Mask of PLLs reserved for use by HTI and unavailable to driver. */
> + u32 hti_pll_mask;
> +
> /*
> * edram size in MB.
> * Cannot be determined by PCIID. You must always read a register.
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 34f8698ac3aa6..34b2ec04ccd86 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2908,6 +2908,12 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define MBUS_BBOX_CTL_S1 _MMIO(0x45040)
> #define MBUS_BBOX_CTL_S2 _MMIO(0x45044)
>
> +#define HDPORT_STATE _MMIO(0x45050)
> +#define HDPORT_DPLL_USED_MASK REG_GENMASK(14, 12)
> +#define HDPORT_PHY_USED_DP(phy) REG_BIT(2 * (phy) + 2)
> +#define HDPORT_PHY_USED_HDMI(phy) REG_BIT(2 * (phy) + 1)
> +#define HDPORT_ENABLED REG_BIT(0)
> +
> /* Make render/texture TLB fetches lower priorty than associated data
> * fetches. This is not turned on by default
> */
_______________________________________________
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^ permalink raw reply [flat|nested] 48+ messages in thread
* [Intel-gfx] [PATCH v2 04/32] drm/i915/rkl: Add initial workarounds
2020-06-18 0:42 [Intel-gfx] [PATCH v2 00/32] Introduce DG1 Lucas De Marchi
` (2 preceding siblings ...)
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 03/32] drm/i915/rkl: Handle HTI Lucas De Marchi
@ 2020-06-18 0:42 ` Lucas De Marchi
2020-06-24 0:13 ` Souza, Jose
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 05/32] drm/i915/rkl: Add Wa_14011224835 for PHY B initialization Lucas De Marchi
` (30 subsequent siblings)
34 siblings, 1 reply; 48+ messages in thread
From: Lucas De Marchi @ 2020-06-18 0:42 UTC (permalink / raw)
To: intel-gfx
From: Matt Roper <matthew.d.roper@intel.com>
RKL and TGL share some general gen12 workarounds, but each platform also
has its own platform-specific workarounds.
v2:
- Add Wa_1604555607 for RKL. This makes RKL's ctx WA list identical to
TGL's, so we'll have both functions call the tgl_ function for now;
this workaround isn't listed for DG1 so we don't want to add it to
the general gen12_ function.
Cc: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_sprite.c | 5 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 88 +++++++++++++--------
2 files changed, 59 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 3cd461bf91311..63ac79f88fa21 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -2842,8 +2842,9 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv,
enum plane_id plane_id)
{
- /* Wa_14010477008:tgl[a0..c0] */
- if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0))
+ /* Wa_14010477008:tgl[a0..c0],rkl[all] */
+ if (IS_ROCKETLAKE(dev_priv) ||
+ IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0))
return false;
return plane_id < PLANE_SPRITE4;
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 2da366821ddaf..741710ca2b9a5 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -596,8 +596,8 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU);
}
-static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
- struct i915_wa_list *wal)
+static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine,
+ struct i915_wa_list *wal)
{
/*
* Wa_1409142259:tgl
@@ -607,12 +607,28 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
* Wa_1409207793:tgl
* Wa_1409178076:tgl
* Wa_1408979724:tgl
+ * Wa_14010443199:rkl
+ * Wa_14010698770:rkl
*/
WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
+ /* WaDisableGPGPUMidThreadPreemption:gen12 */
+ WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,
+ GEN9_PREEMPT_GPGPU_LEVEL_MASK,
+ GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL);
+}
+
+static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
+ struct i915_wa_list *wal)
+{
+ gen12_ctx_workarounds_init(engine, wal);
+
/*
- * Wa_1604555607:gen12 and Wa_1608008084:gen12
+ * Wa_1604555607:tgl,rkl
+ *
+ * Note that the implementation of this workaround is further modified
+ * according to the FF_MODE2 guidance given by Wa_1608008084:gen12.
* FF_MODE2 register will return the wrong value when read. The default
* value for this register is zero for all fields and there are no bit
* masks. So instead of doing a RMW we should just write the GS Timer
@@ -623,11 +639,6 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
FF_MODE2_GS_TIMER_MASK | FF_MODE2_TDS_TIMER_MASK,
FF_MODE2_GS_TIMER_224 | FF_MODE2_TDS_TIMER_128,
0);
-
- /* WaDisableGPGPUMidThreadPreemption:tgl */
- WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,
- GEN9_PREEMPT_GPGPU_LEVEL_MASK,
- GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL);
}
static void
@@ -642,8 +653,10 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
wa_init_start(wal, name, engine->name);
- if (IS_GEN(i915, 12))
+ if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915))
tgl_ctx_workarounds_init(engine, wal);
+ else if (IS_GEN(i915, 12))
+ gen12_ctx_workarounds_init(engine, wal);
else if (IS_GEN(i915, 11))
icl_ctx_workarounds_init(engine, wal);
else if (IS_CANNONLAKE(i915))
@@ -1176,9 +1189,16 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
}
static void
-tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
+gen12_gt_workarounds_init(struct drm_i915_private *i915,
+ struct i915_wa_list *wal)
{
wa_init_mcr(i915, wal);
+}
+
+static void
+tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
+{
+ gen12_gt_workarounds_init(i915, wal);
/* Wa_1409420604:tgl */
if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
@@ -1196,8 +1216,10 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
static void
gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
{
- if (IS_GEN(i915, 12))
+ if (IS_TIGERLAKE(i915))
tgl_gt_workarounds_init(i915, wal);
+ else if (IS_GEN(i915, 12))
+ gen12_gt_workarounds_init(i915, wal);
else if (IS_GEN(i915, 11))
icl_gt_workarounds_init(i915, wal);
else if (IS_CANNONLAKE(i915))
@@ -1629,18 +1651,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
GEN9_CTX_PREEMPT_REG,
GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
- /*
- * Wa_1607030317:tgl
- * Wa_1607186500:tgl
- * Wa_1607297627:tgl there is 3 entries for this WA on BSpec, 2
- * of then says it is fixed on B0 the other one says it is
- * permanent
- */
- wa_masked_en(wal,
- GEN6_RC_SLEEP_PSMI_CONTROL,
- GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
- GEN8_RC_SEMA_IDLE_MSG_DISABLE);
-
/*
* Wa_1606679103:tgl
* (see also Wa_1606682166:icl)
@@ -1659,24 +1669,38 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
VSUNIT_CLKGATE_DIS_TGL);
}
- if (IS_TIGERLAKE(i915)) {
- /* Wa_1606931601:tgl */
+ if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
+ /* Wa_1606931601:tgl,rkl */
wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ);
- /* Wa_1409804808:tgl */
+ /* Wa_1409804808:tgl,rkl */
wa_masked_en(wal, GEN7_ROW_CHICKEN2,
GEN12_PUSH_CONST_DEREF_HOLD_DIS);
- /* Wa_1606700617:tgl */
- wa_masked_en(wal,
- GEN9_CS_DEBUG_MODE1,
- FF_DOP_CLOCK_GATE_DISABLE);
-
/*
* Wa_1409085225:tgl
- * Wa_14010229206:tgl
+ * Wa_14010229206:tgl,rkl
*/
wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH);
+
+ /*
+ * Wa_1607030317:tgl
+ * Wa_1607186500:tgl
+ * Wa_1607297627:tgl,rkl there are multiple entries for this
+ * WA in the BSpec; some indicate this is an A0-only WA,
+ * others indicate it applies to all steppings.
+ */
+ wa_masked_en(wal,
+ GEN6_RC_SLEEP_PSMI_CONTROL,
+ GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
+ GEN8_RC_SEMA_IDLE_MSG_DISABLE);
+ }
+
+ if (IS_TIGERLAKE(i915)) {
+ /* Wa_1606700617:tgl */
+ wa_masked_en(wal,
+ GEN9_CS_DEBUG_MODE1,
+ FF_DOP_CLOCK_GATE_DISABLE);
}
if (IS_GEN(i915, 11)) {
--
2.26.2
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^ permalink raw reply related [flat|nested] 48+ messages in thread* Re: [Intel-gfx] [PATCH v2 04/32] drm/i915/rkl: Add initial workarounds
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 04/32] drm/i915/rkl: Add initial workarounds Lucas De Marchi
@ 2020-06-24 0:13 ` Souza, Jose
0 siblings, 0 replies; 48+ messages in thread
From: Souza, Jose @ 2020-06-24 0:13 UTC (permalink / raw)
To: intel-gfx, De Marchi, Lucas
On Wed, 2020-06-17 at 17:42 -0700, Lucas De Marchi wrote:
> From: Matt Roper <matthew.d.roper@intel.com>
>
> RKL and TGL share some general gen12 workarounds, but each platform also
> has its own platform-specific workarounds.
>
> v2:
> - Add Wa_1604555607 for RKL. This makes RKL's ctx WA list identical to
> TGL's, so we'll have both functions call the tgl_ function for now;
> this workaround isn't listed for DG1 so we don't want to add it to
> the general gen12_ function.
>
> Cc: Matt Atwood <matthew.s.atwood@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_sprite.c | 5 +-
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 88 +++++++++++++--------
> 2 files changed, 59 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 3cd461bf91311..63ac79f88fa21 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -2842,8 +2842,9 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
> static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv,
> enum plane_id plane_id)
> {
> - /* Wa_14010477008:tgl[a0..c0] */
> - if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0))
> + /* Wa_14010477008:tgl[a0..c0],rkl[all] */
> + if (IS_ROCKETLAKE(dev_priv) ||
> + IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0))
> return false;
>
> return plane_id < PLANE_SPRITE4;
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 2da366821ddaf..741710ca2b9a5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -596,8 +596,8 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
> wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU);
> }
>
> -static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
> - struct i915_wa_list *wal)
> +static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine,
> + struct i915_wa_list *wal)
> {
> /*
> * Wa_1409142259:tgl
> @@ -607,12 +607,28 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
> * Wa_1409207793:tgl
> * Wa_1409178076:tgl
> * Wa_1408979724:tgl
> + * Wa_14010443199:rkl
> + * Wa_14010698770:rkl
> */
> WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
> GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
>
> + /* WaDisableGPGPUMidThreadPreemption:gen12 */
> + WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,
> + GEN9_PREEMPT_GPGPU_LEVEL_MASK,
> + GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL);
> +}
> +
> +static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
> + struct i915_wa_list *wal)
> +{
> + gen12_ctx_workarounds_init(engine, wal);
> +
> /*
> - * Wa_1604555607:gen12 and Wa_1608008084:gen12
> + * Wa_1604555607:tgl,rkl
> + *
> + * Note that the implementation of this workaround is further modified
> + * according to the FF_MODE2 guidance given by Wa_1608008084:gen12.
> * FF_MODE2 register will return the wrong value when read. The default
> * value for this register is zero for all fields and there are no bit
> * masks. So instead of doing a RMW we should just write the GS Timer
> @@ -623,11 +639,6 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
> FF_MODE2_GS_TIMER_MASK | FF_MODE2_TDS_TIMER_MASK,
> FF_MODE2_GS_TIMER_224 | FF_MODE2_TDS_TIMER_128,
> 0);
> -
> - /* WaDisableGPGPUMidThreadPreemption:tgl */
> - WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,
> - GEN9_PREEMPT_GPGPU_LEVEL_MASK,
> - GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL);
> }
>
> static void
> @@ -642,8 +653,10 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
>
> wa_init_start(wal, name, engine->name);
>
> - if (IS_GEN(i915, 12))
> + if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915))
> tgl_ctx_workarounds_init(engine, wal);
> + else if (IS_GEN(i915, 12))
> + gen12_ctx_workarounds_init(engine, wal);
> else if (IS_GEN(i915, 11))
> icl_ctx_workarounds_init(engine, wal);
> else if (IS_CANNONLAKE(i915))
> @@ -1176,9 +1189,16 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
> }
>
> static void
> -tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
> +gen12_gt_workarounds_init(struct drm_i915_private *i915,
> + struct i915_wa_list *wal)
> {
> wa_init_mcr(i915, wal);
> +}
> +
> +static void
> +tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
> +{
> + gen12_gt_workarounds_init(i915, wal);
>
> /* Wa_1409420604:tgl */
> if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
> @@ -1196,8 +1216,10 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
> static void
> gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
> {
> - if (IS_GEN(i915, 12))
> + if (IS_TIGERLAKE(i915))
> tgl_gt_workarounds_init(i915, wal);
> + else if (IS_GEN(i915, 12))
> + gen12_gt_workarounds_init(i915, wal);
> else if (IS_GEN(i915, 11))
> icl_gt_workarounds_init(i915, wal);
> else if (IS_CANNONLAKE(i915))
> @@ -1629,18 +1651,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> GEN9_CTX_PREEMPT_REG,
> GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
>
> - /*
> - * Wa_1607030317:tgl
> - * Wa_1607186500:tgl
> - * Wa_1607297627:tgl there is 3 entries for this WA on BSpec, 2
> - * of then says it is fixed on B0 the other one says it is
> - * permanent
> - */
> - wa_masked_en(wal,
> - GEN6_RC_SLEEP_PSMI_CONTROL,
> - GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
> - GEN8_RC_SEMA_IDLE_MSG_DISABLE);
> -
> /*
> * Wa_1606679103:tgl
> * (see also Wa_1606682166:icl)
> @@ -1659,24 +1669,38 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> VSUNIT_CLKGATE_DIS_TGL);
> }
>
> - if (IS_TIGERLAKE(i915)) {
> - /* Wa_1606931601:tgl */
> + if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
> + /* Wa_1606931601:tgl,rkl */
> wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ);
>
> - /* Wa_1409804808:tgl */
> + /* Wa_1409804808:tgl,rkl */
> wa_masked_en(wal, GEN7_ROW_CHICKEN2,
> GEN12_PUSH_CONST_DEREF_HOLD_DIS);
>
> - /* Wa_1606700617:tgl */
> - wa_masked_en(wal,
> - GEN9_CS_DEBUG_MODE1,
> - FF_DOP_CLOCK_GATE_DISABLE);
> -
> /*
> * Wa_1409085225:tgl
> - * Wa_14010229206:tgl
> + * Wa_14010229206:tgl,rkl
> */
> wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH);
> +
> + /*
> + * Wa_1607030317:tgl
> + * Wa_1607186500:tgl
> + * Wa_1607297627:tgl,rkl there are multiple entries for this
> + * WA in the BSpec; some indicate this is an A0-only WA,
> + * others indicate it applies to all steppings.
> + */
> + wa_masked_en(wal,
> + GEN6_RC_SLEEP_PSMI_CONTROL,
> + GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
> + GEN8_RC_SEMA_IDLE_MSG_DISABLE);
> + }
> +
> + if (IS_TIGERLAKE(i915)) {
> + /* Wa_1606700617:tgl */
> + wa_masked_en(wal,
> + GEN9_CS_DEBUG_MODE1,
> + FF_DOP_CLOCK_GATE_DISABLE);
RKL might need this one too under the number 14010230801 but is still pending.
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> }
>
> if (IS_GEN(i915, 11)) {
_______________________________________________
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^ permalink raw reply [flat|nested] 48+ messages in thread
* [Intel-gfx] [PATCH v2 05/32] drm/i915/rkl: Add Wa_14011224835 for PHY B initialization
2020-06-18 0:42 [Intel-gfx] [PATCH v2 00/32] Introduce DG1 Lucas De Marchi
` (3 preceding siblings ...)
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 04/32] drm/i915/rkl: Add initial workarounds Lucas De Marchi
@ 2020-06-18 0:42 ` Lucas De Marchi
2020-06-24 0:07 ` Souza, Jose
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 06/32] drm/i915: Add has_master_unit_irq flag Lucas De Marchi
` (29 subsequent siblings)
34 siblings, 1 reply; 48+ messages in thread
From: Lucas De Marchi @ 2020-06-18 0:42 UTC (permalink / raw)
To: intel-gfx
From: Matt Roper <matthew.d.roper@intel.com>
After doing normal PHY-B initialization on Rocket Lake, we need to
manually copy some additional PHY-A register values into PHY-B
registers.
Note that the bspec's combo phy page doesn't specify that this
workaround is restricted to specific platform steppings (and doesn't
even do a very good job of specifying that RKL is the only platform this
is needed on), but the RKL workaround page lists this as relevant only
for A and B steppings, so I'm trusting that information for now.
v2: Make rkl_combo_phy_b_init_wa() static
Bspec: 49291
Bspec: 53273
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
.../gpu/drm/i915/display/intel_combo_phy.c | 26 +++++++++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 13 +++++++++-
2 files changed, 38 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index 77b04bb3ec624..d5d95e2746c2c 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -338,6 +338,27 @@ void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv,
intel_de_write(dev_priv, ICL_PORT_CL_DW10(phy), val);
}
+static void rkl_combo_phy_b_init_wa(struct drm_i915_private *i915)
+{
+ u32 grccode, grccode_ldo;
+ u32 iref_rcal_ord, rcompcode_ld_cap_ov;
+
+ intel_de_wait_for_register(i915, ICL_PORT_COMP_DW3(PHY_A),
+ FIRST_COMP_DONE, FIRST_COMP_DONE, 100);
+
+ grccode = REG_FIELD_GET(GRCCODE,
+ intel_de_read(i915, ICL_PORT_COMP_DW6(PHY_A)));
+ iref_rcal_ord = REG_FIELD_PREP(IREF_RCAL_ORD, grccode);
+ intel_de_rmw(i915, ICL_PORT_COMP_DW2(PHY_B), IREF_RCAL_ORD,
+ iref_rcal_ord | IREF_RCAL_ORD_EN);
+
+ grccode_ldo = REG_FIELD_GET(GRCCODE_LDO,
+ intel_de_read(i915, ICL_PORT_COMP_DW0(PHY_A)));
+ rcompcode_ld_cap_ov = REG_FIELD_PREP(RCOMPCODE_LD_CAP_OV, grccode_ldo);
+ intel_de_rmw(i915, ICL_PORT_COMP_DW6(PHY_B), RCOMPCODE_LD_CAP_OV,
+ rcompcode_ld_cap_ov | RCOMPCODEOVEN_LDO_SYNC);
+}
+
static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
{
enum phy phy;
@@ -390,6 +411,11 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
val = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy));
val |= CL_POWER_DOWN_ENABLE;
intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val);
+
+ if (IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_B0) &&
+ phy == PHY_B)
+ /* Wa_14011224835:rkl[a0..c0] */
+ rkl_combo_phy_b_init_wa(dev_priv);
}
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 34b2ec04ccd86..10f6e46523b6e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1908,11 +1908,16 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define CNL_PORT_COMP_DW0 _MMIO(0x162100)
#define ICL_PORT_COMP_DW0(phy) _MMIO(_ICL_PORT_COMP_DW(0, phy))
-#define COMP_INIT (1 << 31)
+#define COMP_INIT REG_BIT(31)
+#define GRCCODE_LDO REG_GENMASK(7, 0)
#define CNL_PORT_COMP_DW1 _MMIO(0x162104)
#define ICL_PORT_COMP_DW1(phy) _MMIO(_ICL_PORT_COMP_DW(1, phy))
+#define ICL_PORT_COMP_DW2(phy) _MMIO(_ICL_PORT_COMP_DW(2, phy))
+#define IREF_RCAL_ORD_EN REG_BIT(7)
+#define IREF_RCAL_ORD REG_GENMASK(6, 0)
+
#define CNL_PORT_COMP_DW3 _MMIO(0x16210c)
#define ICL_PORT_COMP_DW3(phy) _MMIO(_ICL_PORT_COMP_DW(3, phy))
#define PROCESS_INFO_DOT_0 (0 << 26)
@@ -1925,6 +1930,12 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define VOLTAGE_INFO_1_05V (2 << 24)
#define VOLTAGE_INFO_MASK (3 << 24)
#define VOLTAGE_INFO_SHIFT 24
+#define FIRST_COMP_DONE REG_BIT(22)
+
+#define ICL_PORT_COMP_DW6(phy) _MMIO(_ICL_PORT_COMP_DW(6, phy))
+#define GRCCODE REG_GENMASK(30, 24)
+#define RCOMPCODEOVEN_LDO_SYNC REG_BIT(23)
+#define RCOMPCODE_LD_CAP_OV REG_GENMASK(22, 16)
#define ICL_PORT_COMP_DW8(phy) _MMIO(_ICL_PORT_COMP_DW(8, phy))
#define IREFGEN (1 << 24)
--
2.26.2
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^ permalink raw reply related [flat|nested] 48+ messages in thread* Re: [Intel-gfx] [PATCH v2 05/32] drm/i915/rkl: Add Wa_14011224835 for PHY B initialization
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 05/32] drm/i915/rkl: Add Wa_14011224835 for PHY B initialization Lucas De Marchi
@ 2020-06-24 0:07 ` Souza, Jose
0 siblings, 0 replies; 48+ messages in thread
From: Souza, Jose @ 2020-06-24 0:07 UTC (permalink / raw)
To: intel-gfx, De Marchi, Lucas
On Wed, 2020-06-17 at 17:42 -0700, Lucas De Marchi wrote:
> From: Matt Roper <matthew.d.roper@intel.com>
>
> After doing normal PHY-B initialization on Rocket Lake, we need to
> manually copy some additional PHY-A register values into PHY-B
> registers.
Damn, just sent this, did a search using 14011471926 and did not found it anywhere, anyways lets go with this one, please also refers to 14011471926.
https://patchwork.freedesktop.org/patch/372713/?series=78761&rev=1
>
> Note that the bspec's combo phy page doesn't specify that this
> workaround is restricted to specific platform steppings (and doesn't
> even do a very good job of specifying that RKL is the only platform this
> is needed on), but the RKL workaround page lists this as relevant only
> for A and B steppings, so I'm trusting that information for now.
>
> v2: Make rkl_combo_phy_b_init_wa() static
>
> Bspec: 49291
> Bspec: 53273
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> .../gpu/drm/i915/display/intel_combo_phy.c | 26 +++++++++++++++++++
> drivers/gpu/drm/i915/i915_reg.h | 13 +++++++++-
> 2 files changed, 38 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> index 77b04bb3ec624..d5d95e2746c2c 100644
> --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> @@ -338,6 +338,27 @@ void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv,
> intel_de_write(dev_priv, ICL_PORT_CL_DW10(phy), val);
> }
>
> +static void rkl_combo_phy_b_init_wa(struct drm_i915_private *i915)
> +{
> + u32 grccode, grccode_ldo;
> + u32 iref_rcal_ord, rcompcode_ld_cap_ov;
Nitpick: you could do all the bellow with just 2 u32(val and grccode).
> +
> + intel_de_wait_for_register(i915, ICL_PORT_COMP_DW3(PHY_A),
> + FIRST_COMP_DONE, FIRST_COMP_DONE, 100);
The timeout parameter here is in ms not usec.
> +
> + grccode = REG_FIELD_GET(GRCCODE,
> + intel_de_read(i915, ICL_PORT_COMP_DW6(PHY_A)));
> + iref_rcal_ord = REG_FIELD_PREP(IREF_RCAL_ORD, grccode);
> + intel_de_rmw(i915, ICL_PORT_COMP_DW2(PHY_B), IREF_RCAL_ORD,
> + iref_rcal_ord | IREF_RCAL_ORD_EN);
> +
> + grccode_ldo = REG_FIELD_GET(GRCCODE_LDO,
> + intel_de_read(i915, ICL_PORT_COMP_DW0(PHY_A)));
> + rcompcode_ld_cap_ov = REG_FIELD_PREP(RCOMPCODE_LD_CAP_OV, grccode_ldo);
> + intel_de_rmw(i915, ICL_PORT_COMP_DW6(PHY_B), RCOMPCODE_LD_CAP_OV,
> + rcompcode_ld_cap_ov | RCOMPCODEOVEN_LDO_SYNC);
> +}
> +
> static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
> {
> enum phy phy;
> @@ -390,6 +411,11 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
> val = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy));
> val |= CL_POWER_DOWN_ENABLE;
> intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val);
> +
> + if (IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_B0) &&
> + phy == PHY_B)
> + /* Wa_14011224835:rkl[a0..c0] */
> + rkl_combo_phy_b_init_wa(dev_priv);
Missing the icl_combo_phy_verify_state() counter part.
> }
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 34b2ec04ccd86..10f6e46523b6e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1908,11 +1908,16 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>
> #define CNL_PORT_COMP_DW0 _MMIO(0x162100)
> #define ICL_PORT_COMP_DW0(phy) _MMIO(_ICL_PORT_COMP_DW(0, phy))
> -#define COMP_INIT (1 << 31)
> +#define COMP_INIT REG_BIT(31)
> +#define GRCCODE_LDO REG_GENMASK(7, 0)
>
> #define CNL_PORT_COMP_DW1 _MMIO(0x162104)
> #define ICL_PORT_COMP_DW1(phy) _MMIO(_ICL_PORT_COMP_DW(1, phy))
>
> +#define ICL_PORT_COMP_DW2(phy) _MMIO(_ICL_PORT_COMP_DW(2, phy))
> +#define IREF_RCAL_ORD_EN REG_BIT(7)
> +#define IREF_RCAL_ORD REG_GENMASK(6, 0)
> +
> #define CNL_PORT_COMP_DW3 _MMIO(0x16210c)
> #define ICL_PORT_COMP_DW3(phy) _MMIO(_ICL_PORT_COMP_DW(3, phy))
> #define PROCESS_INFO_DOT_0 (0 << 26)
> @@ -1925,6 +1930,12 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define VOLTAGE_INFO_1_05V (2 << 24)
> #define VOLTAGE_INFO_MASK (3 << 24)
> #define VOLTAGE_INFO_SHIFT 24
> +#define FIRST_COMP_DONE REG_BIT(22)
> +
> +#define ICL_PORT_COMP_DW6(phy) _MMIO(_ICL_PORT_COMP_DW(6, phy))
> +#define GRCCODE REG_GENMASK(30, 24)
> +#define RCOMPCODEOVEN_LDO_SYNC REG_BIT(23)
> +#define RCOMPCODE_LD_CAP_OV REG_GENMASK(22, 16)
>
> #define ICL_PORT_COMP_DW8(phy) _MMIO(_ICL_PORT_COMP_DW(8, phy))
> #define IREFGEN (1 << 24)
Register definition matches.
_______________________________________________
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^ permalink raw reply [flat|nested] 48+ messages in thread
* [Intel-gfx] [PATCH v2 06/32] drm/i915: Add has_master_unit_irq flag
2020-06-18 0:42 [Intel-gfx] [PATCH v2 00/32] Introduce DG1 Lucas De Marchi
` (4 preceding siblings ...)
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 05/32] drm/i915/rkl: Add Wa_14011224835 for PHY B initialization Lucas De Marchi
@ 2020-06-18 0:42 ` Lucas De Marchi
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 07/32] drm/i915/dg1: add initial DG-1 definitions Lucas De Marchi
` (28 subsequent siblings)
34 siblings, 0 replies; 48+ messages in thread
From: Lucas De Marchi @ 2020-06-18 0:42 UTC (permalink / raw)
To: intel-gfx
From: Stuart Summers <stuart.summers@intel.com>
Add flag to differentiate platforms with and without the master
IRQ control bit.
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_device_info.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b836032fa0deb..2f8057a0b2280 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1595,6 +1595,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
(INTEL_INFO(dev_priv)->has_logical_ring_preemption)
+#define HAS_MASTER_UNIT_IRQ(dev_priv) (INTEL_INFO(dev_priv)->has_master_unit_irq)
+
#define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
#define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type)
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 8d62b8538585d..770d07003ce60 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -122,6 +122,7 @@ enum intel_ppgtt_type {
func(has_logical_ring_contexts); \
func(has_logical_ring_elsq); \
func(has_logical_ring_preemption); \
+ func(has_master_unit_irq); \
func(has_pooled_eu); \
func(has_rc6); \
func(has_rc6p); \
--
2.26.2
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 48+ messages in thread* [Intel-gfx] [PATCH v2 07/32] drm/i915/dg1: add initial DG-1 definitions
2020-06-18 0:42 [Intel-gfx] [PATCH v2 00/32] Introduce DG1 Lucas De Marchi
` (5 preceding siblings ...)
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 06/32] drm/i915: Add has_master_unit_irq flag Lucas De Marchi
@ 2020-06-18 0:42 ` Lucas De Marchi
2020-06-22 7:51 ` Daniel Vetter
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 08/32] drm/i915/dg1: Add DG1 PCI IDs Lucas De Marchi
` (27 subsequent siblings)
34 siblings, 1 reply; 48+ messages in thread
From: Lucas De Marchi @ 2020-06-18 0:42 UTC (permalink / raw)
To: intel-gfx
From: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Bspec: 33617, 33617
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Stuart Summers <stuart.summers@intel.com>
Cc: Vanshidhar Konda <vanshidhar.r.konda@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 7 +++++++
drivers/gpu/drm/i915/i915_pci.c | 12 ++++++++++++
drivers/gpu/drm/i915/intel_device_info.c | 1 +
drivers/gpu/drm/i915/intel_device_info.h | 1 +
4 files changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2f8057a0b2280..f79c09257eb6b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1428,6 +1428,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_ELKHARTLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
#define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
#define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
+#define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG1)
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
(INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
#define IS_BDW_ULT(dev_priv) \
@@ -1556,6 +1557,12 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_RKL_REVID(p, since, until) \
(IS_ROCKETLAKE(p) && IS_REVID(p, since, until))
+#define DG1_REVID_A0 0x0
+#define DG1_REVID_B0 0x1
+
+#define IS_DG1_REVID(p, since, until) \
+ (IS_DG1(p) && IS_REVID(p, since, until))
+
#define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
#define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
#define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index e5fdf17cd9cdd..58cceeaa0ffa5 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -896,8 +896,20 @@ static const struct intel_device_info rkl_info = {
#define GEN12_DGFX_FEATURES \
GEN12_FEATURES, \
+ .memory_regions = REGION_SMEM | REGION_LMEM, \
+ .has_master_unit_irq = 1, \
.is_dgfx = 1
+static const struct intel_device_info intel_dg1_info = {
+ GEN12_DGFX_FEATURES,
+ PLATFORM(INTEL_DG1),
+ .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
+ .require_force_probe = 1,
+ .engine_mask =
+ BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
+ BIT(VCS0) | BIT(VCS2),
+};
+
#undef GEN
#undef PLATFORM
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 544ac61fbc363..2e40a6649d142 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -63,6 +63,7 @@ static const char * const platform_names[] = {
PLATFORM_NAME(ELKHARTLAKE),
PLATFORM_NAME(TIGERLAKE),
PLATFORM_NAME(ROCKETLAKE),
+ PLATFORM_NAME(DG1),
};
#undef PLATFORM_NAME
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 770d07003ce60..bdd21cde917cc 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -82,6 +82,7 @@ enum intel_platform {
/* gen12 */
INTEL_TIGERLAKE,
INTEL_ROCKETLAKE,
+ INTEL_DG1,
INTEL_MAX_PLATFORMS
};
--
2.26.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 48+ messages in thread* Re: [Intel-gfx] [PATCH v2 07/32] drm/i915/dg1: add initial DG-1 definitions
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 07/32] drm/i915/dg1: add initial DG-1 definitions Lucas De Marchi
@ 2020-06-22 7:51 ` Daniel Vetter
2020-06-22 9:55 ` Jani Nikula
0 siblings, 1 reply; 48+ messages in thread
From: Daniel Vetter @ 2020-06-22 7:51 UTC (permalink / raw)
To: Lucas De Marchi, Dave Airlie, Rodrigo Vivi, Nikula, Jani,
Joonas Lahtinen
Cc: intel-gfx
On Wed, Jun 17, 2020 at 05:42:15PM -0700, Lucas De Marchi wrote:
> From: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
>
> Bspec: 33617, 33617
>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Stuart Summers <stuart.summers@intel.com>
> Cc: Vanshidhar Konda <vanshidhar.r.konda@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 7 +++++++
> drivers/gpu/drm/i915/i915_pci.c | 12 ++++++++++++
> drivers/gpu/drm/i915/intel_device_info.c | 1 +
> drivers/gpu/drm/i915/intel_device_info.h | 1 +
> 4 files changed, 21 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 2f8057a0b2280..f79c09257eb6b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1428,6 +1428,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define IS_ELKHARTLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
> #define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
> #define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
> +#define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG1)
> #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
> (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
> #define IS_BDW_ULT(dev_priv) \
> @@ -1556,6 +1557,12 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define IS_RKL_REVID(p, since, until) \
> (IS_ROCKETLAKE(p) && IS_REVID(p, since, until))
>
> +#define DG1_REVID_A0 0x0
> +#define DG1_REVID_B0 0x1
> +
> +#define IS_DG1_REVID(p, since, until) \
> + (IS_DG1(p) && IS_REVID(p, since, until))
> +
> #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
> #define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
> #define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index e5fdf17cd9cdd..58cceeaa0ffa5 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -896,8 +896,20 @@ static const struct intel_device_info rkl_info = {
>
> #define GEN12_DGFX_FEATURES \
> GEN12_FEATURES, \
> + .memory_regions = REGION_SMEM | REGION_LMEM, \
This has lmem, and we need a new uapi for that. Last year we discussed a
plan to have that behind a very scary compile-time only option, to make
absolutely sure no one will start relying on this broken state before we
aligned everything. And we know the current status is wrong since this
patch series doesn't include any of the lmem specific uapi that's being
worked on.
But now almost a year passed, so that original plan needs to be
renegotiated. Personally I'm not sure the scary compile option makes
sense any longer, we're way later, users will soon have real hw, and once
they have that they will find ways to enable it and we're potentially
screwed. Discussed this also with Joonas last week or so in private, and
he shares similar concerns.
So I think best option here (since keeping patches out of tree is rarely
best option) would be to merge just the display enabling for DG1, but also
making sure that we have all the rendering support completely disabled.
This would mean:
- wedge gpu on startup, just to make sure
- drm_driver->num_ioctls = 0 (plus ioctls = NULL)
- no setting DRIVER_RENDER and DRIVER_SYNCOBJ, we'd be a pure
display-only driver
Adding Dave and drm-intel maintainers to quickly hash this out. Thoughts?
-Daniel
> + .has_master_unit_irq = 1, \
> .is_dgfx = 1
>
> +static const struct intel_device_info intel_dg1_info = {
> + GEN12_DGFX_FEATURES,
> + PLATFORM(INTEL_DG1),
> + .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
> + .require_force_probe = 1,
> + .engine_mask =
> + BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
> + BIT(VCS0) | BIT(VCS2),
> +};
> +
> #undef GEN
> #undef PLATFORM
>
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 544ac61fbc363..2e40a6649d142 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -63,6 +63,7 @@ static const char * const platform_names[] = {
> PLATFORM_NAME(ELKHARTLAKE),
> PLATFORM_NAME(TIGERLAKE),
> PLATFORM_NAME(ROCKETLAKE),
> + PLATFORM_NAME(DG1),
> };
> #undef PLATFORM_NAME
>
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 770d07003ce60..bdd21cde917cc 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -82,6 +82,7 @@ enum intel_platform {
> /* gen12 */
> INTEL_TIGERLAKE,
> INTEL_ROCKETLAKE,
> + INTEL_DG1,
> INTEL_MAX_PLATFORMS
> };
>
> --
> 2.26.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 48+ messages in thread* Re: [Intel-gfx] [PATCH v2 07/32] drm/i915/dg1: add initial DG-1 definitions
2020-06-22 7:51 ` Daniel Vetter
@ 2020-06-22 9:55 ` Jani Nikula
2020-06-23 4:54 ` Dave Airlie
0 siblings, 1 reply; 48+ messages in thread
From: Jani Nikula @ 2020-06-22 9:55 UTC (permalink / raw)
To: Daniel Vetter, Lucas De Marchi, Dave Airlie, Rodrigo Vivi,
Joonas Lahtinen
Cc: intel-gfx
On Mon, 22 Jun 2020, Daniel Vetter <daniel@ffwll.ch> wrote:
> On Wed, Jun 17, 2020 at 05:42:15PM -0700, Lucas De Marchi wrote:
>> From: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
>>
>> Bspec: 33617, 33617
>>
>> Cc: José Roberto de Souza <jose.souza@intel.com>
>> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>> Cc: Stuart Summers <stuart.summers@intel.com>
>> Cc: Vanshidhar Konda <vanshidhar.r.konda@intel.com>
>> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>> Cc: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
>> Cc: Matt Roper <matthew.d.roper@intel.com>
>> Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_drv.h | 7 +++++++
>> drivers/gpu/drm/i915/i915_pci.c | 12 ++++++++++++
>> drivers/gpu/drm/i915/intel_device_info.c | 1 +
>> drivers/gpu/drm/i915/intel_device_info.h | 1 +
>> 4 files changed, 21 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 2f8057a0b2280..f79c09257eb6b 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -1428,6 +1428,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>> #define IS_ELKHARTLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
>> #define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
>> #define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
>> +#define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG1)
>> #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
>> (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
>> #define IS_BDW_ULT(dev_priv) \
>> @@ -1556,6 +1557,12 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>> #define IS_RKL_REVID(p, since, until) \
>> (IS_ROCKETLAKE(p) && IS_REVID(p, since, until))
>>
>> +#define DG1_REVID_A0 0x0
>> +#define DG1_REVID_B0 0x1
>> +
>> +#define IS_DG1_REVID(p, since, until) \
>> + (IS_DG1(p) && IS_REVID(p, since, until))
>> +
>> #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
>> #define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
>> #define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
>> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
>> index e5fdf17cd9cdd..58cceeaa0ffa5 100644
>> --- a/drivers/gpu/drm/i915/i915_pci.c
>> +++ b/drivers/gpu/drm/i915/i915_pci.c
>> @@ -896,8 +896,20 @@ static const struct intel_device_info rkl_info = {
>>
>> #define GEN12_DGFX_FEATURES \
>> GEN12_FEATURES, \
>> + .memory_regions = REGION_SMEM | REGION_LMEM, \
>
> This has lmem, and we need a new uapi for that. Last year we discussed a
> plan to have that behind a very scary compile-time only option, to make
> absolutely sure no one will start relying on this broken state before we
> aligned everything. And we know the current status is wrong since this
> patch series doesn't include any of the lmem specific uapi that's being
> worked on.
>
> But now almost a year passed, so that original plan needs to be
> renegotiated. Personally I'm not sure the scary compile option makes
> sense any longer, we're way later, users will soon have real hw, and once
> they have that they will find ways to enable it and we're potentially
> screwed. Discussed this also with Joonas last week or so in private, and
> he shares similar concerns.
>
> So I think best option here (since keeping patches out of tree is rarely
> best option) would be to merge just the display enabling for DG1, but also
> making sure that we have all the rendering support completely disabled.
> This would mean:
> - wedge gpu on startup, just to make sure
> - drm_driver->num_ioctls = 0 (plus ioctls = NULL)
> - no setting DRIVER_RENDER and DRIVER_SYNCOBJ, we'd be a pure
> display-only driver
>
> Adding Dave and drm-intel maintainers to quickly hash this out. Thoughts?
I'll defer the decision on lmem to folks who actually know this stuff,
and focus on display. And from that perspective, I'd like to unblock
merging the display patches.
BR,
Jani.
> -Daniel
>
>
>> + .has_master_unit_irq = 1, \
>> .is_dgfx = 1
>>
>> +static const struct intel_device_info intel_dg1_info = {
>> + GEN12_DGFX_FEATURES,
>> + PLATFORM(INTEL_DG1),
>> + .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
>> + .require_force_probe = 1,
>> + .engine_mask =
>> + BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
>> + BIT(VCS0) | BIT(VCS2),
>> +};
>> +
>> #undef GEN
>> #undef PLATFORM
>>
>> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
>> index 544ac61fbc363..2e40a6649d142 100644
>> --- a/drivers/gpu/drm/i915/intel_device_info.c
>> +++ b/drivers/gpu/drm/i915/intel_device_info.c
>> @@ -63,6 +63,7 @@ static const char * const platform_names[] = {
>> PLATFORM_NAME(ELKHARTLAKE),
>> PLATFORM_NAME(TIGERLAKE),
>> PLATFORM_NAME(ROCKETLAKE),
>> + PLATFORM_NAME(DG1),
>> };
>> #undef PLATFORM_NAME
>>
>> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
>> index 770d07003ce60..bdd21cde917cc 100644
>> --- a/drivers/gpu/drm/i915/intel_device_info.h
>> +++ b/drivers/gpu/drm/i915/intel_device_info.h
>> @@ -82,6 +82,7 @@ enum intel_platform {
>> /* gen12 */
>> INTEL_TIGERLAKE,
>> INTEL_ROCKETLAKE,
>> + INTEL_DG1,
>> INTEL_MAX_PLATFORMS
>> };
>>
>> --
>> 2.26.2
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 48+ messages in thread* Re: [Intel-gfx] [PATCH v2 07/32] drm/i915/dg1: add initial DG-1 definitions
2020-06-22 9:55 ` Jani Nikula
@ 2020-06-23 4:54 ` Dave Airlie
2020-06-23 6:17 ` Daniel Vetter
0 siblings, 1 reply; 48+ messages in thread
From: Dave Airlie @ 2020-06-23 4:54 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, Lucas De Marchi, Dave Airlie
On Mon, 22 Jun 2020 at 19:55, Jani Nikula <jani.nikula@linux.intel.com> wrote:
>
> On Mon, 22 Jun 2020, Daniel Vetter <daniel@ffwll.ch> wrote:
> > On Wed, Jun 17, 2020 at 05:42:15PM -0700, Lucas De Marchi wrote:
> >> From: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
> >>
> >> Bspec: 33617, 33617
> >>
> >> Cc: José Roberto de Souza <jose.souza@intel.com>
> >> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> >> Cc: Stuart Summers <stuart.summers@intel.com>
> >> Cc: Vanshidhar Konda <vanshidhar.r.konda@intel.com>
> >> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> >> Cc: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
> >> Cc: Matt Roper <matthew.d.roper@intel.com>
> >> Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
> >> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> >> Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> >> ---
> >> drivers/gpu/drm/i915/i915_drv.h | 7 +++++++
> >> drivers/gpu/drm/i915/i915_pci.c | 12 ++++++++++++
> >> drivers/gpu/drm/i915/intel_device_info.c | 1 +
> >> drivers/gpu/drm/i915/intel_device_info.h | 1 +
> >> 4 files changed, 21 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> >> index 2f8057a0b2280..f79c09257eb6b 100644
> >> --- a/drivers/gpu/drm/i915/i915_drv.h
> >> +++ b/drivers/gpu/drm/i915/i915_drv.h
> >> @@ -1428,6 +1428,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> >> #define IS_ELKHARTLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
> >> #define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
> >> #define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
> >> +#define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG1)
> >> #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
> >> (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
> >> #define IS_BDW_ULT(dev_priv) \
> >> @@ -1556,6 +1557,12 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> >> #define IS_RKL_REVID(p, since, until) \
> >> (IS_ROCKETLAKE(p) && IS_REVID(p, since, until))
> >>
> >> +#define DG1_REVID_A0 0x0
> >> +#define DG1_REVID_B0 0x1
> >> +
> >> +#define IS_DG1_REVID(p, since, until) \
> >> + (IS_DG1(p) && IS_REVID(p, since, until))
> >> +
> >> #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
> >> #define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
> >> #define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
> >> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> >> index e5fdf17cd9cdd..58cceeaa0ffa5 100644
> >> --- a/drivers/gpu/drm/i915/i915_pci.c
> >> +++ b/drivers/gpu/drm/i915/i915_pci.c
> >> @@ -896,8 +896,20 @@ static const struct intel_device_info rkl_info = {
> >>
> >> #define GEN12_DGFX_FEATURES \
> >> GEN12_FEATURES, \
> >> + .memory_regions = REGION_SMEM | REGION_LMEM, \
> >
> > This has lmem, and we need a new uapi for that. Last year we discussed a
> > plan to have that behind a very scary compile-time only option, to make
> > absolutely sure no one will start relying on this broken state before we
> > aligned everything. And we know the current status is wrong since this
> > patch series doesn't include any of the lmem specific uapi that's being
> > worked on.
> >
> > But now almost a year passed, so that original plan needs to be
> > renegotiated. Personally I'm not sure the scary compile option makes
> > sense any longer, we're way later, users will soon have real hw, and once
> > they have that they will find ways to enable it and we're potentially
> > screwed. Discussed this also with Joonas last week or so in private, and
> > he shares similar concerns.
> >
> > So I think best option here (since keeping patches out of tree is rarely
> > best option) would be to merge just the display enabling for DG1, but also
> > making sure that we have all the rendering support completely disabled.
> > This would mean:
> > - wedge gpu on startup, just to make sure
> > - drm_driver->num_ioctls = 0 (plus ioctls = NULL)
> > - no setting DRIVER_RENDER and DRIVER_SYNCOBJ, we'd be a pure
> > display-only driver
> >
> > Adding Dave and drm-intel maintainers to quickly hash this out. Thoughts?
>
> I'll defer the decision on lmem to folks who actually know this stuff,
> and focus on display. And from that perspective, I'd like to unblock
> merging the display patches.
>
How does display work without LMEM, I'm assuming you have to scan out
from VRAM on DG1, even if we only have internal non-uapi is this
enough to bring up fbcon?
Dave.
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 48+ messages in thread* Re: [Intel-gfx] [PATCH v2 07/32] drm/i915/dg1: add initial DG-1 definitions
2020-06-23 4:54 ` Dave Airlie
@ 2020-06-23 6:17 ` Daniel Vetter
0 siblings, 0 replies; 48+ messages in thread
From: Daniel Vetter @ 2020-06-23 6:17 UTC (permalink / raw)
To: Dave Airlie; +Cc: intel-gfx, Lucas De Marchi, Dave Airlie
On Tue, Jun 23, 2020 at 6:54 AM Dave Airlie <airlied@gmail.com> wrote:
>
> On Mon, 22 Jun 2020 at 19:55, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> >
> > On Mon, 22 Jun 2020, Daniel Vetter <daniel@ffwll.ch> wrote:
> > > On Wed, Jun 17, 2020 at 05:42:15PM -0700, Lucas De Marchi wrote:
> > >> From: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
> > >>
> > >> Bspec: 33617, 33617
> > >>
> > >> Cc: José Roberto de Souza <jose.souza@intel.com>
> > >> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> > >> Cc: Stuart Summers <stuart.summers@intel.com>
> > >> Cc: Vanshidhar Konda <vanshidhar.r.konda@intel.com>
> > >> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > >> Cc: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
> > >> Cc: Matt Roper <matthew.d.roper@intel.com>
> > >> Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
> > >> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > >> Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> > >> ---
> > >> drivers/gpu/drm/i915/i915_drv.h | 7 +++++++
> > >> drivers/gpu/drm/i915/i915_pci.c | 12 ++++++++++++
> > >> drivers/gpu/drm/i915/intel_device_info.c | 1 +
> > >> drivers/gpu/drm/i915/intel_device_info.h | 1 +
> > >> 4 files changed, 21 insertions(+)
> > >>
> > >> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > >> index 2f8057a0b2280..f79c09257eb6b 100644
> > >> --- a/drivers/gpu/drm/i915/i915_drv.h
> > >> +++ b/drivers/gpu/drm/i915/i915_drv.h
> > >> @@ -1428,6 +1428,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> > >> #define IS_ELKHARTLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
> > >> #define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
> > >> #define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
> > >> +#define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG1)
> > >> #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
> > >> (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
> > >> #define IS_BDW_ULT(dev_priv) \
> > >> @@ -1556,6 +1557,12 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> > >> #define IS_RKL_REVID(p, since, until) \
> > >> (IS_ROCKETLAKE(p) && IS_REVID(p, since, until))
> > >>
> > >> +#define DG1_REVID_A0 0x0
> > >> +#define DG1_REVID_B0 0x1
> > >> +
> > >> +#define IS_DG1_REVID(p, since, until) \
> > >> + (IS_DG1(p) && IS_REVID(p, since, until))
> > >> +
> > >> #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
> > >> #define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
> > >> #define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
> > >> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> > >> index e5fdf17cd9cdd..58cceeaa0ffa5 100644
> > >> --- a/drivers/gpu/drm/i915/i915_pci.c
> > >> +++ b/drivers/gpu/drm/i915/i915_pci.c
> > >> @@ -896,8 +896,20 @@ static const struct intel_device_info rkl_info = {
> > >>
> > >> #define GEN12_DGFX_FEATURES \
> > >> GEN12_FEATURES, \
> > >> + .memory_regions = REGION_SMEM | REGION_LMEM, \
> > >
> > > This has lmem, and we need a new uapi for that. Last year we discussed a
> > > plan to have that behind a very scary compile-time only option, to make
> > > absolutely sure no one will start relying on this broken state before we
> > > aligned everything. And we know the current status is wrong since this
> > > patch series doesn't include any of the lmem specific uapi that's being
> > > worked on.
> > >
> > > But now almost a year passed, so that original plan needs to be
> > > renegotiated. Personally I'm not sure the scary compile option makes
> > > sense any longer, we're way later, users will soon have real hw, and once
> > > they have that they will find ways to enable it and we're potentially
> > > screwed. Discussed this also with Joonas last week or so in private, and
> > > he shares similar concerns.
> > >
> > > So I think best option here (since keeping patches out of tree is rarely
> > > best option) would be to merge just the display enabling for DG1, but also
> > > making sure that we have all the rendering support completely disabled.
> > > This would mean:
> > > - wedge gpu on startup, just to make sure
> > > - drm_driver->num_ioctls = 0 (plus ioctls = NULL)
> > > - no setting DRIVER_RENDER and DRIVER_SYNCOBJ, we'd be a pure
> > > display-only driver
> > >
> > > Adding Dave and drm-intel maintainers to quickly hash this out. Thoughts?
> >
> > I'll defer the decision on lmem to folks who actually know this stuff,
> > and focus on display. And from that perspective, I'd like to unblock
> > merging the display patches.
> >
>
> How does display work without LMEM, I'm assuming you have to scan out
> from VRAM on DG1, even if we only have internal non-uapi is this
> enough to bring up fbcon?
It doesn't. And I think merging completely non-functional code to
upstream would be rather pointless, no one (outside from intel) can
test it, so the usual Dave Airlie "how does this benefit upstream"
would get a "not really, just dead weight".
But we have some basic lmem code in upstream already, and afaik it's
not much code to wire this up into dumb_create and intel_fbdev.c.
Which would give us a working kms-only driver (more or less, still
early enabling), which can be tested with what's in upstream only (so
actually somewhat useful, and unblocks all the display upstreaming,
heck we could even do kms-only CI with igt to make sure it keeps
working). And as long as we remove the ioctls and DRIVER_RENDER flag
(wedging the gpu is a bit overkill) I don't think there's any risk for
uapi: As long as the i915 getparam ioctl doesn't work for reading the
chipset id, umds skip (might need to double-check that, worst case we
have to rename the driver to something like "intel-display" to make
sure no one matches).
But yeah I think this series here is not quite there yet.
And then once Joonas we can try and figure out a new plan for
upstreaming lmem refactoring and uapi. When we discussed this all late
last summer just upstreaming kms-only was the first planned step,
altough back then with the render uapi hidden behind a compile flag.
Joonas thinks that's a bit too risk now that we're a lot later.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 48+ messages in thread
* [Intel-gfx] [PATCH v2 08/32] drm/i915/dg1: Add DG1 PCI IDs
2020-06-18 0:42 [Intel-gfx] [PATCH v2 00/32] Introduce DG1 Lucas De Marchi
` (6 preceding siblings ...)
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 07/32] drm/i915/dg1: add initial DG-1 definitions Lucas De Marchi
@ 2020-06-18 0:42 ` Lucas De Marchi
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 09/32] drm/i915/dg1: add support for the master unit interrupt Lucas De Marchi
` (26 subsequent siblings)
34 siblings, 0 replies; 48+ messages in thread
From: Lucas De Marchi @ 2020-06-18 0:42 UTC (permalink / raw)
To: intel-gfx
From: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Bspec: 44463
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/i915_pci.c | 3 ++-
include/drm/i915_pciids.h | 4 ++++
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 58cceeaa0ffa5..8d5b23946d7dd 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -900,7 +900,7 @@ static const struct intel_device_info rkl_info = {
.has_master_unit_irq = 1, \
.is_dgfx = 1
-static const struct intel_device_info intel_dg1_info = {
+static const struct intel_device_info dg1_info = {
GEN12_DGFX_FEATURES,
PLATFORM(INTEL_DG1),
.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
@@ -985,6 +985,7 @@ static const struct pci_device_id pciidlist[] = {
INTEL_EHL_IDS(&ehl_info),
INTEL_TGL_12_IDS(&tgl_info),
INTEL_RKL_IDS(&rkl_info),
+ INTEL_DG1_IDS(&dg1_info),
{0, 0, 0}
};
MODULE_DEVICE_TABLE(pci, pciidlist);
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index bc989de2aac2b..f44fe822880d2 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -614,4 +614,8 @@
INTEL_VGA_DEVICE(0x4C90, info), \
INTEL_VGA_DEVICE(0x4C9A, info)
+/* DG1 */
+#define INTEL_DG1_IDS(info) \
+ INTEL_VGA_DEVICE(0x4905, info)
+
#endif /* _I915_PCIIDS_H */
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 48+ messages in thread* [Intel-gfx] [PATCH v2 09/32] drm/i915/dg1: add support for the master unit interrupt
2020-06-18 0:42 [Intel-gfx] [PATCH v2 00/32] Introduce DG1 Lucas De Marchi
` (7 preceding siblings ...)
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 08/32] drm/i915/dg1: Add DG1 PCI IDs Lucas De Marchi
@ 2020-06-18 0:42 ` Lucas De Marchi
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 10/32] drm/i915/dg1: Remove SHPD_FILTER_CNT register programming Lucas De Marchi
` (25 subsequent siblings)
34 siblings, 0 replies; 48+ messages in thread
From: Lucas De Marchi @ 2020-06-18 0:42 UTC (permalink / raw)
To: intel-gfx
DG1 has master unit interrupt register which is used to indicate the
correct source of interrupt.
v2: fix coding style on register definition
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Cc: Daniele Spurio Ceraolo <daniele.ceraolospurio@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 4 +++
drivers/gpu/drm/i915/i915_irq.c | 56 +++++++++++++++++++++++++++--
drivers/gpu/drm/i915/i915_reg.h | 4 +++
3 files changed, 61 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index bca036ac66212..4e13f7d7dc5de 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -492,6 +492,10 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
seq_printf(m, "PCU interrupt enable:\t%08x\n",
I915_READ(GEN8_PCU_IER));
} else if (INTEL_GEN(dev_priv) >= 11) {
+ if (HAS_MASTER_UNIT_IRQ(dev_priv))
+ seq_printf(m, "Master Unit Interrupt Control: %08x\n",
+ I915_READ(DG1_MSTR_UNIT_INTR));
+
seq_printf(m, "Master Interrupt Control: %08x\n",
I915_READ(GEN11_GFX_MSTR_IRQ));
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 710224d930c53..8652e1e69db72 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2584,6 +2584,46 @@ static irqreturn_t gen11_irq_handler(int irq, void *arg)
gen11_master_intr_enable);
}
+static u32 dg1_master_intr_disable_and_ack(void __iomem * const regs)
+{
+ u32 val;
+
+ /* First disable interrupts */
+ raw_reg_write(regs, DG1_MSTR_UNIT_INTR, 0);
+
+ /* Get the indication levels and ack the master unit */
+ val = raw_reg_read(regs, DG1_MSTR_UNIT_INTR);
+ if (unlikely(!val))
+ return 0;
+
+ raw_reg_write(regs, DG1_MSTR_UNIT_INTR, val);
+
+ /*
+ * Now with master disabled, get a sample of level indications
+ * for this interrupt and ack them right away - we keep GEN11_MASTER_IRQ
+ * out as this bit doesn't exist anymore for DG1
+ */
+ val = raw_reg_read(regs, GEN11_GFX_MSTR_IRQ) & ~GEN11_MASTER_IRQ;
+ if (unlikely(!val))
+ return 0;
+
+ raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, val);
+
+ return val;
+}
+
+static inline void dg1_master_intr_enable(void __iomem * const regs)
+{
+ raw_reg_write(regs, DG1_MSTR_UNIT_INTR, DG1_MSTR_IRQ);
+}
+
+static irqreturn_t dg1_irq_handler(int irq, void *arg)
+{
+ return __gen11_irq_handler(arg,
+ dg1_master_intr_disable_and_ack,
+ dg1_master_intr_enable);
+}
+
/* Called from drm generic code, passed 'crtc' which
* we use as a pipe index
*/
@@ -2922,7 +2962,10 @@ static void gen11_irq_reset(struct drm_i915_private *dev_priv)
{
struct intel_uncore *uncore = &dev_priv->uncore;
- gen11_master_intr_disable(dev_priv->uncore.regs);
+ if (HAS_MASTER_UNIT_IRQ(dev_priv))
+ dg1_master_intr_disable_and_ack(dev_priv->uncore.regs);
+ else
+ gen11_master_intr_disable(dev_priv->uncore.regs);
gen11_gt_irq_reset(&dev_priv->gt);
gen11_display_irq_reset(dev_priv);
@@ -3519,8 +3562,13 @@ static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
I915_WRITE(GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
- gen11_master_intr_enable(uncore->regs);
- POSTING_READ(GEN11_GFX_MSTR_IRQ);
+ if (HAS_MASTER_UNIT_IRQ(dev_priv)) {
+ dg1_master_intr_enable(uncore->regs);
+ POSTING_READ(DG1_MSTR_UNIT_INTR);
+ } else {
+ gen11_master_intr_enable(uncore->regs);
+ POSTING_READ(GEN11_GFX_MSTR_IRQ);
+ }
}
static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
@@ -4045,6 +4093,8 @@ static irq_handler_t intel_irq_handler(struct drm_i915_private *dev_priv)
else
return i8xx_irq_handler;
} else {
+ if (HAS_MASTER_UNIT_IRQ(dev_priv))
+ return dg1_irq_handler;
if (INTEL_GEN(dev_priv) >= 11)
return gen11_irq_handler;
else if (INTEL_GEN(dev_priv) >= 8)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 10f6e46523b6e..52cef469b8b7c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7678,6 +7678,10 @@ enum {
#define GEN11_GT_DW1_IRQ (1 << 1)
#define GEN11_GT_DW0_IRQ (1 << 0)
+#define DG1_MSTR_UNIT_INTR _MMIO(0x190008)
+#define DG1_MSTR_IRQ REG_BIT(31)
+#define DG1_MSTR_UNIT(u) REG_BIT(u)
+
#define GEN11_DISPLAY_INT_CTL _MMIO(0x44200)
#define GEN11_DISPLAY_IRQ_ENABLE (1 << 31)
#define GEN11_AUDIO_CODEC_IRQ (1 << 24)
--
2.26.2
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^ permalink raw reply related [flat|nested] 48+ messages in thread* [Intel-gfx] [PATCH v2 10/32] drm/i915/dg1: Remove SHPD_FILTER_CNT register programming
2020-06-18 0:42 [Intel-gfx] [PATCH v2 00/32] Introduce DG1 Lucas De Marchi
` (8 preceding siblings ...)
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 09/32] drm/i915/dg1: add support for the master unit interrupt Lucas De Marchi
@ 2020-06-18 0:42 ` Lucas De Marchi
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 11/32] drm/i915/dg1: Add fake PCH Lucas De Marchi
` (24 subsequent siblings)
34 siblings, 0 replies; 48+ messages in thread
From: Lucas De Marchi @ 2020-06-18 0:42 UTC (permalink / raw)
To: intel-gfx
From: Anusha Srivatsa <anusha.srivatsa@intel.com>
Bspec asks us to remove the special programming of the
SHPD_FILTER_CNT register which we have been doing since CNP+.
Bspec: 49305
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 8652e1e69db72..48e1686df3416 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3116,7 +3116,8 @@ static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv,
hotplug_irqs = sde_ddi_mask | sde_tc_mask;
enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
- I915_WRITE(SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
+ if (INTEL_PCH_TYPE(dev_priv) <= PCH_TGP)
+ I915_WRITE(SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
--
2.26.2
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^ permalink raw reply related [flat|nested] 48+ messages in thread* [Intel-gfx] [PATCH v2 11/32] drm/i915/dg1: Add fake PCH
2020-06-18 0:42 [Intel-gfx] [PATCH v2 00/32] Introduce DG1 Lucas De Marchi
` (9 preceding siblings ...)
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 10/32] drm/i915/dg1: Remove SHPD_FILTER_CNT register programming Lucas De Marchi
@ 2020-06-18 0:42 ` Lucas De Marchi
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 12/32] drm/i915/dg1: Initialize RAWCLK properly Lucas De Marchi
` (23 subsequent siblings)
34 siblings, 0 replies; 48+ messages in thread
From: Lucas De Marchi @ 2020-06-18 0:42 UTC (permalink / raw)
To: intel-gfx
DG1 has the south engine display on the same PCI device. Ideally we
could use HAS_PCH_SPLIT(), but that macro is misused all across the
code base to rather signify a range of gens. So add a fake one for DG1
to be used where needed.
Cc: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/intel_pch.c | 6 ++++++
drivers/gpu/drm/i915/intel_pch.h | 4 ++++
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c
index c668e99eb2e46..6c97192e9ca87 100644
--- a/drivers/gpu/drm/i915/intel_pch.c
+++ b/drivers/gpu/drm/i915/intel_pch.c
@@ -188,6 +188,12 @@ void intel_detect_pch(struct drm_i915_private *dev_priv)
{
struct pci_dev *pch = NULL;
+ /* DG1 has south engine display on the same PCI device */
+ if (IS_DG1(dev_priv)) {
+ dev_priv->pch_type = PCH_DG1;
+ return;
+ }
+
/*
* The reason to probe ISA bridge instead of Dev31:Fun0 is to
* make graphics device passthrough work easy for VMM, that only
diff --git a/drivers/gpu/drm/i915/intel_pch.h b/drivers/gpu/drm/i915/intel_pch.h
index 3053d1ce398b1..06d2cd50af0b9 100644
--- a/drivers/gpu/drm/i915/intel_pch.h
+++ b/drivers/gpu/drm/i915/intel_pch.h
@@ -26,6 +26,9 @@ enum intel_pch {
PCH_JSP, /* Jasper Lake PCH */
PCH_MCC, /* Mule Creek Canyon PCH */
PCH_TGP, /* Tiger Lake PCH */
+
+ /* Fake PCHs, functionality handled on the same PCI dev */
+ PCH_DG1 = 1024,
};
#define INTEL_PCH_DEVICE_ID_MASK 0xff80
@@ -56,6 +59,7 @@ enum intel_pch {
#define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
#define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
+#define HAS_PCH_DG1(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG1)
#define HAS_PCH_JSP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_JSP)
#define HAS_PCH_MCC(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MCC)
#define HAS_PCH_TGP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_TGP)
--
2.26.2
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^ permalink raw reply related [flat|nested] 48+ messages in thread* [Intel-gfx] [PATCH v2 12/32] drm/i915/dg1: Initialize RAWCLK properly
2020-06-18 0:42 [Intel-gfx] [PATCH v2 00/32] Introduce DG1 Lucas De Marchi
` (10 preceding siblings ...)
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 11/32] drm/i915/dg1: Add fake PCH Lucas De Marchi
@ 2020-06-18 0:42 ` Lucas De Marchi
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 13/32] drm/i915/dg1: Define MOCS table for DG1 Lucas De Marchi
` (22 subsequent siblings)
34 siblings, 0 replies; 48+ messages in thread
From: Lucas De Marchi @ 2020-06-18 0:42 UTC (permalink / raw)
To: intel-gfx
From: Matt Roper <matthew.d.roper@intel.com>
DG1 always uses a 38.4 MHz rawclk rather than the 19.2/24 MHz
frequencies on CNP+. Note that register bits associated with this
frequency confusingly use 37 for the divider field rather than 38 as you
might expect.
For simplicity, let's just assume that this 38.4 MHz frequency will hold
true for other future platforms with "fake" PCH south displays and that
the CNP-style behavior will remain for other platforms with a real PCH.
Bspec: 49950
Bspec: 49309
Cc: Aditya Swarup <aditya.swarup@intel.com>
Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 16 +++++++++++++++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 45f7f33d11447..3aea30ba9f743 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2673,6 +2673,18 @@ void intel_update_cdclk(struct drm_i915_private *dev_priv)
DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000));
}
+static int dg1_rawclk(struct drm_i915_private *dev_priv)
+{
+ /*
+ * DG1 always uses a 38.4 MHz rawclk. The bspec tells us
+ * "Program Numerator=2, Denominator=4, Divider=37 decimal."
+ */
+ I915_WRITE(PCH_RAWCLK_FREQ,
+ CNP_RAWCLK_DEN(4) | CNP_RAWCLK_DIV(37) | ICP_RAWCLK_NUM(2));
+
+ return 38400;
+}
+
static int cnp_rawclk(struct drm_i915_private *dev_priv)
{
u32 rawclk;
@@ -2781,7 +2793,9 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
{
u32 freq;
- if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+ freq = dg1_rawclk(dev_priv);
+ else if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
freq = cnp_rawclk(dev_priv);
else if (HAS_PCH_SPLIT(dev_priv))
freq = pch_rawclk(dev_priv);
--
2.26.2
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^ permalink raw reply related [flat|nested] 48+ messages in thread* [Intel-gfx] [PATCH v2 13/32] drm/i915/dg1: Define MOCS table for DG1
2020-06-18 0:42 [Intel-gfx] [PATCH v2 00/32] Introduce DG1 Lucas De Marchi
` (11 preceding siblings ...)
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 12/32] drm/i915/dg1: Initialize RAWCLK properly Lucas De Marchi
@ 2020-06-18 0:42 ` Lucas De Marchi
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 14/32] drm/i915/dg1: Add DG1 power wells Lucas De Marchi
` (21 subsequent siblings)
34 siblings, 0 replies; 48+ messages in thread
From: Lucas De Marchi @ 2020-06-18 0:42 UTC (permalink / raw)
To: intel-gfx
DG1 has a new MOCS table. We still use the old definition of the table,
but as for any dgfx card it doesn't contain the control_value values
(these values don't matter as we won't program them).
Bspec: 45101
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/gt/intel_mocs.c | 39 +++++++++++++++++++++++++++-
1 file changed, 38 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 632e08a4592b2..7217c6e2087cb 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -280,6 +280,39 @@ static const struct drm_i915_mocs_entry icl_mocs_table[] = {
GEN11_MOCS_ENTRIES
};
+static const struct drm_i915_mocs_entry dg1_mocs_table[] = {
+ /* Error */
+ MOCS_ENTRY(0, 0, L3_0_DIRECT),
+
+ /* UC */
+ MOCS_ENTRY(1, 0, L3_1_UC),
+
+ /* Reserved */
+ MOCS_ENTRY(2, 0, L3_0_DIRECT),
+ MOCS_ENTRY(3, 0, L3_0_DIRECT),
+ MOCS_ENTRY(4, 0, L3_0_DIRECT),
+
+ /* WB - L3 */
+ MOCS_ENTRY(5, 0, L3_3_WB),
+ /* WB - L3 50% */
+ MOCS_ENTRY(6, 0, L3_ESC(1) | L3_SCC(1) | L3_3_WB),
+ /* WB - L3 25% */
+ MOCS_ENTRY(7, 0, L3_ESC(1) | L3_SCC(3) | L3_3_WB),
+ /* WB - L3 12.5% */
+ MOCS_ENTRY(8, 0, L3_ESC(1) | L3_SCC(7) | L3_3_WB),
+
+ /* HDC:L1 + L3 */
+ MOCS_ENTRY(48, 0, L3_3_WB),
+ /* HDC:L1 */
+ MOCS_ENTRY(49, 0, L3_1_UC),
+
+ /* HW Reserved */
+ MOCS_ENTRY(60, 0, L3_1_UC),
+ MOCS_ENTRY(61, 0, L3_1_UC),
+ MOCS_ENTRY(62, 0, L3_1_UC),
+ MOCS_ENTRY(63, 0, L3_1_UC),
+};
+
enum {
HAS_GLOBAL_MOCS = BIT(0),
HAS_ENGINE_MOCS = BIT(1),
@@ -306,7 +339,11 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
{
unsigned int flags;
- if (INTEL_GEN(i915) >= 12) {
+ if (IS_DG1(i915)) {
+ table->size = ARRAY_SIZE(dg1_mocs_table);
+ table->table = dg1_mocs_table;
+ table->n_entries = GEN11_NUM_MOCS_ENTRIES;
+ } else if (INTEL_GEN(i915) >= 12) {
table->size = ARRAY_SIZE(tgl_mocs_table);
table->table = tgl_mocs_table;
table->n_entries = GEN11_NUM_MOCS_ENTRIES;
--
2.26.2
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^ permalink raw reply related [flat|nested] 48+ messages in thread* [Intel-gfx] [PATCH v2 14/32] drm/i915/dg1: Add DG1 power wells
2020-06-18 0:42 [Intel-gfx] [PATCH v2 00/32] Introduce DG1 Lucas De Marchi
` (12 preceding siblings ...)
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 13/32] drm/i915/dg1: Define MOCS table for DG1 Lucas De Marchi
@ 2020-06-18 0:42 ` Lucas De Marchi
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 15/32] drm/i915/dg1: Increase mmio size to 4MB Lucas De Marchi
` (20 subsequent siblings)
34 siblings, 0 replies; 48+ messages in thread
From: Lucas De Marchi @ 2020-06-18 0:42 UTC (permalink / raw)
To: intel-gfx
From: Uma Shankar <uma.shankar@intel.com>
Most of TGL power wells are re-used for DG1. However, AUDIO Power
Domain is moved from PG3 to PG0. Handle the change and initialize
power wells with the new power well structure.
Some of the Audio Streaming logic still remains in PW3 so still
it needs to be enabled.
DDIA, DDIB, TC1 and TC2 are the active ports on DG1.
Need to keep Transcoder C and D to Pipe Power wells, this is against
the spec but else hitting unclaimed register warnings (kept the logic
same as TGL)
Bspec: 49182
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
.../drm/i915/display/intel_display_power.c | 201 +++++++++++++++++-
1 file changed, 200 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 24a2aa1fdc9c1..5dc62e6068f24 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -2970,6 +2970,44 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
BIT_ULL(POWER_DOMAIN_AUX_B) | \
BIT_ULL(POWER_DOMAIN_INIT))
+#define DG1_PW_5_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_D) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_D) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define DG1_PW_4_POWER_DOMAINS ( \
+ DG1_PW_5_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_PIPE_C) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define DG1_PW_3_POWER_DOMAINS ( \
+ DG1_PW_4_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \
+ BIT_ULL(POWER_DOMAIN_AUX_D) | \
+ BIT_ULL(POWER_DOMAIN_AUX_E) | \
+ BIT_ULL(POWER_DOMAIN_VGA) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define DG1_PW_2_POWER_DOMAINS ( \
+ DG1_PW_3_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define DG1_DISPLAY_DC_OFF_POWER_DOMAINS ( \
+ DG1_PW_3_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_MODESET) | \
+ BIT_ULL(POWER_DOMAIN_AUX_A) | \
+ BIT_ULL(POWER_DOMAIN_AUX_B) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
.sync_hw = i9xx_power_well_sync_hw_noop,
.enable = i9xx_always_on_power_well_noop,
@@ -4474,6 +4512,165 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
},
};
+static const struct i915_power_well_desc dg1_power_wells[] = {
+ {
+ .name = "always-on",
+ .always_on = true,
+ .domains = POWER_DOMAIN_MASK,
+ .ops = &i9xx_always_on_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ },
+ {
+ .name = "power well 1",
+ /* Handled by the DMC firmware */
+ .always_on = true,
+ .domains = 0,
+ .ops = &hsw_power_well_ops,
+ .id = SKL_DISP_PW_1,
+ {
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_1,
+ .hsw.has_fuses = true,
+ },
+ },
+ {
+ .name = "DC off",
+ .domains = DG1_DISPLAY_DC_OFF_POWER_DOMAINS,
+ .ops = &gen9_dc_off_power_well_ops,
+ .id = SKL_DISP_DC_OFF,
+ },
+ {
+ .name = "power well 2",
+ .domains = DG1_PW_2_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = SKL_DISP_PW_2,
+ {
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_2,
+ .hsw.has_fuses = true,
+ },
+ },
+ {
+ .name = "power well 3",
+ .domains = DG1_PW_3_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = ICL_DISP_PW_3,
+ {
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_3,
+ .hsw.irq_pipe_mask = BIT(PIPE_B),
+ .hsw.has_vga = true,
+ .hsw.has_fuses = true,
+ },
+ },
+ {
+ .name = "DDI A IO",
+ .domains = ICL_DDI_IO_A_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_ddi_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
+ }
+ },
+ {
+ .name = "DDI B IO",
+ .domains = ICL_DDI_IO_B_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_ddi_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
+ }
+ },
+ {
+ .name = "DDI D TC1 IO",
+ .domains = TGL_DDI_IO_D_TC1_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_ddi_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
+ },
+ },
+ {
+ .name = "DDI E TC2 IO",
+ .domains = TGL_DDI_IO_E_TC2_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_ddi_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
+ },
+ },
+ {
+ .name = "AUX A",
+ .domains = ICL_AUX_A_IO_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
+ },
+ },
+ {
+ .name = "AUX B",
+ .domains = ICL_AUX_B_IO_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
+ },
+ },
+ {
+ .name = "AUX D TC1",
+ .domains = TGL_AUX_D_TC1_IO_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
+ .hsw.is_tc_tbt = false,
+ },
+ },
+ {
+ .name = "AUX E TC2",
+ .domains = TGL_AUX_E_TC2_IO_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
+ .hsw.is_tc_tbt = false,
+ },
+ },
+ {
+ .name = "power well 4",
+ .domains = DG1_PW_4_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_4,
+ .hsw.has_fuses = true,
+ .hsw.irq_pipe_mask = BIT(PIPE_C),
+ }
+ },
+ {
+ .name = "power well 5",
+ .domains = DG1_PW_5_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_PW_5,
+ .hsw.has_fuses = true,
+ .hsw.irq_pipe_mask = BIT(PIPE_D),
+ },
+ },
+};
+
static int
sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
int disable_power_well)
@@ -4622,7 +4819,9 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
* The enabling order will be from lower to higher indexed wells,
* the disabling order is reversed.
*/
- if (IS_ROCKETLAKE(dev_priv)) {
+ if (IS_DG1(dev_priv)) {
+ err = set_power_wells(power_domains, dg1_power_wells);
+ } else if (IS_ROCKETLAKE(dev_priv)) {
err = set_power_wells(power_domains, rkl_power_wells);
} else if (IS_GEN(dev_priv, 12)) {
err = set_power_wells(power_domains, tgl_power_wells);
--
2.26.2
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^ permalink raw reply related [flat|nested] 48+ messages in thread* [Intel-gfx] [PATCH v2 15/32] drm/i915/dg1: Increase mmio size to 4MB
2020-06-18 0:42 [Intel-gfx] [PATCH v2 00/32] Introduce DG1 Lucas De Marchi
` (13 preceding siblings ...)
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 14/32] drm/i915/dg1: Add DG1 power wells Lucas De Marchi
@ 2020-06-18 0:42 ` Lucas De Marchi
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 16/32] drm/i915/dg1: Wait for pcode/uncore handshake at startup Lucas De Marchi
` (19 subsequent siblings)
34 siblings, 0 replies; 48+ messages in thread
From: Lucas De Marchi @ 2020-06-18 0:42 UTC (permalink / raw)
To: intel-gfx
From: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota@intel.com>
On dgfx register range has been extended to go up to 4MB.
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Michael J. Ruhl <michael.j.ruhl@intel.com>
Signed-off-by: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/intel_uncore.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 7d6b9ae7403cb..ed56608ae925a 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1699,11 +1699,15 @@ static int uncore_mmio_setup(struct intel_uncore *uncore)
* clobbering the GTT which we want ioremap_wc instead. Fortunately,
* the register BAR remains the same size for all the earlier
* generations up to Ironlake.
+ * For dgfx chips register range is expanded to 4MB.
*/
if (INTEL_GEN(i915) < 5)
mmio_size = 512 * 1024;
+ else if (IS_DGFX(i915))
+ mmio_size = 4 * 1024 * 1024;
else
mmio_size = 2 * 1024 * 1024;
+
uncore->regs = pci_iomap(pdev, mmio_bar, mmio_size);
if (uncore->regs == NULL) {
drm_err(&i915->drm, "failed to map registers\n");
--
2.26.2
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 48+ messages in thread* [Intel-gfx] [PATCH v2 16/32] drm/i915/dg1: Wait for pcode/uncore handshake at startup
2020-06-18 0:42 [Intel-gfx] [PATCH v2 00/32] Introduce DG1 Lucas De Marchi
` (14 preceding siblings ...)
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 15/32] drm/i915/dg1: Increase mmio size to 4MB Lucas De Marchi
@ 2020-06-18 0:42 ` Lucas De Marchi
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 17/32] drm/i915/dg1: Add DPLL macros for DG1 Lucas De Marchi
` (18 subsequent siblings)
34 siblings, 0 replies; 48+ messages in thread
From: Lucas De Marchi @ 2020-06-18 0:42 UTC (permalink / raw)
To: intel-gfx
From: Matt Roper <matthew.d.roper@intel.com>
DG1 does some additional pcode/uncore handshaking at
boot time; this handshaking must complete before various other pcode
commands are effective and before general work is submitted to the GPU.
We need to poll a new pcode mailbox during startup until it reports that
this handshaking is complete.
The bspec doesn't give guidance on how long we may need to wait for this
handshaking to complete. For now, let's just set a really long timeout;
if we still don't get a completion status by the end of that timeout,
we'll just continue on and hope for the best.
Bspec: 52065
Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 3 +++
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_sideband.c | 15 +++++++++++++++
drivers/gpu/drm/i915/intel_sideband.h | 2 ++
4 files changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 34ee12f3f02d4..58b9c6b778aa4 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -85,6 +85,7 @@
#include "intel_gvt.h"
#include "intel_memory_region.h"
#include "intel_pm.h"
+#include "intel_sideband.h"
#include "vlv_suspend.h"
static struct drm_driver driver;
@@ -741,6 +742,8 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
*/
intel_dram_detect(dev_priv);
+ intel_pcode_init(dev_priv);
+
intel_bw_init_hw(dev_priv);
return 0;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 52cef469b8b7c..cc593c8b43ac3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9164,6 +9164,9 @@ enum {
#define GEN9_SAGV_DISABLE 0x0
#define GEN9_SAGV_IS_DISABLED 0x1
#define GEN9_SAGV_ENABLE 0x3
+#define DG1_PCODE_STATUS 0x7E
+#define DG1_CHECK_UNCORE_INIT_STATUS 0x0
+#define DG1_UNCORE_INIT_COMPLETE 0x1
#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23
#define GEN6_PCODE_DATA _MMIO(0x138128)
#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
index 916ccd1c0e969..8b093525240d6 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -543,3 +543,18 @@ int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request,
return ret ? ret : status;
#undef COND
}
+
+void intel_pcode_init(struct drm_i915_private *i915)
+{
+ int ret;
+
+ if (!IS_DGFX(i915))
+ return;
+
+ ret = skl_pcode_request(i915, DG1_PCODE_STATUS,
+ DG1_CHECK_UNCORE_INIT_STATUS,
+ DG1_UNCORE_INIT_COMPLETE,
+ DG1_UNCORE_INIT_COMPLETE, 50);
+ if (ret)
+ drm_err(&i915->drm, "Pcode did not report uncore initialization completion!\n");
+}
diff --git a/drivers/gpu/drm/i915/intel_sideband.h b/drivers/gpu/drm/i915/intel_sideband.h
index 7fb95745a4449..094c7b19c5d42 100644
--- a/drivers/gpu/drm/i915/intel_sideband.h
+++ b/drivers/gpu/drm/i915/intel_sideband.h
@@ -138,4 +138,6 @@ int sandybridge_pcode_write_timeout(struct drm_i915_private *i915, u32 mbox,
int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request,
u32 reply_mask, u32 reply, int timeout_base_ms);
+void intel_pcode_init(struct drm_i915_private *i915);
+
#endif /* _INTEL_SIDEBAND_H */
--
2.26.2
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 48+ messages in thread* [Intel-gfx] [PATCH v2 17/32] drm/i915/dg1: Add DPLL macros for DG1
2020-06-18 0:42 [Intel-gfx] [PATCH v2 00/32] Introduce DG1 Lucas De Marchi
` (15 preceding siblings ...)
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 16/32] drm/i915/dg1: Wait for pcode/uncore handshake at startup Lucas De Marchi
@ 2020-06-18 0:42 ` Lucas De Marchi
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 18/32] drm/i915/dg1: Add and setup DPLLs " Lucas De Marchi
` (17 subsequent siblings)
34 siblings, 0 replies; 48+ messages in thread
From: Lucas De Marchi @ 2020-06-18 0:42 UTC (permalink / raw)
To: intel-gfx
From: Aditya Swarup <aditya.swarup@intel.com>
DG1 has 4 DPLLs where DPLL0 and DPLL1 drive DDIA/B and
DPLL2 and DPLL3 drive DDIC/DDID.
Introduce DG1_DPLL_CFCRx() helper macros to configure
DPLL registers.
Bspec: 50288, 50299
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 17 +++++++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 15 +++++++++++++++
2 files changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index edcc43f4670ff..325d22bf7b9ef 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -154,6 +154,23 @@ enum intel_dpll_id {
* @DPLL_ID_TGL_MGPLL6: TGL TC PLL port 6 (TC6)
*/
DPLL_ID_TGL_MGPLL6,
+
+ /**
+ * @DPLL_ID_DG1_DPLL0: DG1 combo PHY DPLL0
+ */
+ DPLL_ID_DG1_DPLL0 = 0,
+ /**
+ * @DPLL_ID_DG1_DPLL1: DG1 combo PHY DPLL1
+ */
+ DPLL_ID_DG1_DPLL1,
+ /**
+ * @DPLL_ID_DG1_DPLL2: DG1 combo PHY DPLL2
+ */
+ DPLL_ID_DG1_DPLL2,
+ /**
+ * @DPLL_ID_DG1_DPLL3: DG1 combo PHY DPLL3
+ */
+ DPLL_ID_DG1_DPLL3,
};
#define I915_NUM_PLLS 9
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cc593c8b43ac3..7519371a5144e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -242,6 +242,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
#define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
#define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
+#define _MMIO_PLL3(pll, ...) _MMIO(_PICK(pll, __VA_ARGS__))
/*
* Device info offset array based helpers for groups of registers with unevenly
@@ -10458,6 +10459,20 @@ enum skl_power_gate {
#define TGL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \
_TGL_DPLL1_CFGCR1)
+#define _DG1_DPLL2_CFGCR0 0x16C284
+#define _DG1_DPLL3_CFGCR0 0x16C28C
+#define DG1_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
+ _TGL_DPLL1_CFGCR0, \
+ _DG1_DPLL2_CFGCR0, \
+ _DG1_DPLL3_CFGCR0)
+
+#define _DG1_DPLL2_CFGCR1 0x16C288
+#define _DG1_DPLL3_CFGCR1 0x16C290
+#define DG1_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
+ _TGL_DPLL1_CFGCR1, \
+ _DG1_DPLL2_CFGCR1, \
+ _DG1_DPLL3_CFGCR1)
+
#define _DKL_PHY1_BASE 0x168000
#define _DKL_PHY2_BASE 0x169000
#define _DKL_PHY3_BASE 0x16A000
--
2.26.2
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^ permalink raw reply related [flat|nested] 48+ messages in thread* [Intel-gfx] [PATCH v2 18/32] drm/i915/dg1: Add and setup DPLLs for DG1
2020-06-18 0:42 [Intel-gfx] [PATCH v2 00/32] Introduce DG1 Lucas De Marchi
` (16 preceding siblings ...)
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 17/32] drm/i915/dg1: Add DPLL macros for DG1 Lucas De Marchi
@ 2020-06-18 0:42 ` Lucas De Marchi
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 19/32] drm/i915/dg1: Enable DPLL " Lucas De Marchi
` (16 subsequent siblings)
34 siblings, 0 replies; 48+ messages in thread
From: Lucas De Marchi @ 2020-06-18 0:42 UTC (permalink / raw)
To: intel-gfx
From: Aditya Swarup <aditya.swarup@intel.com>
Add entries for dg1 plls and setup dg1_pll_mgr to reuse icl callbacks.
Initial setup for shared dplls DPLL0/1 for DDIA/B and DPLL2/3 for
DDIC/D. Configure dpll cfgcrx registers to drive the plls on DG1.
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 41 +++++++++++++++++--
1 file changed, 37 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 6f59f9ec453bf..ed2d007d2687e 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3527,7 +3527,17 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state,
return false;
}
- if (IS_ROCKETLAKE(dev_priv)) {
+ if (IS_DG1(dev_priv)) {
+ if (port == PORT_D || port == PORT_E) {
+ dpll_mask =
+ BIT(DPLL_ID_DG1_DPLL2) |
+ BIT(DPLL_ID_DG1_DPLL3);
+ } else {
+ dpll_mask =
+ BIT(DPLL_ID_DG1_DPLL0) |
+ BIT(DPLL_ID_DG1_DPLL1);
+ }
+ } else if (IS_ROCKETLAKE(dev_priv)) {
dpll_mask =
BIT(DPLL_ID_EHL_DPLL4) |
BIT(DPLL_ID_ICL_DPLL1) |
@@ -3817,7 +3827,10 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
if (!(val & PLL_ENABLE))
goto out;
- if (INTEL_GEN(dev_priv) >= 12) {
+ if (IS_DG1(dev_priv)) {
+ hw_state->cfgcr0 = intel_de_read(dev_priv, DG1_DPLL_CFGCR0(id));
+ hw_state->cfgcr1 = intel_de_read(dev_priv, DG1_DPLL_CFGCR1(id));
+ } else if (INTEL_GEN(dev_priv) >= 12) {
hw_state->cfgcr0 = intel_de_read(dev_priv,
TGL_DPLL_CFGCR0(id));
hw_state->cfgcr1 = intel_de_read(dev_priv,
@@ -3870,7 +3883,10 @@ static void icl_dpll_write(struct drm_i915_private *dev_priv,
const enum intel_dpll_id id = pll->info->id;
i915_reg_t cfgcr0_reg, cfgcr1_reg;
- if (INTEL_GEN(dev_priv) >= 12) {
+ if (IS_DG1(dev_priv)) {
+ cfgcr0_reg = DG1_DPLL_CFGCR0(id);
+ cfgcr1_reg = DG1_DPLL_CFGCR1(id);
+ } else if (INTEL_GEN(dev_priv) >= 12) {
cfgcr0_reg = TGL_DPLL_CFGCR0(id);
cfgcr1_reg = TGL_DPLL_CFGCR1(id);
} else {
@@ -4317,6 +4333,21 @@ static const struct intel_dpll_mgr rkl_pll_mgr = {
.dump_hw_state = icl_dump_hw_state,
};
+static const struct dpll_info dg1_plls[] = {
+ { "DPLL 0", &combo_pll_funcs, DPLL_ID_DG1_DPLL0, 0 },
+ { "DPLL 1", &combo_pll_funcs, DPLL_ID_DG1_DPLL1, 0 },
+ { "DPLL 2", &combo_pll_funcs, DPLL_ID_DG1_DPLL2, 0 },
+ { "DPLL 3", &combo_pll_funcs, DPLL_ID_DG1_DPLL3, 0 },
+ { },
+};
+
+static const struct intel_dpll_mgr dg1_pll_mgr = {
+ .dpll_info = dg1_plls,
+ .get_dplls = icl_get_dplls,
+ .put_dplls = icl_put_dplls,
+ .dump_hw_state = icl_dump_hw_state,
+};
+
/**
* intel_shared_dpll_init - Initialize shared DPLLs
* @dev: drm device
@@ -4330,7 +4361,9 @@ void intel_shared_dpll_init(struct drm_device *dev)
const struct dpll_info *dpll_info;
int i;
- if (IS_ROCKETLAKE(dev_priv))
+ if (IS_DG1(dev_priv))
+ dpll_mgr = &dg1_pll_mgr;
+ else if (IS_ROCKETLAKE(dev_priv))
dpll_mgr = &rkl_pll_mgr;
else if (INTEL_GEN(dev_priv) >= 12)
dpll_mgr = &tgl_pll_mgr;
--
2.26.2
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^ permalink raw reply related [flat|nested] 48+ messages in thread* [Intel-gfx] [PATCH v2 19/32] drm/i915/dg1: Enable DPLL for DG1
2020-06-18 0:42 [Intel-gfx] [PATCH v2 00/32] Introduce DG1 Lucas De Marchi
` (17 preceding siblings ...)
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 18/32] drm/i915/dg1: Add and setup DPLLs " Lucas De Marchi
@ 2020-06-18 0:42 ` Lucas De Marchi
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 20/32] drm/i915/dg1: add hpd interrupt handling Lucas De Marchi
` (15 subsequent siblings)
34 siblings, 0 replies; 48+ messages in thread
From: Lucas De Marchi @ 2020-06-18 0:42 UTC (permalink / raw)
To: intel-gfx
From: Aditya Swarup <aditya.swarup@intel.com>
Add DG1 DPLL Enable register macro and use the macro to enable the
correct DPLL based on PLL id.
Bspec: 49443, 49206
Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 30 ++++++++++++-------
drivers/gpu/drm/i915/i915_reg.h | 4 +++
2 files changed, 24 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index ed2d007d2687e..7035280e2e9ea 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3859,12 +3859,14 @@ static bool combo_pll_get_hw_state(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll,
struct intel_dpll_hw_state *hw_state)
{
- i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
+ i915_reg_t enable_reg;
- if (IS_ELKHARTLAKE(dev_priv) &&
- pll->info->id == DPLL_ID_EHL_DPLL4) {
+ if (IS_DG1(dev_priv))
+ enable_reg = DG1_DPLL_ENABLE(pll->info->id);
+ else if (IS_ELKHARTLAKE(dev_priv) && pll->info->id == DPLL_ID_EHL_DPLL4)
enable_reg = MG_PLL_ENABLE(0);
- }
+ else
+ enable_reg = CNL_DPLL_ENABLE(pll->info->id);
return icl_pll_get_hw_state(dev_priv, pll, hw_state, enable_reg);
}
@@ -4062,10 +4064,12 @@ static void icl_pll_enable(struct drm_i915_private *dev_priv,
static void combo_pll_enable(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll)
{
- i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
+ i915_reg_t enable_reg;
- if (IS_ELKHARTLAKE(dev_priv) &&
- pll->info->id == DPLL_ID_EHL_DPLL4) {
+ if (IS_DG1(dev_priv)) {
+ enable_reg = DG1_DPLL_ENABLE(pll->info->id);
+ } else if (IS_ELKHARTLAKE(dev_priv) &&
+ pll->info->id == DPLL_ID_EHL_DPLL4) {
enable_reg = MG_PLL_ENABLE(0);
/*
@@ -4075,6 +4079,8 @@ static void combo_pll_enable(struct drm_i915_private *dev_priv,
*/
pll->wakeref = intel_display_power_get(dev_priv,
POWER_DOMAIN_DPLL_DC_OFF);
+ } else {
+ enable_reg = CNL_DPLL_ENABLE(pll->info->id);
}
icl_pll_power_enable(dev_priv, pll, enable_reg);
@@ -4174,16 +4180,20 @@ static void icl_pll_disable(struct drm_i915_private *dev_priv,
static void combo_pll_disable(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll)
{
- i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
+ i915_reg_t enable_reg;
- if (IS_ELKHARTLAKE(dev_priv) &&
- pll->info->id == DPLL_ID_EHL_DPLL4) {
+ if (IS_DG1(dev_priv)) {
+ enable_reg = DG1_DPLL_ENABLE(pll->info->id);
+ } else if (IS_ELKHARTLAKE(dev_priv) &&
+ pll->info->id == DPLL_ID_EHL_DPLL4) {
enable_reg = MG_PLL_ENABLE(0);
icl_pll_disable(dev_priv, pll, enable_reg);
intel_display_power_put(dev_priv, POWER_DOMAIN_DPLL_DC_OFF,
pll->wakeref);
return;
+ } else {
+ enable_reg = CNL_DPLL_ENABLE(pll->info->id);
}
icl_pll_disable(dev_priv, pll, enable_reg);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7519371a5144e..6649aeca25d72 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10251,6 +10251,10 @@ enum skl_power_gate {
#define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \
_MG_PLL2_ENABLE)
+/* DG1 PLL */
+#define DG1_DPLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \
+ _MG_PLL1_ENABLE, _MG_PLL2_ENABLE)
+
#define _MG_REFCLKIN_CTL_PORT1 0x16892C
#define _MG_REFCLKIN_CTL_PORT2 0x16992C
#define _MG_REFCLKIN_CTL_PORT3 0x16A92C
--
2.26.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 48+ messages in thread* [Intel-gfx] [PATCH v2 20/32] drm/i915/dg1: add hpd interrupt handling
2020-06-18 0:42 [Intel-gfx] [PATCH v2 00/32] Introduce DG1 Lucas De Marchi
` (18 preceding siblings ...)
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 19/32] drm/i915/dg1: Enable DPLL " Lucas De Marchi
@ 2020-06-18 0:42 ` Lucas De Marchi
2020-06-22 18:35 ` Imre Deak
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 21/32] drm/i915/dg1: invert HPD pins Lucas De Marchi
` (14 subsequent siblings)
34 siblings, 1 reply; 48+ messages in thread
From: Lucas De Marchi @ 2020-06-18 0:42 UTC (permalink / raw)
To: intel-gfx
DG1 has one more combo phy port, no TC and all irq handling goes through
SDE, like for MCC.
Cc: Anshuman Gupta <anshuman.gupta@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 57 +++++++++++++++++++++++++++++----
drivers/gpu/drm/i915/i915_reg.h | 8 +++++
2 files changed, 59 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 48e1686df3416..3707f9231171f 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -167,6 +167,13 @@ static const u32 hpd_tgp[HPD_NUM_PINS] = {
[HPD_PORT_I] = SDE_TC_HOTPLUG_ICP(PORT_TC6),
};
+static const u32 hpd_dg1_sde[HPD_NUM_PINS] = {
+ [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PHY_A),
+ [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PHY_B),
+ [HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(PHY_C),
+ [HPD_PORT_E] = SDE_DDI_HOTPLUG_ICP(PHY_D),
+};
+
static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
{
struct i915_hotplug *hpd = &dev_priv->hotplug;
@@ -193,10 +200,13 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
else
hpd->hpd = hpd_ilk;
- if (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv))
+ if ((INTEL_PCH_TYPE(dev_priv) < PCH_DG1) &&
+ (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv)))
return;
- if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv))
+ if (HAS_PCH_DG1(dev_priv))
+ hpd->pch_hpd = hpd_dg1_sde;
+ else if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv))
hpd->pch_hpd = hpd_tgp;
else if (HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv))
hpd->pch_hpd = hpd_icp;
@@ -1145,6 +1155,22 @@ static bool tgp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
}
}
+static bool dg1_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
+{
+ switch (pin) {
+ case HPD_PORT_A:
+ return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_A);
+ case HPD_PORT_B:
+ return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_B);
+ case HPD_PORT_D:
+ return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_C);
+ case HPD_PORT_E:
+ return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_D);
+ default:
+ return false;
+ }
+}
+
static bool spt_port_hotplug2_long_detect(enum hpd_pin pin, u32 val)
{
switch (pin) {
@@ -1893,13 +1919,20 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
u32 ddi_hotplug_trigger, tc_hotplug_trigger;
u32 pin_mask = 0, long_mask = 0;
bool (*tc_port_hotplug_long_detect)(enum hpd_pin pin, u32 val);
+ bool (*ddi_port_hotplug_long_detect)(enum hpd_pin pin, u32 val);
- if (HAS_PCH_TGP(dev_priv)) {
+ if (HAS_PCH_DG1(dev_priv)) {
+ ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_DG1;
+ ddi_port_hotplug_long_detect = dg1_ddi_port_hotplug_long_detect;
+ tc_hotplug_trigger = 0;
+ } else if (HAS_PCH_TGP(dev_priv)) {
ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
+ ddi_port_hotplug_long_detect = icp_ddi_port_hotplug_long_detect;
tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP;
tc_port_hotplug_long_detect = tgp_tc_port_hotplug_long_detect;
} else if (HAS_PCH_JSP(dev_priv)) {
ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
+ ddi_port_hotplug_long_detect = icp_ddi_port_hotplug_long_detect;
tc_hotplug_trigger = 0;
} else if (HAS_PCH_MCC(dev_priv)) {
ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
@@ -1911,6 +1944,7 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
INTEL_PCH_TYPE(dev_priv));
ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
+ ddi_port_hotplug_long_detect = icp_ddi_port_hotplug_long_detect;
tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
tc_port_hotplug_long_detect = icp_tc_port_hotplug_long_detect;
}
@@ -1924,7 +1958,7 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
ddi_hotplug_trigger, dig_hotplug_reg,
dev_priv->hotplug.pch_hpd,
- icp_ddi_port_hotplug_long_detect);
+ ddi_port_hotplug_long_detect);
}
if (tc_hotplug_trigger) {
@@ -3147,6 +3181,13 @@ static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv)
TGP_DDI_HPD_ENABLE_MASK, 0);
}
+static void dg1_hpd_irq_setup(struct drm_i915_private *dev_priv)
+{
+ icp_hpd_irq_setup(dev_priv,
+ SDE_DDI_MASK_DG1, 0,
+ DG1_DDI_HPD_ENABLE_MASK, 0);
+}
+
static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
{
u32 hotplug;
@@ -3535,7 +3576,9 @@ static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
I915_WRITE(SDEIMR, ~mask);
- if (HAS_PCH_TGP(dev_priv))
+ if (HAS_PCH_DG1(dev_priv))
+ icp_hpd_detection_setup(dev_priv, DG1_DDI_HPD_ENABLE_MASK, 0);
+ else if (HAS_PCH_TGP(dev_priv))
icp_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK,
TGP_TC_HPD_ENABLE_MASK);
else if (HAS_PCH_JSP(dev_priv))
@@ -4051,7 +4094,9 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
if (I915_HAS_HOTPLUG(dev_priv))
dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
} else {
- if (HAS_PCH_JSP(dev_priv))
+ if (HAS_PCH_DG1(dev_priv))
+ dev_priv->display.hpd_irq_setup = dg1_hpd_irq_setup;
+ else if (HAS_PCH_JSP(dev_priv))
dev_priv->display.hpd_irq_setup = jsp_hpd_irq_setup;
else if (HAS_PCH_MCC(dev_priv))
dev_priv->display.hpd_irq_setup = mcc_hpd_irq_setup;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6649aeca25d72..13a989f5e8dd3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8168,6 +8168,10 @@ enum {
SDE_TC_HOTPLUG_ICP(PORT_TC3) | \
SDE_TC_HOTPLUG_ICP(PORT_TC2) | \
SDE_TC_HOTPLUG_ICP(PORT_TC1))
+#define SDE_DDI_MASK_DG1 (SDE_DDI_HOTPLUG_ICP(PORT_D) | \
+ SDE_DDI_HOTPLUG_ICP(PORT_C) | \
+ SDE_DDI_HOTPLUG_ICP(PORT_B) | \
+ SDE_DDI_HOTPLUG_ICP(PORT_A))
#define SDEISR _MMIO(0xc4000)
#define SDEIMR _MMIO(0xc4004)
@@ -8367,6 +8371,10 @@ enum {
#define TGP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(PORT_TC6) | \
ICP_TC_HPD_ENABLE(PORT_TC5) | \
ICP_TC_HPD_ENABLE_MASK)
+#define DG1_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_D) | \
+ SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_C) | \
+ SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \
+ SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A))
#define _PCH_DPLL_A 0xc6014
#define _PCH_DPLL_B 0xc6018
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 48+ messages in thread* Re: [Intel-gfx] [PATCH v2 20/32] drm/i915/dg1: add hpd interrupt handling
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 20/32] drm/i915/dg1: add hpd interrupt handling Lucas De Marchi
@ 2020-06-22 18:35 ` Imre Deak
2020-06-22 20:43 ` Lucas De Marchi
0 siblings, 1 reply; 48+ messages in thread
From: Imre Deak @ 2020-06-22 18:35 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
On Wed, Jun 17, 2020 at 05:42:28PM -0700, Lucas De Marchi wrote:
> DG1 has one more combo phy port, no TC and all irq handling goes through
> SDE, like for MCC.
>
> Cc: Anshuman Gupta <anshuman.gupta@intel.com>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 57 +++++++++++++++++++++++++++++----
> drivers/gpu/drm/i915/i915_reg.h | 8 +++++
> 2 files changed, 59 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 48e1686df3416..3707f9231171f 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -167,6 +167,13 @@ static const u32 hpd_tgp[HPD_NUM_PINS] = {
> [HPD_PORT_I] = SDE_TC_HOTPLUG_ICP(PORT_TC6),
> };
>
> +static const u32 hpd_dg1_sde[HPD_NUM_PINS] = {
> + [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PHY_A),
> + [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PHY_B),
> + [HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(PHY_C),
> + [HPD_PORT_E] = SDE_DDI_HOTPLUG_ICP(PHY_D),
The above 2 entries look incorrect. encoder->hpd_pin will be assigned
based on the encoder/port's PHY (see intel_hpd_pin_default()). On DG1
port D is connected to PHY C and port E is connected to PHY D. So the
above two pin definitions should be:
[HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(PHY_C),
[HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(PHY_D),
> +};
> +
> static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
> {
> struct i915_hotplug *hpd = &dev_priv->hotplug;
> @@ -193,10 +200,13 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
> else
> hpd->hpd = hpd_ilk;
>
> - if (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv))
> + if ((INTEL_PCH_TYPE(dev_priv) < PCH_DG1) &&
> + (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv)))
> return;
>
> - if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv))
> + if (HAS_PCH_DG1(dev_priv))
> + hpd->pch_hpd = hpd_dg1_sde;
> + else if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv))
> hpd->pch_hpd = hpd_tgp;
> else if (HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv))
> hpd->pch_hpd = hpd_icp;
> @@ -1145,6 +1155,22 @@ static bool tgp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
> }
> }
>
> +static bool dg1_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
> +{
> + switch (pin) {
> + case HPD_PORT_A:
> + return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_A);
> + case HPD_PORT_B:
> + return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_B);
> + case HPD_PORT_D:
> + return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_C);
> + case HPD_PORT_E:
> + return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_D);
> + default:
> + return false;
> + }
> +}
> +
> static bool spt_port_hotplug2_long_detect(enum hpd_pin pin, u32 val)
> {
> switch (pin) {
> @@ -1893,13 +1919,20 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
> u32 ddi_hotplug_trigger, tc_hotplug_trigger;
> u32 pin_mask = 0, long_mask = 0;
> bool (*tc_port_hotplug_long_detect)(enum hpd_pin pin, u32 val);
> + bool (*ddi_port_hotplug_long_detect)(enum hpd_pin pin, u32 val);
>
> - if (HAS_PCH_TGP(dev_priv)) {
> + if (HAS_PCH_DG1(dev_priv)) {
> + ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_DG1;
> + ddi_port_hotplug_long_detect = dg1_ddi_port_hotplug_long_detect;
> + tc_hotplug_trigger = 0;
> + } else if (HAS_PCH_TGP(dev_priv)) {
> ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
> + ddi_port_hotplug_long_detect = icp_ddi_port_hotplug_long_detect;
> tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP;
> tc_port_hotplug_long_detect = tgp_tc_port_hotplug_long_detect;
> } else if (HAS_PCH_JSP(dev_priv)) {
> ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
> + ddi_port_hotplug_long_detect = icp_ddi_port_hotplug_long_detect;
> tc_hotplug_trigger = 0;
> } else if (HAS_PCH_MCC(dev_priv)) {
> ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
> @@ -1911,6 +1944,7 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
> INTEL_PCH_TYPE(dev_priv));
>
> ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
> + ddi_port_hotplug_long_detect = icp_ddi_port_hotplug_long_detect;
> tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
> tc_port_hotplug_long_detect = icp_tc_port_hotplug_long_detect;
> }
> @@ -1924,7 +1958,7 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
> intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
> ddi_hotplug_trigger, dig_hotplug_reg,
> dev_priv->hotplug.pch_hpd,
> - icp_ddi_port_hotplug_long_detect);
> + ddi_port_hotplug_long_detect);
> }
>
> if (tc_hotplug_trigger) {
> @@ -3147,6 +3181,13 @@ static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv)
> TGP_DDI_HPD_ENABLE_MASK, 0);
> }
>
> +static void dg1_hpd_irq_setup(struct drm_i915_private *dev_priv)
> +{
> + icp_hpd_irq_setup(dev_priv,
> + SDE_DDI_MASK_DG1, 0,
> + DG1_DDI_HPD_ENABLE_MASK, 0);
> +}
> +
> static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
> {
> u32 hotplug;
> @@ -3535,7 +3576,9 @@ static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
> I915_WRITE(SDEIMR, ~mask);
>
> - if (HAS_PCH_TGP(dev_priv))
> + if (HAS_PCH_DG1(dev_priv))
> + icp_hpd_detection_setup(dev_priv, DG1_DDI_HPD_ENABLE_MASK, 0);
> + else if (HAS_PCH_TGP(dev_priv))
> icp_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK,
> TGP_TC_HPD_ENABLE_MASK);
> else if (HAS_PCH_JSP(dev_priv))
> @@ -4051,7 +4094,9 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
> if (I915_HAS_HOTPLUG(dev_priv))
> dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
> } else {
> - if (HAS_PCH_JSP(dev_priv))
> + if (HAS_PCH_DG1(dev_priv))
> + dev_priv->display.hpd_irq_setup = dg1_hpd_irq_setup;
> + else if (HAS_PCH_JSP(dev_priv))
> dev_priv->display.hpd_irq_setup = jsp_hpd_irq_setup;
> else if (HAS_PCH_MCC(dev_priv))
> dev_priv->display.hpd_irq_setup = mcc_hpd_irq_setup;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 6649aeca25d72..13a989f5e8dd3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8168,6 +8168,10 @@ enum {
> SDE_TC_HOTPLUG_ICP(PORT_TC3) | \
> SDE_TC_HOTPLUG_ICP(PORT_TC2) | \
> SDE_TC_HOTPLUG_ICP(PORT_TC1))
> +#define SDE_DDI_MASK_DG1 (SDE_DDI_HOTPLUG_ICP(PORT_D) | \
> + SDE_DDI_HOTPLUG_ICP(PORT_C) | \
> + SDE_DDI_HOTPLUG_ICP(PORT_B) | \
> + SDE_DDI_HOTPLUG_ICP(PORT_A))
>
> #define SDEISR _MMIO(0xc4000)
> #define SDEIMR _MMIO(0xc4004)
> @@ -8367,6 +8371,10 @@ enum {
> #define TGP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(PORT_TC6) | \
> ICP_TC_HPD_ENABLE(PORT_TC5) | \
> ICP_TC_HPD_ENABLE_MASK)
> +#define DG1_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_D) | \
> + SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_C) | \
> + SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \
> + SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A))
>
> #define _PCH_DPLL_A 0xc6014
> #define _PCH_DPLL_B 0xc6018
> --
> 2.26.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 48+ messages in thread* Re: [Intel-gfx] [PATCH v2 20/32] drm/i915/dg1: add hpd interrupt handling
2020-06-22 18:35 ` Imre Deak
@ 2020-06-22 20:43 ` Lucas De Marchi
2020-06-22 20:54 ` Imre Deak
0 siblings, 1 reply; 48+ messages in thread
From: Lucas De Marchi @ 2020-06-22 20:43 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Mon, Jun 22, 2020 at 09:35:09PM +0300, Imre Deak wrote:
>On Wed, Jun 17, 2020 at 05:42:28PM -0700, Lucas De Marchi wrote:
>> DG1 has one more combo phy port, no TC and all irq handling goes through
>> SDE, like for MCC.
>>
>> Cc: Anshuman Gupta <anshuman.gupta@intel.com>
>> Cc: José Roberto de Souza <jose.souza@intel.com>
>> Cc: Imre Deak <imre.deak@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_irq.c | 57 +++++++++++++++++++++++++++++----
>> drivers/gpu/drm/i915/i915_reg.h | 8 +++++
>> 2 files changed, 59 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>> index 48e1686df3416..3707f9231171f 100644
>> --- a/drivers/gpu/drm/i915/i915_irq.c
>> +++ b/drivers/gpu/drm/i915/i915_irq.c
>> @@ -167,6 +167,13 @@ static const u32 hpd_tgp[HPD_NUM_PINS] = {
>> [HPD_PORT_I] = SDE_TC_HOTPLUG_ICP(PORT_TC6),
>> };
>>
>> +static const u32 hpd_dg1_sde[HPD_NUM_PINS] = {
>> + [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PHY_A),
>> + [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PHY_B),
>> + [HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(PHY_C),
>> + [HPD_PORT_E] = SDE_DDI_HOTPLUG_ICP(PHY_D),
>
>The above 2 entries look incorrect. encoder->hpd_pin will be assigned
>based on the encoder/port's PHY (see intel_hpd_pin_default()). On DG1
Humn... it was not like that. It seems to have changed recently:
270810a73210 ("drm/i915/hotplug: Use phy to get the hpd_pin instead of the port (v5)")
Thanks for spotting that.
Lucas De Marchi
>port D is connected to PHY C and port E is connected to PHY D. So the
>above two pin definitions should be:
>
> [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(PHY_C),
> [HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(PHY_D),
>
>> +};
>> +
>> static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
>> {
>> struct i915_hotplug *hpd = &dev_priv->hotplug;
>> @@ -193,10 +200,13 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
>> else
>> hpd->hpd = hpd_ilk;
>>
>> - if (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv))
>> + if ((INTEL_PCH_TYPE(dev_priv) < PCH_DG1) &&
>> + (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv)))
>> return;
>>
>> - if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv))
>> + if (HAS_PCH_DG1(dev_priv))
>> + hpd->pch_hpd = hpd_dg1_sde;
>> + else if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv))
>> hpd->pch_hpd = hpd_tgp;
>> else if (HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv))
>> hpd->pch_hpd = hpd_icp;
>> @@ -1145,6 +1155,22 @@ static bool tgp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
>> }
>> }
>>
>> +static bool dg1_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
>> +{
>> + switch (pin) {
>> + case HPD_PORT_A:
>> + return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_A);
>> + case HPD_PORT_B:
>> + return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_B);
>> + case HPD_PORT_D:
>> + return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_C);
>> + case HPD_PORT_E:
>> + return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_D);
>> + default:
>> + return false;
>> + }
>> +}
>> +
>> static bool spt_port_hotplug2_long_detect(enum hpd_pin pin, u32 val)
>> {
>> switch (pin) {
>> @@ -1893,13 +1919,20 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
>> u32 ddi_hotplug_trigger, tc_hotplug_trigger;
>> u32 pin_mask = 0, long_mask = 0;
>> bool (*tc_port_hotplug_long_detect)(enum hpd_pin pin, u32 val);
>> + bool (*ddi_port_hotplug_long_detect)(enum hpd_pin pin, u32 val);
>>
>> - if (HAS_PCH_TGP(dev_priv)) {
>> + if (HAS_PCH_DG1(dev_priv)) {
>> + ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_DG1;
>> + ddi_port_hotplug_long_detect = dg1_ddi_port_hotplug_long_detect;
>> + tc_hotplug_trigger = 0;
>> + } else if (HAS_PCH_TGP(dev_priv)) {
>> ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
>> + ddi_port_hotplug_long_detect = icp_ddi_port_hotplug_long_detect;
>> tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP;
>> tc_port_hotplug_long_detect = tgp_tc_port_hotplug_long_detect;
>> } else if (HAS_PCH_JSP(dev_priv)) {
>> ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
>> + ddi_port_hotplug_long_detect = icp_ddi_port_hotplug_long_detect;
>> tc_hotplug_trigger = 0;
>> } else if (HAS_PCH_MCC(dev_priv)) {
>> ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
>> @@ -1911,6 +1944,7 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
>> INTEL_PCH_TYPE(dev_priv));
>>
>> ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
>> + ddi_port_hotplug_long_detect = icp_ddi_port_hotplug_long_detect;
>> tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
>> tc_port_hotplug_long_detect = icp_tc_port_hotplug_long_detect;
>> }
>> @@ -1924,7 +1958,7 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
>> intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
>> ddi_hotplug_trigger, dig_hotplug_reg,
>> dev_priv->hotplug.pch_hpd,
>> - icp_ddi_port_hotplug_long_detect);
>> + ddi_port_hotplug_long_detect);
>> }
>>
>> if (tc_hotplug_trigger) {
>> @@ -3147,6 +3181,13 @@ static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv)
>> TGP_DDI_HPD_ENABLE_MASK, 0);
>> }
>>
>> +static void dg1_hpd_irq_setup(struct drm_i915_private *dev_priv)
>> +{
>> + icp_hpd_irq_setup(dev_priv,
>> + SDE_DDI_MASK_DG1, 0,
>> + DG1_DDI_HPD_ENABLE_MASK, 0);
>> +}
>> +
>> static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
>> {
>> u32 hotplug;
>> @@ -3535,7 +3576,9 @@ static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
>> gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
>> I915_WRITE(SDEIMR, ~mask);
>>
>> - if (HAS_PCH_TGP(dev_priv))
>> + if (HAS_PCH_DG1(dev_priv))
>> + icp_hpd_detection_setup(dev_priv, DG1_DDI_HPD_ENABLE_MASK, 0);
>> + else if (HAS_PCH_TGP(dev_priv))
>> icp_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK,
>> TGP_TC_HPD_ENABLE_MASK);
>> else if (HAS_PCH_JSP(dev_priv))
>> @@ -4051,7 +4094,9 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
>> if (I915_HAS_HOTPLUG(dev_priv))
>> dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
>> } else {
>> - if (HAS_PCH_JSP(dev_priv))
>> + if (HAS_PCH_DG1(dev_priv))
>> + dev_priv->display.hpd_irq_setup = dg1_hpd_irq_setup;
>> + else if (HAS_PCH_JSP(dev_priv))
>> dev_priv->display.hpd_irq_setup = jsp_hpd_irq_setup;
>> else if (HAS_PCH_MCC(dev_priv))
>> dev_priv->display.hpd_irq_setup = mcc_hpd_irq_setup;
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 6649aeca25d72..13a989f5e8dd3 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -8168,6 +8168,10 @@ enum {
>> SDE_TC_HOTPLUG_ICP(PORT_TC3) | \
>> SDE_TC_HOTPLUG_ICP(PORT_TC2) | \
>> SDE_TC_HOTPLUG_ICP(PORT_TC1))
>> +#define SDE_DDI_MASK_DG1 (SDE_DDI_HOTPLUG_ICP(PORT_D) | \
>> + SDE_DDI_HOTPLUG_ICP(PORT_C) | \
>> + SDE_DDI_HOTPLUG_ICP(PORT_B) | \
>> + SDE_DDI_HOTPLUG_ICP(PORT_A))
>>
>> #define SDEISR _MMIO(0xc4000)
>> #define SDEIMR _MMIO(0xc4004)
>> @@ -8367,6 +8371,10 @@ enum {
>> #define TGP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(PORT_TC6) | \
>> ICP_TC_HPD_ENABLE(PORT_TC5) | \
>> ICP_TC_HPD_ENABLE_MASK)
>> +#define DG1_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_D) | \
>> + SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_C) | \
>> + SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \
>> + SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A))
>>
>> #define _PCH_DPLL_A 0xc6014
>> #define _PCH_DPLL_B 0xc6018
>> --
>> 2.26.2
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 48+ messages in thread* Re: [Intel-gfx] [PATCH v2 20/32] drm/i915/dg1: add hpd interrupt handling
2020-06-22 20:43 ` Lucas De Marchi
@ 2020-06-22 20:54 ` Imre Deak
2020-06-22 21:59 ` Lucas De Marchi
0 siblings, 1 reply; 48+ messages in thread
From: Imre Deak @ 2020-06-22 20:54 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
On Mon, Jun 22, 2020 at 01:43:45PM -0700, Lucas De Marchi wrote:
> On Mon, Jun 22, 2020 at 09:35:09PM +0300, Imre Deak wrote:
> > On Wed, Jun 17, 2020 at 05:42:28PM -0700, Lucas De Marchi wrote:
> > > DG1 has one more combo phy port, no TC and all irq handling goes through
> > > SDE, like for MCC.
> > >
> > > Cc: Anshuman Gupta <anshuman.gupta@intel.com>
> > > Cc: José Roberto de Souza <jose.souza@intel.com>
> > > Cc: Imre Deak <imre.deak@intel.com>
> > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/i915_irq.c | 57 +++++++++++++++++++++++++++++----
> > > drivers/gpu/drm/i915/i915_reg.h | 8 +++++
> > > 2 files changed, 59 insertions(+), 6 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> > > index 48e1686df3416..3707f9231171f 100644
> > > --- a/drivers/gpu/drm/i915/i915_irq.c
> > > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > > @@ -167,6 +167,13 @@ static const u32 hpd_tgp[HPD_NUM_PINS] = {
> > > [HPD_PORT_I] = SDE_TC_HOTPLUG_ICP(PORT_TC6),
> > > };
> > >
> > > +static const u32 hpd_dg1_sde[HPD_NUM_PINS] = {
> > > + [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PHY_A),
> > > + [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PHY_B),
> > > + [HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(PHY_C),
> > > + [HPD_PORT_E] = SDE_DDI_HOTPLUG_ICP(PHY_D),
> >
> > The above 2 entries look incorrect. encoder->hpd_pin will be assigned
> > based on the encoder/port's PHY (see intel_hpd_pin_default()). On DG1
>
> Humn... it was not like that. It seems to have changed recently:
> 270810a73210 ("drm/i915/hotplug: Use phy to get the hpd_pin instead of the port (v5)")
>
> Thanks for spotting that.
Yea, but I think the correct change is to keep the hpd pin table above
as-is and make DG1 the same case as RKL + TGP in
intel_hpd_pin_default(). By changing the hpd pin table above would break
the long/short pulse detection.
>
> Lucas De Marchi
>
> > port D is connected to PHY C and port E is connected to PHY D. So the
> > above two pin definitions should be:
> >
> > [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(PHY_C),
> > [HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(PHY_D),
> >
> > > +};
> > > +
> > > static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
> > > {
> > > struct i915_hotplug *hpd = &dev_priv->hotplug;
> > > @@ -193,10 +200,13 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
> > > else
> > > hpd->hpd = hpd_ilk;
> > >
> > > - if (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv))
> > > + if ((INTEL_PCH_TYPE(dev_priv) < PCH_DG1) &&
> > > + (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv)))
> > > return;
> > >
> > > - if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv))
> > > + if (HAS_PCH_DG1(dev_priv))
> > > + hpd->pch_hpd = hpd_dg1_sde;
> > > + else if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv))
> > > hpd->pch_hpd = hpd_tgp;
> > > else if (HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv))
> > > hpd->pch_hpd = hpd_icp;
> > > @@ -1145,6 +1155,22 @@ static bool tgp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
> > > }
> > > }
> > >
> > > +static bool dg1_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
> > > +{
> > > + switch (pin) {
> > > + case HPD_PORT_A:
> > > + return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_A);
> > > + case HPD_PORT_B:
> > > + return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_B);
> > > + case HPD_PORT_D:
> > > + return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_C);
> > > + case HPD_PORT_E:
> > > + return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_D);
> > > + default:
> > > + return false;
> > > + }
> > > +}
> > > +
> > > static bool spt_port_hotplug2_long_detect(enum hpd_pin pin, u32 val)
> > > {
> > > switch (pin) {
> > > @@ -1893,13 +1919,20 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
> > > u32 ddi_hotplug_trigger, tc_hotplug_trigger;
> > > u32 pin_mask = 0, long_mask = 0;
> > > bool (*tc_port_hotplug_long_detect)(enum hpd_pin pin, u32 val);
> > > + bool (*ddi_port_hotplug_long_detect)(enum hpd_pin pin, u32 val);
> > >
> > > - if (HAS_PCH_TGP(dev_priv)) {
> > > + if (HAS_PCH_DG1(dev_priv)) {
> > > + ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_DG1;
> > > + ddi_port_hotplug_long_detect = dg1_ddi_port_hotplug_long_detect;
> > > + tc_hotplug_trigger = 0;
> > > + } else if (HAS_PCH_TGP(dev_priv)) {
> > > ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
> > > + ddi_port_hotplug_long_detect = icp_ddi_port_hotplug_long_detect;
> > > tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP;
> > > tc_port_hotplug_long_detect = tgp_tc_port_hotplug_long_detect;
> > > } else if (HAS_PCH_JSP(dev_priv)) {
> > > ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
> > > + ddi_port_hotplug_long_detect = icp_ddi_port_hotplug_long_detect;
> > > tc_hotplug_trigger = 0;
> > > } else if (HAS_PCH_MCC(dev_priv)) {
> > > ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
> > > @@ -1911,6 +1944,7 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
> > > INTEL_PCH_TYPE(dev_priv));
> > >
> > > ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
> > > + ddi_port_hotplug_long_detect = icp_ddi_port_hotplug_long_detect;
> > > tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
> > > tc_port_hotplug_long_detect = icp_tc_port_hotplug_long_detect;
> > > }
> > > @@ -1924,7 +1958,7 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
> > > intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
> > > ddi_hotplug_trigger, dig_hotplug_reg,
> > > dev_priv->hotplug.pch_hpd,
> > > - icp_ddi_port_hotplug_long_detect);
> > > + ddi_port_hotplug_long_detect);
> > > }
> > >
> > > if (tc_hotplug_trigger) {
> > > @@ -3147,6 +3181,13 @@ static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv)
> > > TGP_DDI_HPD_ENABLE_MASK, 0);
> > > }
> > >
> > > +static void dg1_hpd_irq_setup(struct drm_i915_private *dev_priv)
> > > +{
> > > + icp_hpd_irq_setup(dev_priv,
> > > + SDE_DDI_MASK_DG1, 0,
> > > + DG1_DDI_HPD_ENABLE_MASK, 0);
> > > +}
> > > +
> > > static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
> > > {
> > > u32 hotplug;
> > > @@ -3535,7 +3576,9 @@ static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> > > gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
> > > I915_WRITE(SDEIMR, ~mask);
> > >
> > > - if (HAS_PCH_TGP(dev_priv))
> > > + if (HAS_PCH_DG1(dev_priv))
> > > + icp_hpd_detection_setup(dev_priv, DG1_DDI_HPD_ENABLE_MASK, 0);
> > > + else if (HAS_PCH_TGP(dev_priv))
> > > icp_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK,
> > > TGP_TC_HPD_ENABLE_MASK);
> > > else if (HAS_PCH_JSP(dev_priv))
> > > @@ -4051,7 +4094,9 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
> > > if (I915_HAS_HOTPLUG(dev_priv))
> > > dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
> > > } else {
> > > - if (HAS_PCH_JSP(dev_priv))
> > > + if (HAS_PCH_DG1(dev_priv))
> > > + dev_priv->display.hpd_irq_setup = dg1_hpd_irq_setup;
> > > + else if (HAS_PCH_JSP(dev_priv))
> > > dev_priv->display.hpd_irq_setup = jsp_hpd_irq_setup;
> > > else if (HAS_PCH_MCC(dev_priv))
> > > dev_priv->display.hpd_irq_setup = mcc_hpd_irq_setup;
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > index 6649aeca25d72..13a989f5e8dd3 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -8168,6 +8168,10 @@ enum {
> > > SDE_TC_HOTPLUG_ICP(PORT_TC3) | \
> > > SDE_TC_HOTPLUG_ICP(PORT_TC2) | \
> > > SDE_TC_HOTPLUG_ICP(PORT_TC1))
> > > +#define SDE_DDI_MASK_DG1 (SDE_DDI_HOTPLUG_ICP(PORT_D) | \
> > > + SDE_DDI_HOTPLUG_ICP(PORT_C) | \
> > > + SDE_DDI_HOTPLUG_ICP(PORT_B) | \
> > > + SDE_DDI_HOTPLUG_ICP(PORT_A))
> > >
> > > #define SDEISR _MMIO(0xc4000)
> > > #define SDEIMR _MMIO(0xc4004)
> > > @@ -8367,6 +8371,10 @@ enum {
> > > #define TGP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(PORT_TC6) | \
> > > ICP_TC_HPD_ENABLE(PORT_TC5) | \
> > > ICP_TC_HPD_ENABLE_MASK)
> > > +#define DG1_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_D) | \
> > > + SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_C) | \
> > > + SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \
> > > + SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A))
> > >
> > > #define _PCH_DPLL_A 0xc6014
> > > #define _PCH_DPLL_B 0xc6018
> > > --
> > > 2.26.2
> > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 48+ messages in thread* Re: [Intel-gfx] [PATCH v2 20/32] drm/i915/dg1: add hpd interrupt handling
2020-06-22 20:54 ` Imre Deak
@ 2020-06-22 21:59 ` Lucas De Marchi
0 siblings, 0 replies; 48+ messages in thread
From: Lucas De Marchi @ 2020-06-22 21:59 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Mon, Jun 22, 2020 at 11:54:11PM +0300, Imre Deak wrote:
>On Mon, Jun 22, 2020 at 01:43:45PM -0700, Lucas De Marchi wrote:
>> On Mon, Jun 22, 2020 at 09:35:09PM +0300, Imre Deak wrote:
>> > On Wed, Jun 17, 2020 at 05:42:28PM -0700, Lucas De Marchi wrote:
>> > > DG1 has one more combo phy port, no TC and all irq handling goes through
>> > > SDE, like for MCC.
>> > >
>> > > Cc: Anshuman Gupta <anshuman.gupta@intel.com>
>> > > Cc: José Roberto de Souza <jose.souza@intel.com>
>> > > Cc: Imre Deak <imre.deak@intel.com>
>> > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> > > ---
>> > > drivers/gpu/drm/i915/i915_irq.c | 57 +++++++++++++++++++++++++++++----
>> > > drivers/gpu/drm/i915/i915_reg.h | 8 +++++
>> > > 2 files changed, 59 insertions(+), 6 deletions(-)
>> > >
>> > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>> > > index 48e1686df3416..3707f9231171f 100644
>> > > --- a/drivers/gpu/drm/i915/i915_irq.c
>> > > +++ b/drivers/gpu/drm/i915/i915_irq.c
>> > > @@ -167,6 +167,13 @@ static const u32 hpd_tgp[HPD_NUM_PINS] = {
>> > > [HPD_PORT_I] = SDE_TC_HOTPLUG_ICP(PORT_TC6),
>> > > };
>> > >
>> > > +static const u32 hpd_dg1_sde[HPD_NUM_PINS] = {
>> > > + [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PHY_A),
>> > > + [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PHY_B),
>> > > + [HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(PHY_C),
>> > > + [HPD_PORT_E] = SDE_DDI_HOTPLUG_ICP(PHY_D),
>> >
>> > The above 2 entries look incorrect. encoder->hpd_pin will be assigned
>> > based on the encoder/port's PHY (see intel_hpd_pin_default()). On DG1
>>
>> Humn... it was not like that. It seems to have changed recently:
>> 270810a73210 ("drm/i915/hotplug: Use phy to get the hpd_pin instead of the port (v5)")
>>
>> Thanks for spotting that.
>
>Yea, but I think the correct change is to keep the hpd pin table above
>as-is and make DG1 the same case as RKL + TGP in
>intel_hpd_pin_default(). By changing the hpd pin table above would break
>the long/short pulse detection.
I think long term we should stop doing these conversions back and forth
from port <-> phy. I will se if I can revive an old series I had to
accomplish that.
Lucas D Marchi
>
>>
>> Lucas De Marchi
>>
>> > port D is connected to PHY C and port E is connected to PHY D. So the
>> > above two pin definitions should be:
>> >
>> > [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(PHY_C),
>> > [HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(PHY_D),
>> >
>> > > +};
>> > > +
>> > > static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
>> > > {
>> > > struct i915_hotplug *hpd = &dev_priv->hotplug;
>> > > @@ -193,10 +200,13 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
>> > > else
>> > > hpd->hpd = hpd_ilk;
>> > >
>> > > - if (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv))
>> > > + if ((INTEL_PCH_TYPE(dev_priv) < PCH_DG1) &&
>> > > + (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv)))
>> > > return;
>> > >
>> > > - if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv))
>> > > + if (HAS_PCH_DG1(dev_priv))
>> > > + hpd->pch_hpd = hpd_dg1_sde;
>> > > + else if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv))
>> > > hpd->pch_hpd = hpd_tgp;
>> > > else if (HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv))
>> > > hpd->pch_hpd = hpd_icp;
>> > > @@ -1145,6 +1155,22 @@ static bool tgp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
>> > > }
>> > > }
>> > >
>> > > +static bool dg1_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
>> > > +{
>> > > + switch (pin) {
>> > > + case HPD_PORT_A:
>> > > + return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_A);
>> > > + case HPD_PORT_B:
>> > > + return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_B);
>> > > + case HPD_PORT_D:
>> > > + return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_C);
>> > > + case HPD_PORT_E:
>> > > + return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_D);
>> > > + default:
>> > > + return false;
>> > > + }
>> > > +}
>> > > +
>> > > static bool spt_port_hotplug2_long_detect(enum hpd_pin pin, u32 val)
>> > > {
>> > > switch (pin) {
>> > > @@ -1893,13 +1919,20 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
>> > > u32 ddi_hotplug_trigger, tc_hotplug_trigger;
>> > > u32 pin_mask = 0, long_mask = 0;
>> > > bool (*tc_port_hotplug_long_detect)(enum hpd_pin pin, u32 val);
>> > > + bool (*ddi_port_hotplug_long_detect)(enum hpd_pin pin, u32 val);
>> > >
>> > > - if (HAS_PCH_TGP(dev_priv)) {
>> > > + if (HAS_PCH_DG1(dev_priv)) {
>> > > + ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_DG1;
>> > > + ddi_port_hotplug_long_detect = dg1_ddi_port_hotplug_long_detect;
>> > > + tc_hotplug_trigger = 0;
>> > > + } else if (HAS_PCH_TGP(dev_priv)) {
>> > > ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
>> > > + ddi_port_hotplug_long_detect = icp_ddi_port_hotplug_long_detect;
>> > > tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP;
>> > > tc_port_hotplug_long_detect = tgp_tc_port_hotplug_long_detect;
>> > > } else if (HAS_PCH_JSP(dev_priv)) {
>> > > ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
>> > > + ddi_port_hotplug_long_detect = icp_ddi_port_hotplug_long_detect;
>> > > tc_hotplug_trigger = 0;
>> > > } else if (HAS_PCH_MCC(dev_priv)) {
>> > > ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
>> > > @@ -1911,6 +1944,7 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
>> > > INTEL_PCH_TYPE(dev_priv));
>> > >
>> > > ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
>> > > + ddi_port_hotplug_long_detect = icp_ddi_port_hotplug_long_detect;
>> > > tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
>> > > tc_port_hotplug_long_detect = icp_tc_port_hotplug_long_detect;
>> > > }
>> > > @@ -1924,7 +1958,7 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
>> > > intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
>> > > ddi_hotplug_trigger, dig_hotplug_reg,
>> > > dev_priv->hotplug.pch_hpd,
>> > > - icp_ddi_port_hotplug_long_detect);
>> > > + ddi_port_hotplug_long_detect);
>> > > }
>> > >
>> > > if (tc_hotplug_trigger) {
>> > > @@ -3147,6 +3181,13 @@ static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv)
>> > > TGP_DDI_HPD_ENABLE_MASK, 0);
>> > > }
>> > >
>> > > +static void dg1_hpd_irq_setup(struct drm_i915_private *dev_priv)
>> > > +{
>> > > + icp_hpd_irq_setup(dev_priv,
>> > > + SDE_DDI_MASK_DG1, 0,
>> > > + DG1_DDI_HPD_ENABLE_MASK, 0);
>> > > +}
>> > > +
>> > > static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
>> > > {
>> > > u32 hotplug;
>> > > @@ -3535,7 +3576,9 @@ static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
>> > > gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
>> > > I915_WRITE(SDEIMR, ~mask);
>> > >
>> > > - if (HAS_PCH_TGP(dev_priv))
>> > > + if (HAS_PCH_DG1(dev_priv))
>> > > + icp_hpd_detection_setup(dev_priv, DG1_DDI_HPD_ENABLE_MASK, 0);
>> > > + else if (HAS_PCH_TGP(dev_priv))
>> > > icp_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK,
>> > > TGP_TC_HPD_ENABLE_MASK);
>> > > else if (HAS_PCH_JSP(dev_priv))
>> > > @@ -4051,7 +4094,9 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
>> > > if (I915_HAS_HOTPLUG(dev_priv))
>> > > dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
>> > > } else {
>> > > - if (HAS_PCH_JSP(dev_priv))
>> > > + if (HAS_PCH_DG1(dev_priv))
>> > > + dev_priv->display.hpd_irq_setup = dg1_hpd_irq_setup;
>> > > + else if (HAS_PCH_JSP(dev_priv))
>> > > dev_priv->display.hpd_irq_setup = jsp_hpd_irq_setup;
>> > > else if (HAS_PCH_MCC(dev_priv))
>> > > dev_priv->display.hpd_irq_setup = mcc_hpd_irq_setup;
>> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> > > index 6649aeca25d72..13a989f5e8dd3 100644
>> > > --- a/drivers/gpu/drm/i915/i915_reg.h
>> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
>> > > @@ -8168,6 +8168,10 @@ enum {
>> > > SDE_TC_HOTPLUG_ICP(PORT_TC3) | \
>> > > SDE_TC_HOTPLUG_ICP(PORT_TC2) | \
>> > > SDE_TC_HOTPLUG_ICP(PORT_TC1))
>> > > +#define SDE_DDI_MASK_DG1 (SDE_DDI_HOTPLUG_ICP(PORT_D) | \
>> > > + SDE_DDI_HOTPLUG_ICP(PORT_C) | \
>> > > + SDE_DDI_HOTPLUG_ICP(PORT_B) | \
>> > > + SDE_DDI_HOTPLUG_ICP(PORT_A))
>> > >
>> > > #define SDEISR _MMIO(0xc4000)
>> > > #define SDEIMR _MMIO(0xc4004)
>> > > @@ -8367,6 +8371,10 @@ enum {
>> > > #define TGP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(PORT_TC6) | \
>> > > ICP_TC_HPD_ENABLE(PORT_TC5) | \
>> > > ICP_TC_HPD_ENABLE_MASK)
>> > > +#define DG1_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_D) | \
>> > > + SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_C) | \
>> > > + SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \
>> > > + SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A))
>> > >
>> > > #define _PCH_DPLL_A 0xc6014
>> > > #define _PCH_DPLL_B 0xc6018
>> > > --
>> > > 2.26.2
>> > >
>> > > _______________________________________________
>> > > Intel-gfx mailing list
>> > > Intel-gfx@lists.freedesktop.org
>> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 48+ messages in thread
* [Intel-gfx] [PATCH v2 21/32] drm/i915/dg1: invert HPD pins
2020-06-18 0:42 [Intel-gfx] [PATCH v2 00/32] Introduce DG1 Lucas De Marchi
` (19 preceding siblings ...)
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 20/32] drm/i915/dg1: add hpd interrupt handling Lucas De Marchi
@ 2020-06-18 0:42 ` Lucas De Marchi
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 22/32] drm/i915/dg1: gmbus pin mapping Lucas De Marchi
` (13 subsequent siblings)
34 siblings, 0 replies; 48+ messages in thread
From: Lucas De Marchi @ 2020-06-18 0:42 UTC (permalink / raw)
To: intel-gfx
From: Clinton A Taylor <clinton.a.taylor@intel.com>
HPD pins are inverted for DG1 platform.
Bspec: 49956
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Clinton A Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 4 ++++
drivers/gpu/drm/i915/i915_reg.h | 4 ++++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 3707f9231171f..4fd667bc88c2e 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3183,6 +3183,10 @@ static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv)
static void dg1_hpd_irq_setup(struct drm_i915_private *dev_priv)
{
+ intel_de_rmw(dev_priv, SOUTH_CHICKEN1, 0,
+ INVERT_DDIA_HPD | INVERT_DDIB_HPD |
+ INVERT_DDIC_HPD | INVERT_DDID_HPD);
+
icp_hpd_irq_setup(dev_priv,
SDE_DDI_MASK_DG1, 0,
DG1_DDI_HPD_ENABLE_MASK, 0);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 13a989f5e8dd3..3f9a10dd5be27 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8635,6 +8635,10 @@ enum {
#define SOUTH_CHICKEN1 _MMIO(0xc2000)
#define FDIA_PHASE_SYNC_SHIFT_OVR 19
#define FDIA_PHASE_SYNC_SHIFT_EN 18
+#define INVERT_DDID_HPD (1 << 18)
+#define INVERT_DDIC_HPD (1 << 17)
+#define INVERT_DDIB_HPD (1 << 16)
+#define INVERT_DDIA_HPD (1 << 15)
#define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
#define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
#define FDI_BC_BIFURCATION_SELECT (1 << 12)
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 48+ messages in thread* [Intel-gfx] [PATCH v2 22/32] drm/i915/dg1: gmbus pin mapping
2020-06-18 0:42 [Intel-gfx] [PATCH v2 00/32] Introduce DG1 Lucas De Marchi
` (20 preceding siblings ...)
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 21/32] drm/i915/dg1: invert HPD pins Lucas De Marchi
@ 2020-06-18 0:42 ` Lucas De Marchi
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 23/32] drm/i915/dg1: Enable first 2 ports for DG1 Lucas De Marchi
` (12 subsequent siblings)
34 siblings, 0 replies; 48+ messages in thread
From: Lucas De Marchi @ 2020-06-18 0:42 UTC (permalink / raw)
To: intel-gfx
Add tables to map the GMBUS pin pairs to GPIO registers and port to DDC.
The values for VBT are currently not in BSpec. If we assume the latest
is ICL (like we did for TGL), then the mapping is wrong per VBT we can
currently parse.
From spec we have registers GPIO_CTL[1-4], so we should not do the 4->9
mapping as in ICL/TGL.
BSpec: 49311, 49945, 20124
Cc: Aditya Swarup <aditya.swarup@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_bios.c | 4 +++-
drivers/gpu/drm/i915/display/intel_gmbus.c | 15 +++++++++++++--
drivers/gpu/drm/i915/display/intel_hdmi.c | 9 ++++++++-
3 files changed, 24 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index c974c716f8593..308160f015186 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1599,7 +1599,9 @@ static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
const u8 *ddc_pin_map;
int n_entries;
- if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) {
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) {
+ return vbt_pin;
+ } else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) {
ddc_pin_map = icp_ddc_pin_map;
n_entries = ARRAY_SIZE(icp_ddc_pin_map);
} else if (HAS_PCH_CNP(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
index a8d119b6b45c8..528e48658340c 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -90,11 +90,20 @@ static const struct gmbus_pin gmbus_pins_icp[] = {
[GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO },
};
+static const struct gmbus_pin gmbus_pins_dg1[] = {
+ [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
+ [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
+ [GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
+ [GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
+};
+
/* pin is expected to be valid */
static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
unsigned int pin)
{
- if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+ return &gmbus_pins_dg1[pin];
+ else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
return &gmbus_pins_icp[pin];
else if (HAS_PCH_CNP(dev_priv))
return &gmbus_pins_cnp[pin];
@@ -113,7 +122,9 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
{
unsigned int size;
- if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+ size = ARRAY_SIZE(gmbus_pins_dg1);
+ else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
size = ARRAY_SIZE(gmbus_pins_icp);
else if (HAS_PCH_CNP(dev_priv))
size = ARRAY_SIZE(gmbus_pins_cnp);
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index a31a98d268823..34f133e2a90db 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -3100,6 +3100,11 @@ static u8 rkl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
return GMBUS_PIN_1_BXT + phy;
}
+static u8 dg1_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
+{
+ return intel_port_to_phy(dev_priv, port) + 1;
+}
+
static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
enum port port)
{
@@ -3137,7 +3142,9 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder)
return ddc_pin;
}
- if (IS_ROCKETLAKE(dev_priv))
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+ ddc_pin = dg1_port_to_ddc_pin(dev_priv, port);
+ else if (IS_ROCKETLAKE(dev_priv))
ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
else if (HAS_PCH_MCC(dev_priv))
ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
--
2.26.2
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^ permalink raw reply related [flat|nested] 48+ messages in thread* [Intel-gfx] [PATCH v2 23/32] drm/i915/dg1: Enable first 2 ports for DG1
2020-06-18 0:42 [Intel-gfx] [PATCH v2 00/32] Introduce DG1 Lucas De Marchi
` (21 preceding siblings ...)
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 22/32] drm/i915/dg1: gmbus pin mapping Lucas De Marchi
@ 2020-06-18 0:42 ` Lucas De Marchi
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 24/32] drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D Lucas De Marchi
` (11 subsequent siblings)
34 siblings, 0 replies; 48+ messages in thread
From: Lucas De Marchi @ 2020-06-18 0:42 UTC (permalink / raw)
To: intel-gfx
From: Aditya Swarup <aditya.swarup@intel.com>
Enable PORTS A and B for DG1 initially, the other ports still need more
plumbing code in order to be enabled.
Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f16512eddc587..58c08ec0298a0 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7219,6 +7219,9 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
{
if (phy == PHY_NONE)
return false;
+ else if (IS_DG1(dev_priv))
+ /* FIXME: Enable only two ports for now */
+ return phy <= PHY_B;
else if (IS_ROCKETLAKE(dev_priv))
return phy <= PHY_D;
else if (IS_ELKHARTLAKE(dev_priv))
@@ -7231,7 +7234,7 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
{
- if (IS_ROCKETLAKE(dev_priv))
+ if (IS_ROCKETLAKE(dev_priv) || IS_DG1(dev_priv))
return false;
else if (INTEL_GEN(dev_priv) >= 12)
return phy >= PHY_D && phy <= PHY_I;
@@ -16832,7 +16835,11 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv))
return;
- if (IS_ROCKETLAKE(dev_priv)) {
+ if (IS_DG1(dev_priv)) {
+ /* FIXME: Enable only two ports for now */
+ intel_ddi_init(dev_priv, PORT_A);
+ intel_ddi_init(dev_priv, PORT_B);
+ } else if (IS_ROCKETLAKE(dev_priv)) {
/*
* If HTI (aka HDPORT) is enabled at boot, it may have taken
* over some of the PHYs and made them unavailable to the
--
2.26.2
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^ permalink raw reply related [flat|nested] 48+ messages in thread* [Intel-gfx] [PATCH v2 24/32] drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D
2020-06-18 0:42 [Intel-gfx] [PATCH v2 00/32] Introduce DG1 Lucas De Marchi
` (22 preceding siblings ...)
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 23/32] drm/i915/dg1: Enable first 2 ports for DG1 Lucas De Marchi
@ 2020-06-18 0:42 ` Lucas De Marchi
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 25/32] drm/i915/dg1: Update comp master/slave relationships for PHYs Lucas De Marchi
` (10 subsequent siblings)
34 siblings, 0 replies; 48+ messages in thread
From: Lucas De Marchi @ 2020-06-18 0:42 UTC (permalink / raw)
To: intel-gfx
From: Matt Roper <matthew.d.roper@intel.com>
The only bit we use in PHY_MISC is DE_IO_COMP_PWR_DOWN, and the bspec
details for that bit tell us that it need only be set for PHY-A and
PHY-B. It also turns out that there isn't even an instance of the
PHY_MISC register for PHY-D on this platform. Let's extend the EHL/RKL
logic that conditionally skips PHY_MISC usage to DG1 as well.
Bspec: 50107
Cc: Aditya Swarup <aditya.swarup@intel.com>
Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_combo_phy.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index d5d95e2746c2c..336d18f3d1c52 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -189,7 +189,8 @@ static bool has_phy_misc(struct drm_i915_private *i915, enum phy phy)
* other combo PHY's.
*/
if (IS_ELKHARTLAKE(i915) ||
- IS_ROCKETLAKE(i915))
+ IS_ROCKETLAKE(i915) ||
+ IS_DG1(i915))
return phy < PHY_C;
return true;
--
2.26.2
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^ permalink raw reply related [flat|nested] 48+ messages in thread* [Intel-gfx] [PATCH v2 25/32] drm/i915/dg1: Update comp master/slave relationships for PHYs
2020-06-18 0:42 [Intel-gfx] [PATCH v2 00/32] Introduce DG1 Lucas De Marchi
` (23 preceding siblings ...)
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 24/32] drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D Lucas De Marchi
@ 2020-06-18 0:42 ` Lucas De Marchi
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 26/32] drm/i915/dg1: Update voltage swing tables for DP Lucas De Marchi
` (9 subsequent siblings)
34 siblings, 0 replies; 48+ messages in thread
From: Lucas De Marchi @ 2020-06-18 0:42 UTC (permalink / raw)
To: intel-gfx
From: Matt Roper <matthew.d.roper@intel.com>
As with RKL, DG1's PHY C acts as a comp master for PHY D.
Bspec: 49291
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_combo_phy.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index 336d18f3d1c52..ba6a21c5ef15d 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -243,14 +243,14 @@ static bool phy_is_master(struct drm_i915_private *dev_priv, enum phy phy)
*
* ICL,TGL:
* A(master) -> B(slave), C(slave)
- * RKL:
+ * RKL,DG1:
* A(master) -> B(slave)
* C(master) -> D(slave)
*
* We must set the IREFGEN bit for any PHY acting as a master
* to another PHY.
*/
- if (IS_ROCKETLAKE(dev_priv) && phy == PHY_C)
+ if ((IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) && phy == PHY_C)
return true;
return phy == PHY_A;
--
2.26.2
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^ permalink raw reply related [flat|nested] 48+ messages in thread* [Intel-gfx] [PATCH v2 26/32] drm/i915/dg1: Update voltage swing tables for DP
2020-06-18 0:42 [Intel-gfx] [PATCH v2 00/32] Introduce DG1 Lucas De Marchi
` (24 preceding siblings ...)
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 25/32] drm/i915/dg1: Update comp master/slave relationships for PHYs Lucas De Marchi
@ 2020-06-18 0:42 ` Lucas De Marchi
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 27/32] drm/i915/dg1: provide port/phy mapping for vbt Lucas De Marchi
` (8 subsequent siblings)
34 siblings, 0 replies; 48+ messages in thread
From: Lucas De Marchi @ 2020-06-18 0:42 UTC (permalink / raw)
To: intel-gfx
From: Matt Roper <matthew.d.roper@intel.com>
DG1's vswing tables are the same for eDP and HDMI but have slight
differences from ICL/TGL for DP.
Bspec: 49291
Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 34 ++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 8790f221dc77c..f500c9677b278 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -582,6 +582,34 @@ static const struct cnl_ddi_buf_trans ehl_combo_phy_ddi_translations_dp[] = {
{ 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
};
+static const struct cnl_ddi_buf_trans dg1_combo_phy_ddi_translations_dp_hbr[] = {
+ /* NT mV Trans mV db */
+ { 0xA, 0x32, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
+ { 0xA, 0x48, 0x35, 0x00, 0x0A }, /* 350 500 3.1 */
+ { 0xC, 0x63, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
+ { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 350 900 8.2 */
+ { 0xA, 0x43, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
+ { 0xC, 0x60, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
+ { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
+ { 0xC, 0x60, 0x3F, 0x00, 0x00 }, /* 650 700 0.6 */
+ { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 600 900 3.5 */
+ { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
+};
+
+static const struct cnl_ddi_buf_trans dg1_combo_phy_ddi_translations_dp_hbr2[] = {
+ /* NT mV Trans mV db */
+ { 0xA, 0x32, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
+ { 0xA, 0x48, 0x35, 0x00, 0x0A }, /* 350 500 3.1 */
+ { 0xC, 0x63, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
+ { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 350 900 8.2 */
+ { 0xA, 0x43, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
+ { 0xC, 0x60, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
+ { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
+ { 0xC, 0x58, 0x3F, 0x00, 0x00 }, /* 650 700 0.6 */
+ { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
+ { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
+};
+
struct icl_mg_phy_ddi_buf_trans {
u32 cri_txdeemph_override_11_6;
u32 cri_txdeemph_override_5_0;
@@ -993,6 +1021,12 @@ icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
} else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
return icl_combo_phy_ddi_translations_edp_hbr2;
+ } else if (IS_DG1(dev_priv) && rate > 270000) {
+ *n_entries = ARRAY_SIZE(dg1_combo_phy_ddi_translations_dp_hbr2);
+ return dg1_combo_phy_ddi_translations_dp_hbr2;
+ } else if (IS_DG1(dev_priv)) {
+ *n_entries = ARRAY_SIZE(dg1_combo_phy_ddi_translations_dp_hbr);
+ return dg1_combo_phy_ddi_translations_dp_hbr;
}
*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
--
2.26.2
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^ permalink raw reply related [flat|nested] 48+ messages in thread* [Intel-gfx] [PATCH v2 27/32] drm/i915/dg1: provide port/phy mapping for vbt
2020-06-18 0:42 [Intel-gfx] [PATCH v2 00/32] Introduce DG1 Lucas De Marchi
` (25 preceding siblings ...)
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 26/32] drm/i915/dg1: Update voltage swing tables for DP Lucas De Marchi
@ 2020-06-18 0:42 ` Lucas De Marchi
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 28/32] drm/i915/dg1: map/unmap pll clocks Lucas De Marchi
` (7 subsequent siblings)
34 siblings, 0 replies; 48+ messages in thread
From: Lucas De Marchi @ 2020-06-18 0:42 UTC (permalink / raw)
To: intel-gfx
From: Matt Roper <matthew.d.roper@intel.com>
As with RKL, DG1's VBT outputs are indexed according to PHY rather than
DDI.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_bios.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 308160f015186..064c74f70a58b 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1670,7 +1670,7 @@ static enum port dvo_port_to_port(struct drm_i915_private *dev_priv,
[PORT_E] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
};
- if (IS_ROCKETLAKE(dev_priv))
+ if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
return __dvo_port_to_port(ARRAY_SIZE(rkl_port_mapping),
ARRAY_SIZE(rkl_port_mapping[0]),
rkl_port_mapping,
@@ -2635,10 +2635,12 @@ enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv,
aux_ch = AUX_CH_B;
break;
case DP_AUX_C:
- aux_ch = IS_ROCKETLAKE(dev_priv) ? AUX_CH_D : AUX_CH_C;
+ aux_ch = (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) ?
+ AUX_CH_D : AUX_CH_C;
break;
case DP_AUX_D:
- aux_ch = IS_ROCKETLAKE(dev_priv) ? AUX_CH_E : AUX_CH_D;
+ aux_ch = (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) ?
+ AUX_CH_E : AUX_CH_D;
break;
case DP_AUX_E:
aux_ch = AUX_CH_E;
--
2.26.2
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^ permalink raw reply related [flat|nested] 48+ messages in thread* [Intel-gfx] [PATCH v2 28/32] drm/i915/dg1: map/unmap pll clocks
2020-06-18 0:42 [Intel-gfx] [PATCH v2 00/32] Introduce DG1 Lucas De Marchi
` (26 preceding siblings ...)
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 27/32] drm/i915/dg1: provide port/phy mapping for vbt Lucas De Marchi
@ 2020-06-18 0:42 ` Lucas De Marchi
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 29/32] drm/i915/dg1: enable PORT C/D aka D/E Lucas De Marchi
` (6 subsequent siblings)
34 siblings, 0 replies; 48+ messages in thread
From: Lucas De Marchi @ 2020-06-18 0:42 UTC (permalink / raw)
To: intel-gfx
DG1 uses 2 registers for the ddi clock mapping, with PHY A and B using
DPCLKA_CFGCR0 and PHY C and D using DPCLKA1_CFGCR0. Hide this behind a
single macro that chooses the correct register according to the phy
being accessed, use the correct bitfields for each pll/phy and implement
separate functions for DG1 since it doesn't share much with ICL/TGL
anymore.
The previous values were correct for PHY A and B since they were using
the same register as before and the bitfields were matching.
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 92 +++++++++++++++++++-
drivers/gpu/drm/i915/display/intel_display.c | 25 +++++-
drivers/gpu/drm/i915/i915_reg.h | 15 ++++
3 files changed, 128 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index f500c9677b278..85052328a59a2 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2818,6 +2818,38 @@ static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
return 0;
}
+static void dg1_map_plls_to_ports(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+ enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+ u32 val;
+
+ /*
+ * If we fail this, something went very wrong: first 2 PLLs should be
+ * used by first 2 phys and last 2 PLLs by last phys
+ */
+ if (WARN_ON((pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) ||
+ (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C)))
+ return;
+
+ mutex_lock(&dev_priv->dpll.lock);
+
+ val = intel_de_read(dev_priv, DG1_DPCLKA_CFGCR0(phy));
+ WARN_ON((val & DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)) == 0);
+
+ val &= ~DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+ val |= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
+ intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val);
+ intel_de_posting_read(dev_priv, DG1_DPCLKA_CFGCR0(phy));
+
+ val &= ~DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
+ intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val);
+
+ mutex_unlock(&dev_priv->dpll.lock);
+}
+
static void icl_map_plls_to_ports(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
@@ -2865,6 +2897,19 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder,
mutex_unlock(&dev_priv->dpll.lock);
}
+static void dg1_unmap_plls_to_ports(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+
+ mutex_lock(&dev_priv->dpll.lock);
+
+ intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy), 0,
+ DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
+
+ mutex_unlock(&dev_priv->dpll.lock);
+}
+
static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -2880,6 +2925,40 @@ static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
mutex_unlock(&dev_priv->dpll.lock);
}
+static void dg1_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
+ u32 port_mask, bool ddi_clk_needed)
+{
+ enum port port;
+ u32 val;
+
+ for_each_port_masked(port, port_mask) {
+ enum phy phy = intel_port_to_phy(dev_priv, port);
+ bool ddi_clk_off;
+
+ val = intel_de_read(dev_priv, DG1_DPCLKA_CFGCR0(phy));
+ ddi_clk_off = val & DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
+
+ if (ddi_clk_needed == !ddi_clk_off)
+ continue;
+
+ /*
+ * Punt on the case now where clock is gated, but it would
+ * be needed by the port. Something else is really broken then.
+ */
+ if (ddi_clk_needed) {
+ WARN(1, "ddi_clk_needed=%u ddi_clk_off=%u phy=%u\n",
+ ddi_clk_needed, ddi_clk_off, phy);
+ continue;
+ }
+
+ DRM_NOTE("PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
+ phy_name(phy));
+
+ val |= DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
+ intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val);
+ }
+}
+
static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
u32 port_mask, bool ddi_clk_needed)
{
@@ -2962,7 +3041,10 @@ void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
ddi_clk_needed = false;
}
- icl_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed);
+ if (IS_DG1(dev_priv))
+ dg1_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed);
+ else
+ icl_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed);
}
static void intel_ddi_clk_select(struct intel_encoder *encoder,
@@ -3488,7 +3570,9 @@ static void intel_ddi_pre_enable(struct intel_atomic_state *state,
drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder);
- if (INTEL_GEN(dev_priv) >= 11)
+ if (IS_DG1(dev_priv))
+ dg1_map_plls_to_ports(encoder, crtc_state);
+ else if (INTEL_GEN(dev_priv) >= 11)
icl_map_plls_to_ports(encoder, crtc_state);
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
@@ -3674,7 +3758,9 @@ static void intel_ddi_post_disable(struct intel_atomic_state *state,
intel_ddi_post_disable_dp(state, encoder, old_crtc_state,
old_conn_state);
- if (INTEL_GEN(dev_priv) >= 11)
+ if (IS_DG1(dev_priv))
+ dg1_unmap_plls_to_ports(encoder);
+ else if (INTEL_GEN(dev_priv) >= 11)
icl_unmap_plls_to_ports(encoder);
if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 58c08ec0298a0..4b5d6c7c5782d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -10765,6 +10765,27 @@ static int hsw_crtc_compute_clock(struct intel_crtc *crtc,
return 0;
}
+static void dg1_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
+ struct intel_crtc_state *pipe_config)
+{
+ enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT;
+ enum phy phy = intel_port_to_phy(dev_priv, port);
+ enum intel_dpll_id id;
+ u32 val;
+
+ val = intel_de_read(dev_priv, DG1_DPCLKA_CFGCR0(phy))
+ & DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+ id = DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_VAL_TO_ID(val, phy);
+
+ if (WARN_ON(id > DPLL_ID_DG1_DPLL3))
+ return;
+
+ pipe_config->icl_port_dplls[port_dpll_id].pll =
+ intel_get_shared_dpll_by_id(dev_priv, id);
+
+ icl_set_active_port_dpll(pipe_config, port_dpll_id);
+}
+
static void cnl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
struct intel_crtc_state *pipe_config)
{
@@ -11073,7 +11094,9 @@ static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
port = TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
}
- if (INTEL_GEN(dev_priv) >= 11)
+ if (IS_DG1(dev_priv))
+ dg1_get_ddi_pll(dev_priv, port, pipe_config);
+ else if (INTEL_GEN(dev_priv) >= 11)
icl_get_ddi_pll(dev_priv, port, pipe_config);
else if (IS_CANNONLAKE(dev_priv))
cnl_get_ddi_pll(dev_priv, port, pipe_config);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3f9a10dd5be27..34ed419283a70 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -230,12 +230,14 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define _TRANS(tran, a, b) _PICK_EVEN(tran, a, b)
#define _PORT(port, a, b) _PICK_EVEN(port, a, b)
#define _PLL(pll, a, b) _PICK_EVEN(pll, a, b)
+#define _PHY(phy, a, b) _PICK_EVEN(phy, a, b)
#define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b))
#define _MMIO_PLANE(plane, a, b) _MMIO(_PLANE(plane, a, b))
#define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b))
#define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b))
#define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b))
+#define _MMIO_PHY(phy, a, b) _MMIO(_PHY(phy, a, b))
#define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__)
@@ -10229,6 +10231,7 @@ enum skl_power_gate {
#define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
#define DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port) ((pll) << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
+/* ICL Clocks */
#define ICL_DPCLKA_CFGCR0 _MMIO(0x164280)
#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24))
#define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10)
@@ -10244,6 +10247,18 @@ enum skl_power_gate {
#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) \
((pll) << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
+/* DG1 Clocks */
+#define _DG1_DPCLKA_CFGCR0 0x164280
+#define _DG1_DPCLKA1_CFGCR0 0x16C280
+#define DG1_DPCLKA_CFGCR0(phy) _MMIO_PHY((phy) / 2, \
+ _DG1_DPCLKA_CFGCR0, \
+ _DG1_DPCLKA1_CFGCR0)
+#define DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << (10 + ((phy) % 2)))
+#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (0x3 << (((phy) % 2) * 2))
+#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) (((pll) % 2) << (((phy) % 2)) * 2)
+#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_VAL_TO_ID(val, phy) \
+ ((((val) & DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy)) >> ((phy % 2) * 2)) + (2 * (phy / 2)))
+
/* CNL PLL */
#define DPLL0_ENABLE 0x46010
#define DPLL1_ENABLE 0x46014
--
2.26.2
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^ permalink raw reply related [flat|nested] 48+ messages in thread* [Intel-gfx] [PATCH v2 29/32] drm/i915/dg1: enable PORT C/D aka D/E
2020-06-18 0:42 [Intel-gfx] [PATCH v2 00/32] Introduce DG1 Lucas De Marchi
` (27 preceding siblings ...)
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 28/32] drm/i915/dg1: map/unmap pll clocks Lucas De Marchi
@ 2020-06-18 0:42 ` Lucas De Marchi
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 30/32] drm/i915/dg1: Load DMC Lucas De Marchi
` (5 subsequent siblings)
34 siblings, 0 replies; 48+ messages in thread
From: Lucas De Marchi @ 2020-06-18 0:42 UTC (permalink / raw)
To: intel-gfx
For DG1 we have a little of mix up wrt to DDI/port names and indexes.
Bspec refers to the ports as DDIA, DDIB, DDI USBC1 and DDI USBC2
(besides the DDIA, DDIB, DDIC, DDID), but the previous naming is the
most unambiguous one. This means that for any register on Display Engine
we should use the index of A, B, D and E. However in some places this is
not true:
- VBT: uses C and D and have to be mapped to D/E
- IO/Combo: uses C and D, but we already differentiate those when
we created the phy vs port distinction.
Ths additional mapping for VBT and phy are already covered in previous
patches, so now we can initialize the DDI as D/E.
Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 18 ++++++++++++------
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 4b5d6c7c5782d..2a345be705e65 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7219,10 +7219,7 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
{
if (phy == PHY_NONE)
return false;
- else if (IS_DG1(dev_priv))
- /* FIXME: Enable only two ports for now */
- return phy <= PHY_B;
- else if (IS_ROCKETLAKE(dev_priv))
+ else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
return phy <= PHY_D;
else if (IS_ELKHARTLAKE(dev_priv))
return phy <= PHY_C;
@@ -7246,7 +7243,7 @@ bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
{
- if (IS_ROCKETLAKE(i915) && port >= PORT_D)
+ if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_D)
return (enum phy)port - 1;
else if (IS_ELKHARTLAKE(i915) && port == PORT_D)
return PHY_A;
@@ -16859,9 +16856,18 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
return;
if (IS_DG1(dev_priv)) {
- /* FIXME: Enable only two ports for now */
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
+
+ /*
+ * Bspec lists the ports as A, B, C (USBC1) and D (USBC2).
+ * However from the Display Engine perspective all registers are
+ * actually wired to handle C and D as offsets of D/E. Instead
+ * of fighting all our macros for handling them specially for
+ * DG1, just call them D/E
+ */
+ intel_ddi_init(dev_priv, PORT_D);
+ intel_ddi_init(dev_priv, PORT_E);
} else if (IS_ROCKETLAKE(dev_priv)) {
/*
* If HTI (aka HDPORT) is enabled at boot, it may have taken
--
2.26.2
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^ permalink raw reply related [flat|nested] 48+ messages in thread* [Intel-gfx] [PATCH v2 30/32] drm/i915/dg1: Load DMC
2020-06-18 0:42 [Intel-gfx] [PATCH v2 00/32] Introduce DG1 Lucas De Marchi
` (28 preceding siblings ...)
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 29/32] drm/i915/dg1: enable PORT C/D aka D/E Lucas De Marchi
@ 2020-06-18 0:42 ` Lucas De Marchi
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 31/32] drm/i915/dg1: Add initial DG1 workarounds Lucas De Marchi
` (4 subsequent siblings)
34 siblings, 0 replies; 48+ messages in thread
From: Lucas De Marchi @ 2020-06-18 0:42 UTC (permalink / raw)
To: intel-gfx
From: Matt Atwood <matthew.s.atwood@intel.com>
Add support to load DMC v2.0.2 on DG1
While we're at it, tweak the TGL and RKL firmware size definition to
follow the convention used in previous platforms. Remove obsolete
commenting.
Bpec: 49230
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_csr.c | 19 +++++++++++++------
1 file changed, 13 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_csr.c b/drivers/gpu/drm/i915/display/intel_csr.c
index 9843c9af6c132..9cb293ee55cea 100644
--- a/drivers/gpu/drm/i915/display/intel_csr.c
+++ b/drivers/gpu/drm/i915/display/intel_csr.c
@@ -38,15 +38,19 @@
* low-power state and comes back to normal.
*/
-#define GEN12_CSR_MAX_FW_SIZE ICL_CSR_MAX_FW_SIZE
+#define DG1_CSR_PATH "i915/dg1_dmc_ver2_02.bin"
+#define DG1_CSR_VERSION_REQUIRED CSR_VERSION(2, 2)
+#define DG1_CSR_MAX_FW_SIZE ICL_CSR_MAX_FW_SIZE
+MODULE_FIRMWARE(DG1_CSR_PATH);
#define RKL_CSR_PATH "i915/rkl_dmc_ver2_01.bin"
#define RKL_CSR_VERSION_REQUIRED CSR_VERSION(2, 1)
+#define RKL_CSR_MAX_FW_SIZE ICL_CSR_MAX_FW_SIZE
MODULE_FIRMWARE(RKL_CSR_PATH);
#define TGL_CSR_PATH "i915/tgl_dmc_ver2_06.bin"
#define TGL_CSR_VERSION_REQUIRED CSR_VERSION(2, 6)
-#define TGL_CSR_MAX_FW_SIZE 0x6000
+#define TGL_CSR_MAX_FW_SIZE ICL_CSR_MAX_FW_SIZE
MODULE_FIRMWARE(TGL_CSR_PATH);
#define ICL_CSR_PATH "i915/icl_dmc_ver1_09.bin"
@@ -686,15 +690,18 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
*/
intel_csr_runtime_pm_get(dev_priv);
- if (IS_ROCKETLAKE(dev_priv)) {
+ if (IS_DG1(dev_priv)) {
+ csr->fw_path = DG1_CSR_PATH;
+ csr->required_version = DG1_CSR_VERSION_REQUIRED;
+ csr->max_fw_size = DG1_CSR_MAX_FW_SIZE;
+ } else if (IS_ROCKETLAKE(dev_priv)) {
csr->fw_path = RKL_CSR_PATH;
csr->required_version = RKL_CSR_VERSION_REQUIRED;
- csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
+ csr->max_fw_size = RKL_CSR_MAX_FW_SIZE;
} else if (INTEL_GEN(dev_priv) >= 12) {
csr->fw_path = TGL_CSR_PATH;
csr->required_version = TGL_CSR_VERSION_REQUIRED;
- /* Allow to load fw via parameter using the last known size */
- csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
+ csr->max_fw_size = TGL_CSR_MAX_FW_SIZE;
} else if (IS_GEN(dev_priv, 11)) {
csr->fw_path = ICL_CSR_PATH;
csr->required_version = ICL_CSR_VERSION_REQUIRED;
--
2.26.2
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^ permalink raw reply related [flat|nested] 48+ messages in thread* [Intel-gfx] [PATCH v2 31/32] drm/i915/dg1: Add initial DG1 workarounds
2020-06-18 0:42 [Intel-gfx] [PATCH v2 00/32] Introduce DG1 Lucas De Marchi
` (29 preceding siblings ...)
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 30/32] drm/i915/dg1: Load DMC Lucas De Marchi
@ 2020-06-18 0:42 ` Lucas De Marchi
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 32/32] drm/i915/dg1: DG1 does not support DC6 Lucas De Marchi
` (3 subsequent siblings)
34 siblings, 0 replies; 48+ messages in thread
From: Lucas De Marchi @ 2020-06-18 0:42 UTC (permalink / raw)
To: intel-gfx
From: Stuart Summers <stuart.summers@intel.com>
DG1 shares some workarounds with TGL and RKL and also has some
additional workarounds of its own.
Media power gating should not be applied so we just set it to
nop_init_clock_gating().
BSpec: 53508
Cc: Matt Atwood <matthew.s.atwood@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
.../drm/i915/display/intel_display_power.c | 5 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 4 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 91 ++++++++++++++++---
drivers/gpu/drm/i915/i915_reg.h | 10 +-
drivers/gpu/drm/i915/intel_pm.c | 17 +++-
5 files changed, 105 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 5dc62e6068f24..3a016abd80c53 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -5462,8 +5462,9 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
unsigned long abox_mask = INTEL_INFO(dev_priv)->abox_mask;
int config, i;
- if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
- /* Wa_1409767108: tgl */
+ if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
+ IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
+ /* Wa_1409767108:tgl,dg1 */
table = wa_1409767108_buddy_page_masks;
else
table = tgl_buddy_page_masks;
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 63ac79f88fa21..ba03f2459d9b5 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -2842,8 +2842,8 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv,
enum plane_id plane_id)
{
- /* Wa_14010477008:tgl[a0..c0],rkl[all] */
- if (IS_ROCKETLAKE(dev_priv) ||
+ /* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */
+ if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0))
return false;
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 741710ca2b9a5..5a9772011d335 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -641,6 +641,20 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
0);
}
+static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine,
+ struct i915_wa_list *wal)
+{
+ gen12_ctx_workarounds_init(engine, wal);
+
+ /* Wa_1409044764 */
+ WA_CLR_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
+ DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN);
+
+ /* Wa_22010493298 */
+ WA_SET_BIT_MASKED(HIZ_CHICKEN,
+ DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE);
+}
+
static void
__intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
struct i915_wa_list *wal,
@@ -653,7 +667,9 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
wa_init_start(wal, name, engine->name);
- if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915))
+ if (IS_DG1(i915))
+ dg1_ctx_workarounds_init(engine, wal);
+ else if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915))
tgl_ctx_workarounds_init(engine, wal);
else if (IS_GEN(i915, 12))
gen12_ctx_workarounds_init(engine, wal);
@@ -1213,10 +1229,30 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
}
+static void
+dg1_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
+{
+ gen12_gt_workarounds_init(i915, wal);
+
+ /* Wa_1607087056:dg1 */
+ if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0))
+ wa_write_or(wal,
+ SLICE_UNIT_LEVEL_CLKGATE,
+ L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
+
+ /* Wa_1409420604:dg1 */
+ if (IS_DG1(i915))
+ wa_write_or(wal,
+ SUBSLICE_UNIT_LEVEL_CLKGATE2,
+ CPSSUNIT_CLKGATE_DIS);
+}
+
static void
gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
{
- if (IS_TIGERLAKE(i915))
+ if (IS_DG1(i915))
+ dg1_gt_workarounds_init(i915, wal);
+ else if (IS_TIGERLAKE(i915))
tgl_gt_workarounds_init(i915, wal);
else if (IS_GEN(i915, 12))
gen12_gt_workarounds_init(i915, wal);
@@ -1581,6 +1617,20 @@ static void tgl_whitelist_build(struct intel_engine_cs *engine)
}
}
+static void dg1_whitelist_build(struct intel_engine_cs *engine)
+{
+ struct i915_wa_list *w = &engine->whitelist;
+
+ tgl_whitelist_build(engine);
+
+ /* GEN:BUG:1409280441:dg1 */
+ if (IS_DG1_REVID(engine->i915, DG1_REVID_A0, DG1_REVID_A0) &&
+ (engine->class == RENDER_CLASS ||
+ engine->class == COPY_ENGINE_CLASS))
+ whitelist_reg_ext(w, RING_ID(engine->mmio_base),
+ RING_FORCE_TO_NONPRIV_ACCESS_RD);
+}
+
void intel_engine_init_whitelist(struct intel_engine_cs *engine)
{
struct drm_i915_private *i915 = engine->i915;
@@ -1588,7 +1638,9 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
wa_init_start(w, "whitelist", engine->name);
- if (IS_GEN(i915, 12))
+ if (IS_DG1(i915))
+ dg1_whitelist_build(engine);
+ else if (IS_GEN(i915, 12))
tgl_whitelist_build(engine);
else if (IS_GEN(i915, 11))
icl_whitelist_build(engine);
@@ -1642,15 +1694,18 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
{
struct drm_i915_private *i915 = engine->i915;
- if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
+ if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
+ IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
/*
- * Wa_1607138336:tgl
- * Wa_1607063988:tgl
+ * Wa_1607138336:tgl[a0],dg1[a0]
+ * Wa_1607063988:tgl[a0],dg1[a0]
*/
wa_write_or(wal,
GEN9_CTX_PREEMPT_REG,
GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
+ }
+ if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
/*
* Wa_1606679103:tgl
* (see also Wa_1606682166:icl)
@@ -1663,32 +1718,40 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
wa_write_or(wal,
GEN7_FF_THREAD_MODE,
GEN12_FF_TESSELATION_DOP_GATE_DISABLE);
+ }
- /* Wa_1408615072:tgl */
+ if (IS_DG1(i915) || IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
+ /* Wa_1408615072:tgl[a0],dg1 */
wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
VSUNIT_CLKGATE_DIS_TGL);
}
- if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
- /* Wa_1606931601:tgl,rkl */
+ if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
+ /* Wa_1606931601:tgl,rkl,dg1 */
wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ);
+ }
- /* Wa_1409804808:tgl,rkl */
+ if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
+ IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
+ /* Wa_1409804808:tgl,rkl,dg1[a0] */
wa_masked_en(wal, GEN7_ROW_CHICKEN2,
GEN12_PUSH_CONST_DEREF_HOLD_DIS);
/*
* Wa_1409085225:tgl
- * Wa_14010229206:tgl,rkl
+ * Wa_14010229206:tgl,rkl,dg1[a0]
*/
wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH);
/*
* Wa_1607030317:tgl
* Wa_1607186500:tgl
- * Wa_1607297627:tgl,rkl there are multiple entries for this
- * WA in the BSpec; some indicate this is an A0-only WA,
- * others indicate it applies to all steppings.
+ * Wa_1607297627:tgl,rkl,dg1[a0]
+ *
+ * On TGL and RKL there are multiple entries for this WA in the
+ * BSpec; some indicate this is an A0-only WA, others indicate
+ * it applies to all steppings so we trust the "all steppings."
+ * For DG1 this only applies to A0.
*/
wa_masked_en(wal,
GEN6_RC_SLEEP_PSMI_CONTROL,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 34ed419283a70..0fd6aed908cde 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2530,6 +2530,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define RING_PSMI_CTL(base) _MMIO((base) + 0x50)
#define RING_MAX_IDLE(base) _MMIO((base) + 0x54)
#define RING_HWS_PGA(base) _MMIO((base) + 0x80)
+#define RING_ID(base) _MMIO((base) + 0x8c)
#define RING_HWS_PGA_GEN6(base) _MMIO((base) + 0x2080)
#define RING_RESET_CTL(base) _MMIO((base) + 0xd0)
#define RESET_CTL_CAT_ERROR REG_BIT(2)
@@ -4144,6 +4145,7 @@ enum {
#define GEN9_CLKGATE_DIS_3 _MMIO(0x46538)
#define TGL_VRH_GATING_DIS REG_BIT(31)
+#define DPT_GATING_DIS REG_BIT(22)
#define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C)
#define BXT_GMBUS_GATING_DIS (1 << 14)
@@ -7959,12 +7961,14 @@ enum {
#define GEN8_L3CNTLREG _MMIO(0x7034)
#define GEN8_ERRDETBCTRL (1 << 9)
-#define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304)
- #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC (1 << 11)
- #define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE (1 << 9)
+#define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304)
+ #define DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN REG_BIT(12)
+ #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC REG_BIT(11)
+ #define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE REG_BIT(9)
#define HIZ_CHICKEN _MMIO(0x7018)
# define CHV_HZ_8X8_MODE_IN_1X (1 << 15)
+# define DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE (1 << 14)
# define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE (1 << 3)
#define GEN9_SLICE_COMMON_ECO_CHICKEN0 _MMIO(0x7308)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2a32d62307954..77bf1a8c285b3 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7123,6 +7123,19 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
0, DFR_DISABLE);
}
+static void dg1_init_clock_gating(struct drm_i915_private *dev_priv)
+{
+ /*
+ * As opposed to TGL, we should not touch the registers for media power
+ * gating
+ */
+
+ /* Wa_14010096844:dg1[a0] */
+ if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0))
+ I915_WRITE(GEN9_CLKGATE_DIS_3, I915_READ(GEN9_CLKGATE_DIS_3) |
+ DPT_GATING_DIS);
+}
+
static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
{
if (!HAS_PCH_CNP(dev_priv))
@@ -7499,7 +7512,9 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
*/
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
{
- if (IS_GEN(dev_priv, 12))
+ if (IS_DG1(dev_priv))
+ dev_priv->display.init_clock_gating = dg1_init_clock_gating;
+ else if (IS_GEN(dev_priv, 12))
dev_priv->display.init_clock_gating = tgl_init_clock_gating;
else if (IS_GEN(dev_priv, 11))
dev_priv->display.init_clock_gating = icl_init_clock_gating;
--
2.26.2
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 48+ messages in thread* [Intel-gfx] [PATCH v2 32/32] drm/i915/dg1: DG1 does not support DC6
2020-06-18 0:42 [Intel-gfx] [PATCH v2 00/32] Introduce DG1 Lucas De Marchi
` (30 preceding siblings ...)
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 31/32] drm/i915/dg1: Add initial DG1 workarounds Lucas De Marchi
@ 2020-06-18 0:42 ` Lucas De Marchi
2020-06-18 0:56 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce DG1 (rev2) Patchwork
` (2 subsequent siblings)
34 siblings, 0 replies; 48+ messages in thread
From: Lucas De Marchi @ 2020-06-18 0:42 UTC (permalink / raw)
To: intel-gfx
From: Anshuman Gupta <anshuman.gupta@intel.com>
DC6 is not supported on DG1, so change the allowed DC mask for DG1.
Cc: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_power.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 3a016abd80c53..33c89cdfb3977 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -4689,7 +4689,10 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
int max_dc;
if (INTEL_GEN(dev_priv) >= 12) {
- max_dc = 4;
+ if (IS_DG1(dev_priv))
+ max_dc = 3;
+ else
+ max_dc = 4;
/*
* DC9 has a separate HW flow from the rest of the DC states,
* not depending on the DMC firmware. It's needed by system
--
2.26.2
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 48+ messages in thread* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce DG1 (rev2)
2020-06-18 0:42 [Intel-gfx] [PATCH v2 00/32] Introduce DG1 Lucas De Marchi
` (31 preceding siblings ...)
2020-06-18 0:42 ` [Intel-gfx] [PATCH v2 32/32] drm/i915/dg1: DG1 does not support DC6 Lucas De Marchi
@ 2020-06-18 0:56 ` Patchwork
2020-06-18 0:57 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-06-18 1:18 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
34 siblings, 0 replies; 48+ messages in thread
From: Patchwork @ 2020-06-18 0:56 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: Introduce DG1 (rev2)
URL : https://patchwork.freedesktop.org/series/77496/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
0168a6dc120d drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout
b533bd97f161 drm/i915/rkl: Add DPLL4 support
266c7f569e81 drm/i915/rkl: Handle HTI
0dcdc976291d drm/i915/rkl: Add initial workarounds
bc9a17f57138 drm/i915/rkl: Add Wa_14011224835 for PHY B initialization
8f27f0ec2180 drm/i915: Add has_master_unit_irq flag
5e175aa8a3f1 drm/i915/dg1: add initial DG-1 definitions
-:41: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#41: FILE: drivers/gpu/drm/i915/i915_drv.h:1563:
+#define IS_DG1_REVID(p, since, until) \
+ (IS_DG1(p) && IS_REVID(p, since, until))
total: 0 errors, 0 warnings, 1 checks, 53 lines checked
1f9863075fc5 drm/i915/dg1: Add DG1 PCI IDs
e5efb9b1d3a3 drm/i915/dg1: add support for the master unit interrupt
e45165e0ecea drm/i915/dg1: Remove SHPD_FILTER_CNT register programming
1a41b5d5a734 drm/i915/dg1: Add fake PCH
e1eb70f5e961 drm/i915/dg1: Initialize RAWCLK properly
40ff297509d4 drm/i915/dg1: Define MOCS table for DG1
95dc688fbad0 drm/i915/dg1: Add DG1 power wells
9e17457108d4 drm/i915/dg1: Increase mmio size to 4MB
63bc63bff441 drm/i915/dg1: Wait for pcode/uncore handshake at startup
bdec0b31b8b0 drm/i915/dg1: Add DPLL macros for DG1
67f3b147ced0 drm/i915/dg1: Add and setup DPLLs for DG1
955fe7def921 drm/i915/dg1: Enable DPLL for DG1
eb5057fd8085 drm/i915/dg1: add hpd interrupt handling
c56090c99ac7 drm/i915/dg1: invert HPD pins
592dd39473a7 drm/i915/dg1: gmbus pin mapping
9f15f4f45591 drm/i915/dg1: Enable first 2 ports for DG1
5a0cc1900a4f drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D
f2cac2139aff drm/i915/dg1: Update comp master/slave relationships for PHYs
2d8d3581a563 drm/i915/dg1: Update voltage swing tables for DP
ee62584fb237 drm/i915/dg1: provide port/phy mapping for vbt
6313b83c0806 drm/i915/dg1: map/unmap pll clocks
-:244: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'phy' - possible side-effects?
#244: FILE: drivers/gpu/drm/i915/i915_reg.h:10259:
+#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_VAL_TO_ID(val, phy) \
+ ((((val) & DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy)) >> ((phy % 2) * 2)) + (2 * (phy / 2)))
total: 0 errors, 0 warnings, 1 checks, 204 lines checked
a1377be54bdb drm/i915/dg1: enable PORT C/D aka D/E
ad0d140c9965 drm/i915/dg1: Load DMC
277c534f9b87 drm/i915/dg1: Add initial DG1 workarounds
a976a97be22b drm/i915/dg1: DG1 does not support DC6
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 48+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Introduce DG1 (rev2)
2020-06-18 0:42 [Intel-gfx] [PATCH v2 00/32] Introduce DG1 Lucas De Marchi
` (32 preceding siblings ...)
2020-06-18 0:56 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce DG1 (rev2) Patchwork
@ 2020-06-18 0:57 ` Patchwork
2020-06-18 1:18 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
34 siblings, 0 replies; 48+ messages in thread
From: Patchwork @ 2020-06-18 0:57 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: Introduce DG1 (rev2)
URL : https://patchwork.freedesktop.org/series/77496/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.0
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/display/intel_display.c:1223:22: error: Expected constant expression in case statement
+drivers/gpu/drm/i915/display/intel_display.c:1226:22: error: Expected constant expression in case statement
+drivers/gpu/drm/i915/display/intel_display.c:1229:22: error: Expected constant expression in case statement
+drivers/gpu/drm/i915/display/intel_display.c:1232:22: error: Expected constant expression in case statement
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2269:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2270:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2271:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2272:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2273:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2274:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gt/intel_lrc.c:2785:17: error: too long token expansion
+drivers/gpu/drm/i915/gt/intel_lrc.c:2785:17: error: too long token expansion
+drivers/gpu/drm/i915/gt/intel_reset.c:1310:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gt/sysfs_engines.c:61:10: error: bad integer constant expression
+drivers/gpu/drm/i915/gt/sysfs_engines.c:62:10: error: bad integer constant expression
+drivers/gpu/drm/i915/gt/sysfs_engines.c:66:10: error: bad integer constant expression
+drivers/gpu/drm/i915/gvt/mmio.c:287:23: warning: memcpy with byte count of 279040
+drivers/gpu/drm/i915/i915_perf.c:1425:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1479:15: warning: memset with byte count of 16777216
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 48+ messages in thread* [Intel-gfx] ✗ Fi.CI.BAT: failure for Introduce DG1 (rev2)
2020-06-18 0:42 [Intel-gfx] [PATCH v2 00/32] Introduce DG1 Lucas De Marchi
` (33 preceding siblings ...)
2020-06-18 0:57 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2020-06-18 1:18 ` Patchwork
34 siblings, 0 replies; 48+ messages in thread
From: Patchwork @ 2020-06-18 1:18 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: Introduce DG1 (rev2)
URL : https://patchwork.freedesktop.org/series/77496/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8639 -> Patchwork_17985
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_17985 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_17985, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17985/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_17985:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live@gt_engines:
- fi-skl-lmem: [PASS][1] -> [DMESG-WARN][2] +31 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-skl-lmem/igt@i915_selftest@live@gt_engines.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17985/fi-skl-lmem/igt@i915_selftest@live@gt_engines.html
* igt@runner@aborted:
- fi-tgl-u2: NOTRUN -> [FAIL][3]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17985/fi-tgl-u2/igt@runner@aborted.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@runner@aborted:
- {fi-tgl-dsi}: NOTRUN -> [FAIL][4]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17985/fi-tgl-dsi/igt@runner@aborted.html
Known issues
------------
Here are the changes found in Patchwork_17985 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_pm_rpm@module-reload:
- fi-glk-dsi: [PASS][5] -> [DMESG-WARN][6] ([i915#1982])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-glk-dsi/igt@i915_pm_rpm@module-reload.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17985/fi-glk-dsi/igt@i915_pm_rpm@module-reload.html
#### Possible fixes ####
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17985/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@kms_busy@basic@flip:
- fi-kbl-x1275: [DMESG-WARN][9] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-kbl-x1275/igt@kms_busy@basic@flip.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17985/fi-kbl-x1275/igt@kms_busy@basic@flip.html
#### Warnings ####
* igt@i915_pm_rpm@module-reload:
- fi-kbl-x1275: [SKIP][11] ([fdo#109271]) -> [DMESG-FAIL][12] ([i915#62] / [i915#95])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17985/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html
* igt@kms_force_connector_basic@force-edid:
- fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][14] ([i915#62] / [i915#92]) +3 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-kbl-x1275/igt@kms_force_connector_basic@force-edid.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17985/fi-kbl-x1275/igt@kms_force_connector_basic@force-edid.html
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
- fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92]) -> [DMESG-WARN][16] ([i915#62] / [i915#92] / [i915#95]) +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-kbl-x1275/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17985/fi-kbl-x1275/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (48 -> 41)
------------------------------
Missing (7): fi-ilk-m540 fi-cml-s fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper
Build changes
-------------
* Linux: CI_DRM_8639 -> Patchwork_17985
CI-20190529: 20190529
CI_DRM_8639: 47584e59cf51ec499d68a4cefbaf447448ce2894 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5711: 90611a0c90afa4a46496c78a4faf9638a1538ac3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17985: a976a97be22b2b60c6ba1f42db1c5fc110958ba0 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
a976a97be22b drm/i915/dg1: DG1 does not support DC6
277c534f9b87 drm/i915/dg1: Add initial DG1 workarounds
ad0d140c9965 drm/i915/dg1: Load DMC
a1377be54bdb drm/i915/dg1: enable PORT C/D aka D/E
6313b83c0806 drm/i915/dg1: map/unmap pll clocks
ee62584fb237 drm/i915/dg1: provide port/phy mapping for vbt
2d8d3581a563 drm/i915/dg1: Update voltage swing tables for DP
f2cac2139aff drm/i915/dg1: Update comp master/slave relationships for PHYs
5a0cc1900a4f drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D
9f15f4f45591 drm/i915/dg1: Enable first 2 ports for DG1
592dd39473a7 drm/i915/dg1: gmbus pin mapping
c56090c99ac7 drm/i915/dg1: invert HPD pins
eb5057fd8085 drm/i915/dg1: add hpd interrupt handling
955fe7def921 drm/i915/dg1: Enable DPLL for DG1
67f3b147ced0 drm/i915/dg1: Add and setup DPLLs for DG1
bdec0b31b8b0 drm/i915/dg1: Add DPLL macros for DG1
63bc63bff441 drm/i915/dg1: Wait for pcode/uncore handshake at startup
9e17457108d4 drm/i915/dg1: Increase mmio size to 4MB
95dc688fbad0 drm/i915/dg1: Add DG1 power wells
40ff297509d4 drm/i915/dg1: Define MOCS table for DG1
e1eb70f5e961 drm/i915/dg1: Initialize RAWCLK properly
1a41b5d5a734 drm/i915/dg1: Add fake PCH
e45165e0ecea drm/i915/dg1: Remove SHPD_FILTER_CNT register programming
e5efb9b1d3a3 drm/i915/dg1: add support for the master unit interrupt
1f9863075fc5 drm/i915/dg1: Add DG1 PCI IDs
5e175aa8a3f1 drm/i915/dg1: add initial DG-1 definitions
8f27f0ec2180 drm/i915: Add has_master_unit_irq flag
bc9a17f57138 drm/i915/rkl: Add Wa_14011224835 for PHY B initialization
0dcdc976291d drm/i915/rkl: Add initial workarounds
266c7f569e81 drm/i915/rkl: Handle HTI
b533bd97f161 drm/i915/rkl: Add DPLL4 support
0168a6dc120d drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17985/index.html
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