From: Anup Patel <anup.patel@wdc.com> To: Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, Rob Herring <robh+dt@kernel.org>, Daniel Lezcano <daniel.lezcano@linaro.org>, Thomas Gleixner <tglx@linutronix.de> Cc: Damien Le Moal <damien.lemoal@wdc.com>, Atish Patra <atish.patra@wdc.com>, Alistair Francis <Alistair.Francis@wdc.com>, Anup Patel <anup@brainfault.org>, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel <anup.patel@wdc.com> Subject: [PATCH v2 3/5] clocksource/drivers/timer-riscv: Remove MMIO related stuff Date: Sat, 27 Jun 2020 21:49:55 +0530 [thread overview] Message-ID: <20200627161957.134376-4-anup.patel@wdc.com> (raw) In-Reply-To: <20200627161957.134376-1-anup.patel@wdc.com> Right now the RISC-V timer is convoluted to support: 1. Linux RISC-V S-mode (with MMU) where it will use TIME CSR for clocksource and SBI timer calls for clockevent device. 2. Linux RISC-V M-mode (without MMU) where it will use CLINT MMIO counter register for clocksource and CLINT MMIO compare register for clockevent device. This patch removes MMIO related stuff from RISC-V timer driver so that we can have a separate CLINT timer driver. Signed-off-by: Anup Patel <anup.patel@wdc.com> --- arch/riscv/Kconfig | 2 +- arch/riscv/include/asm/timex.h | 28 +++++++--------------------- drivers/clocksource/Kconfig | 2 +- drivers/clocksource/timer-riscv.c | 17 ++--------------- 4 files changed, 11 insertions(+), 38 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 448a9952aa2f..868bbc4d0803 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -72,7 +72,7 @@ config RISCV select PCI_DOMAINS_GENERIC if PCI select PCI_MSI if PCI select RISCV_INTC - select RISCV_TIMER + select RISCV_TIMER if RISCV_SBI select SPARSEMEM_STATIC if 32BIT select SPARSE_IRQ select SYSCTL_EXCEPTION_TRACE diff --git a/arch/riscv/include/asm/timex.h b/arch/riscv/include/asm/timex.h index bad2a7c2cda5..a3fb85d505d4 100644 --- a/arch/riscv/include/asm/timex.h +++ b/arch/riscv/include/asm/timex.h @@ -7,41 +7,27 @@ #define _ASM_RISCV_TIMEX_H #include <asm/csr.h> -#include <asm/mmio.h> typedef unsigned long cycles_t; -extern u64 __iomem *riscv_time_val; -extern u64 __iomem *riscv_time_cmp; - -#ifdef CONFIG_64BIT -#define mmio_get_cycles() readq_relaxed(riscv_time_val) -#else -#define mmio_get_cycles() readl_relaxed(riscv_time_val) -#define mmio_get_cycles_hi() readl_relaxed(((u32 *)riscv_time_val) + 1) -#endif - static inline cycles_t get_cycles(void) { - if (IS_ENABLED(CONFIG_RISCV_SBI)) - return csr_read(CSR_TIME); - return mmio_get_cycles(); + return csr_read(CSR_TIME); } #define get_cycles get_cycles +static inline u32 get_cycles_hi(void) +{ + return csr_read(CSR_TIMEH); +} +#define get_cycles_hi get_cycles_hi + #ifdef CONFIG_64BIT static inline u64 get_cycles64(void) { return get_cycles(); } #else /* CONFIG_64BIT */ -static inline u32 get_cycles_hi(void) -{ - if (IS_ENABLED(CONFIG_RISCV_SBI)) - return csr_read(CSR_TIMEH); - return mmio_get_cycles_hi(); -} - static inline u64 get_cycles64(void) { u32 hi, lo; diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 91418381fcd4..8c6a0f1274af 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -649,7 +649,7 @@ config ATCPIT100_TIMER config RISCV_TIMER bool "Timer for the RISC-V platform" - depends on GENERIC_SCHED_CLOCK && RISCV + depends on GENERIC_SCHED_CLOCK && RISCV_SBI default y select TIMER_PROBE select TIMER_OF diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c index 9de1dabfb126..c51c5ed15aa7 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -19,26 +19,13 @@ #include <linux/of_irq.h> #include <asm/smp.h> #include <asm/sbi.h> - -u64 __iomem *riscv_time_cmp; -u64 __iomem *riscv_time_val; - -static inline void mmio_set_timer(u64 val) -{ - void __iomem *r; - - r = riscv_time_cmp + cpuid_to_hartid_map(smp_processor_id()); - writeq_relaxed(val, r); -} +#include <asm/timex.h> static int riscv_clock_next_event(unsigned long delta, struct clock_event_device *ce) { csr_set(CSR_IE, IE_TIE); - if (IS_ENABLED(CONFIG_RISCV_SBI)) - sbi_set_timer(get_cycles64() + delta); - else - mmio_set_timer(get_cycles64() + delta); + sbi_set_timer(get_cycles64() + delta); return 0; } -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <anup.patel@wdc.com> To: Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, Rob Herring <robh+dt@kernel.org>, Daniel Lezcano <daniel.lezcano@linaro.org>, Thomas Gleixner <tglx@linutronix.de> Cc: devicetree@vger.kernel.org, Damien Le Moal <damien.lemoal@wdc.com>, Anup Patel <anup@brainfault.org>, Anup Patel <anup.patel@wdc.com>, linux-kernel@vger.kernel.org, Atish Patra <atish.patra@wdc.com>, Alistair Francis <Alistair.Francis@wdc.com>, linux-riscv@lists.infradead.org Subject: [PATCH v2 3/5] clocksource/drivers/timer-riscv: Remove MMIO related stuff Date: Sat, 27 Jun 2020 21:49:55 +0530 [thread overview] Message-ID: <20200627161957.134376-4-anup.patel@wdc.com> (raw) In-Reply-To: <20200627161957.134376-1-anup.patel@wdc.com> Right now the RISC-V timer is convoluted to support: 1. Linux RISC-V S-mode (with MMU) where it will use TIME CSR for clocksource and SBI timer calls for clockevent device. 2. Linux RISC-V M-mode (without MMU) where it will use CLINT MMIO counter register for clocksource and CLINT MMIO compare register for clockevent device. This patch removes MMIO related stuff from RISC-V timer driver so that we can have a separate CLINT timer driver. Signed-off-by: Anup Patel <anup.patel@wdc.com> --- arch/riscv/Kconfig | 2 +- arch/riscv/include/asm/timex.h | 28 +++++++--------------------- drivers/clocksource/Kconfig | 2 +- drivers/clocksource/timer-riscv.c | 17 ++--------------- 4 files changed, 11 insertions(+), 38 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 448a9952aa2f..868bbc4d0803 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -72,7 +72,7 @@ config RISCV select PCI_DOMAINS_GENERIC if PCI select PCI_MSI if PCI select RISCV_INTC - select RISCV_TIMER + select RISCV_TIMER if RISCV_SBI select SPARSEMEM_STATIC if 32BIT select SPARSE_IRQ select SYSCTL_EXCEPTION_TRACE diff --git a/arch/riscv/include/asm/timex.h b/arch/riscv/include/asm/timex.h index bad2a7c2cda5..a3fb85d505d4 100644 --- a/arch/riscv/include/asm/timex.h +++ b/arch/riscv/include/asm/timex.h @@ -7,41 +7,27 @@ #define _ASM_RISCV_TIMEX_H #include <asm/csr.h> -#include <asm/mmio.h> typedef unsigned long cycles_t; -extern u64 __iomem *riscv_time_val; -extern u64 __iomem *riscv_time_cmp; - -#ifdef CONFIG_64BIT -#define mmio_get_cycles() readq_relaxed(riscv_time_val) -#else -#define mmio_get_cycles() readl_relaxed(riscv_time_val) -#define mmio_get_cycles_hi() readl_relaxed(((u32 *)riscv_time_val) + 1) -#endif - static inline cycles_t get_cycles(void) { - if (IS_ENABLED(CONFIG_RISCV_SBI)) - return csr_read(CSR_TIME); - return mmio_get_cycles(); + return csr_read(CSR_TIME); } #define get_cycles get_cycles +static inline u32 get_cycles_hi(void) +{ + return csr_read(CSR_TIMEH); +} +#define get_cycles_hi get_cycles_hi + #ifdef CONFIG_64BIT static inline u64 get_cycles64(void) { return get_cycles(); } #else /* CONFIG_64BIT */ -static inline u32 get_cycles_hi(void) -{ - if (IS_ENABLED(CONFIG_RISCV_SBI)) - return csr_read(CSR_TIMEH); - return mmio_get_cycles_hi(); -} - static inline u64 get_cycles64(void) { u32 hi, lo; diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 91418381fcd4..8c6a0f1274af 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -649,7 +649,7 @@ config ATCPIT100_TIMER config RISCV_TIMER bool "Timer for the RISC-V platform" - depends on GENERIC_SCHED_CLOCK && RISCV + depends on GENERIC_SCHED_CLOCK && RISCV_SBI default y select TIMER_PROBE select TIMER_OF diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c index 9de1dabfb126..c51c5ed15aa7 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -19,26 +19,13 @@ #include <linux/of_irq.h> #include <asm/smp.h> #include <asm/sbi.h> - -u64 __iomem *riscv_time_cmp; -u64 __iomem *riscv_time_val; - -static inline void mmio_set_timer(u64 val) -{ - void __iomem *r; - - r = riscv_time_cmp + cpuid_to_hartid_map(smp_processor_id()); - writeq_relaxed(val, r); -} +#include <asm/timex.h> static int riscv_clock_next_event(unsigned long delta, struct clock_event_device *ce) { csr_set(CSR_IE, IE_TIE); - if (IS_ENABLED(CONFIG_RISCV_SBI)) - sbi_set_timer(get_cycles64() + delta); - else - mmio_set_timer(get_cycles64() + delta); + sbi_set_timer(get_cycles64() + delta); return 0; } -- 2.25.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2020-06-27 16:21 UTC|newest] Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-06-27 16:19 [PATCH v2 0/5] Dedicated CLINT timer driver Anup Patel 2020-06-27 16:19 ` Anup Patel 2020-06-27 16:19 ` [PATCH v2 1/5] RISC-V: Add mechanism to provide custom IPI operations Anup Patel 2020-06-27 16:19 ` Anup Patel 2020-06-27 16:19 ` [PATCH v2 2/5] RISC-V: Remove CLINT related code Anup Patel 2020-06-27 16:19 ` Anup Patel 2020-06-27 16:19 ` Anup Patel [this message] 2020-06-27 16:19 ` [PATCH v2 3/5] clocksource/drivers/timer-riscv: Remove MMIO related stuff Anup Patel 2020-06-29 16:03 ` kernel test robot 2020-06-27 16:19 ` [PATCH v2 4/5] clocksource/drivers: Add CLINT timer driver Anup Patel 2020-06-27 16:19 ` Anup Patel 2020-06-29 17:44 ` kernel test robot 2020-06-27 16:19 ` [PATCH v2 5/5] dt-bindings: timer: Add CLINT bindings Anup Patel 2020-06-27 16:19 ` Anup Patel 2020-07-14 2:37 ` Rob Herring 2020-07-14 2:37 ` Rob Herring 2020-07-14 3:47 ` Anup Patel 2020-07-14 3:47 ` Anup Patel 2020-07-14 15:04 ` Rob Herring 2020-07-14 15:04 ` Rob Herring 2020-07-13 23:02 ` [PATCH v2 0/5] Dedicated CLINT timer driver Palmer Dabbelt 2020-07-13 23:02 ` Palmer Dabbelt 2020-07-14 3:49 ` Anup Patel 2020-07-14 3:49 ` Anup Patel
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