From: Rob Herring <robh@kernel.org> To: Anup Patel <anup@brainfault.org> Cc: Anup Patel <anup.patel@wdc.com>, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, Daniel Lezcano <daniel.lezcano@linaro.org>, Thomas Gleixner <tglx@linutronix.de>, Damien Le Moal <damien.lemoal@wdc.com>, Atish Patra <atish.patra@wdc.com>, Alistair Francis <Alistair.Francis@wdc.com>, linux-riscv <linux-riscv@lists.infradead.org>, "linux-kernel@vger.kernel.org List" <linux-kernel@vger.kernel.org>, devicetree@vger.kernel.org, Palmer Dabbelt <palmerdabbelt@google.com> Subject: Re: [PATCH v2 5/5] dt-bindings: timer: Add CLINT bindings Date: Tue, 14 Jul 2020 09:04:12 -0600 [thread overview] Message-ID: <CAL_JsqL9xcnzNAtL5nM3tt21pbfwz8qB_BSwfFAtXe0mj=MVEA@mail.gmail.com> (raw) In-Reply-To: <CAAhSdy0O0YoDJ84NX8OasjuTdE8pd=Yk51WJWLpBiAEk3AcCQQ@mail.gmail.com> On Mon, Jul 13, 2020 at 9:47 PM Anup Patel <anup@brainfault.org> wrote: > > On Tue, Jul 14, 2020 at 8:07 AM Rob Herring <robh@kernel.org> wrote: > > > > On Sat, Jun 27, 2020 at 09:49:57PM +0530, Anup Patel wrote: > > > We add DT bindings documentation for CLINT device. > > > > > > Signed-off-by: Anup Patel <anup.patel@wdc.com> > > > Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> > > > --- > > > .../bindings/timer/sifive,clint.txt | 34 +++++++++++++++++++ > > > 1 file changed, 34 insertions(+) > > > create mode 100644 Documentation/devicetree/bindings/timer/sifive,clint.txt > > > > Bindings should be in DT schema format now. > > Okay, will update. > > > > > > > > > diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.txt b/Documentation/devicetree/bindings/timer/sifive,clint.txt > > > new file mode 100644 > > > index 000000000000..45b75347a7d5 > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/timer/sifive,clint.txt > > > @@ -0,0 +1,34 @@ > > > +SiFive Core Local Interruptor (CLINT) > > > +------------------------------------- > > > + > > > +SiFive (and other RISC-V) SOCs include an implementation of the SiFive Core > > > +Local Interruptor (CLINT) for M-mode timer and inter-processor interrupts. > > > + > > > +It directly connects to the timer and inter-processor interrupt lines of > > > +various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local interrupt > > > +controller is the parent interrupt controller for CLINT device. > > > + > > > +The clock frequency of CLINT is specified via "timebase-frequency" DT > > > +property of "/cpus" DT node. The "timebase-frequency" DT property is > > > +described in: Documentation/devicetree/bindings/riscv/cpus.yaml > > > + > > > +Required properties: > > > +- compatible : should be "riscv,clint0" or "sifive,clint-1.0.0". A specific > > > > A new versioning scheme from SiFive? To review, we don't do version > > numbers unless there's a well defined and documented scheme. IOW, one > > that's not s/w folks just making up v1, v2, v3, etc. > > The "riscv,clint0" is already used by various RISC-V systems (including QEMU). Not my problem that undocumented bindings are being used. > The "sifive,clint-1.0.0" is for being consistent with the PLIC > versioning scheme. Where is that documented? This is what I expect you to be following or updating to match: Documentation/devicetree/bindings/sifive/sifive-blocks-ip-versioning.txt > > There is no clear documentation of CLINT versioning scheme. I think it's best > to just drop "sifive,clint-1.0.0" . Agree ?? No, because then you are left with a very generic compatible string. You need something specific enough to handle any implementation features/quirks/bugs without needing a DT update. Typically, this means a per SoC compatible string for a block as even the same IP version can have different integration quirks. Rob
WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org> To: Anup Patel <anup@brainfault.org> Cc: devicetree@vger.kernel.org, Damien Le Moal <damien.lemoal@wdc.com>, Daniel Lezcano <daniel.lezcano@linaro.org>, Anup Patel <anup.patel@wdc.com>, "linux-kernel@vger.kernel.org List" <linux-kernel@vger.kernel.org>, Atish Patra <atish.patra@wdc.com>, Albert Ou <aou@eecs.berkeley.edu>, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmerdabbelt@google.com>, Alistair Francis <Alistair.Francis@wdc.com>, Thomas Gleixner <tglx@linutronix.de>, linux-riscv <linux-riscv@lists.infradead.org> Subject: Re: [PATCH v2 5/5] dt-bindings: timer: Add CLINT bindings Date: Tue, 14 Jul 2020 09:04:12 -0600 [thread overview] Message-ID: <CAL_JsqL9xcnzNAtL5nM3tt21pbfwz8qB_BSwfFAtXe0mj=MVEA@mail.gmail.com> (raw) In-Reply-To: <CAAhSdy0O0YoDJ84NX8OasjuTdE8pd=Yk51WJWLpBiAEk3AcCQQ@mail.gmail.com> On Mon, Jul 13, 2020 at 9:47 PM Anup Patel <anup@brainfault.org> wrote: > > On Tue, Jul 14, 2020 at 8:07 AM Rob Herring <robh@kernel.org> wrote: > > > > On Sat, Jun 27, 2020 at 09:49:57PM +0530, Anup Patel wrote: > > > We add DT bindings documentation for CLINT device. > > > > > > Signed-off-by: Anup Patel <anup.patel@wdc.com> > > > Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> > > > --- > > > .../bindings/timer/sifive,clint.txt | 34 +++++++++++++++++++ > > > 1 file changed, 34 insertions(+) > > > create mode 100644 Documentation/devicetree/bindings/timer/sifive,clint.txt > > > > Bindings should be in DT schema format now. > > Okay, will update. > > > > > > > > > diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.txt b/Documentation/devicetree/bindings/timer/sifive,clint.txt > > > new file mode 100644 > > > index 000000000000..45b75347a7d5 > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/timer/sifive,clint.txt > > > @@ -0,0 +1,34 @@ > > > +SiFive Core Local Interruptor (CLINT) > > > +------------------------------------- > > > + > > > +SiFive (and other RISC-V) SOCs include an implementation of the SiFive Core > > > +Local Interruptor (CLINT) for M-mode timer and inter-processor interrupts. > > > + > > > +It directly connects to the timer and inter-processor interrupt lines of > > > +various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local interrupt > > > +controller is the parent interrupt controller for CLINT device. > > > + > > > +The clock frequency of CLINT is specified via "timebase-frequency" DT > > > +property of "/cpus" DT node. The "timebase-frequency" DT property is > > > +described in: Documentation/devicetree/bindings/riscv/cpus.yaml > > > + > > > +Required properties: > > > +- compatible : should be "riscv,clint0" or "sifive,clint-1.0.0". A specific > > > > A new versioning scheme from SiFive? To review, we don't do version > > numbers unless there's a well defined and documented scheme. IOW, one > > that's not s/w folks just making up v1, v2, v3, etc. > > The "riscv,clint0" is already used by various RISC-V systems (including QEMU). Not my problem that undocumented bindings are being used. > The "sifive,clint-1.0.0" is for being consistent with the PLIC > versioning scheme. Where is that documented? This is what I expect you to be following or updating to match: Documentation/devicetree/bindings/sifive/sifive-blocks-ip-versioning.txt > > There is no clear documentation of CLINT versioning scheme. I think it's best > to just drop "sifive,clint-1.0.0" . Agree ?? No, because then you are left with a very generic compatible string. You need something specific enough to handle any implementation features/quirks/bugs without needing a DT update. Typically, this means a per SoC compatible string for a block as even the same IP version can have different integration quirks. Rob _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2020-07-14 15:04 UTC|newest] Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-06-27 16:19 [PATCH v2 0/5] Dedicated CLINT timer driver Anup Patel 2020-06-27 16:19 ` Anup Patel 2020-06-27 16:19 ` [PATCH v2 1/5] RISC-V: Add mechanism to provide custom IPI operations Anup Patel 2020-06-27 16:19 ` Anup Patel 2020-06-27 16:19 ` [PATCH v2 2/5] RISC-V: Remove CLINT related code Anup Patel 2020-06-27 16:19 ` Anup Patel 2020-06-27 16:19 ` [PATCH v2 3/5] clocksource/drivers/timer-riscv: Remove MMIO related stuff Anup Patel 2020-06-27 16:19 ` Anup Patel 2020-06-29 16:03 ` kernel test robot 2020-06-27 16:19 ` [PATCH v2 4/5] clocksource/drivers: Add CLINT timer driver Anup Patel 2020-06-27 16:19 ` Anup Patel 2020-06-29 17:44 ` kernel test robot 2020-06-27 16:19 ` [PATCH v2 5/5] dt-bindings: timer: Add CLINT bindings Anup Patel 2020-06-27 16:19 ` Anup Patel 2020-07-14 2:37 ` Rob Herring 2020-07-14 2:37 ` Rob Herring 2020-07-14 3:47 ` Anup Patel 2020-07-14 3:47 ` Anup Patel 2020-07-14 15:04 ` Rob Herring [this message] 2020-07-14 15:04 ` Rob Herring 2020-07-13 23:02 ` [PATCH v2 0/5] Dedicated CLINT timer driver Palmer Dabbelt 2020-07-13 23:02 ` Palmer Dabbelt 2020-07-14 3:49 ` Anup Patel 2020-07-14 3:49 ` Anup Patel
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