From: Palmer Dabbelt <palmer@dabbelt.com> To: Anup Patel <Anup.Patel@wdc.com> Cc: Paul Walmsley <paul.walmsley@sifive.com>, aou@eecs.berkeley.edu, robh+dt@kernel.org, daniel.lezcano@linaro.org, tglx@linutronix.de, Damien Le Moal <Damien.LeMoal@wdc.com>, Atish Patra <Atish.Patra@wdc.com>, Alistair Francis <Alistair.Francis@wdc.com>, anup@brainfault.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel <Anup.Patel@wdc.com> Subject: Re: [PATCH v2 0/5] Dedicated CLINT timer driver Date: Mon, 13 Jul 2020 16:02:01 -0700 (PDT) [thread overview] Message-ID: <mhng-4d70be69-ef20-4d38-bda4-ec4101530c0a@palmerdabbelt-glaptop1> (raw) In-Reply-To: <20200627161957.134376-1-anup.patel@wdc.com> On Sat, 27 Jun 2020 09:19:52 PDT (-0700), Anup Patel wrote: > The current RISC-V timer driver is convoluted and implements two > distinct timers: > 1. S-mode timer: This is for Linux RISC-V S-mode with MMU. The > clocksource is implemented using TIME CSR and clockevent device > is implemented using SBI Timer calls. > 2. M-mode timer: This is for Linux RISC-V M-mode without MMU. The > clocksource is implemented using CLINT MMIO time register and > clockevent device is implemented using CLINT MMIO timecmp registers. > > This patchset removes clint related code from RISC-V timer driver and > arch/riscv directory. Instead, the series adds a dedicated MMIO based > CLINT driver under drivers/clocksource directory which can be used by > Linux RISC-V M-mode (i.e NoMMU Linux RISC-V). > > The patchset is based up Linux-5.8-rc2 and can be found at riscv_clint_v2 > branch of: https://github.com/avpatel/linux.git > > This series is tested on: > 1. QEMU RV64 virt machine using Linux RISC-V S-mode > 2. QEMU RV32 virt machine using Linux RISC-V S-mode > 3. QEMU RV64 virt machine using Linux RISC-V M-mode (i.e. NoMMU) > > Changes since v1: > - Rebased series on Linux-5.8-rc2 > - Added pr_warn() for case where ipi_ops not available in PATCH1 > - Updated ipi_inject() prototype to use "struct cpumask *" in PATCH1 > - Updated CLINT_TIMER kconfig option to depend on RISCV_M_MODE in PATCH4 > - Added riscv,clint0 compatible string in DT bindings document > > Anup Patel (5): > RISC-V: Add mechanism to provide custom IPI operations > RISC-V: Remove CLINT related code > clocksource/drivers/timer-riscv: Remove MMIO related stuff > clocksource/drivers: Add CLINT timer driver > dt-bindings: timer: Add CLINT bindings This all generally LGTM, though I haven't been through the code line-by-line yet. It touches a bunch of trees, so I'd prefer to have some Acks before merging -- I'll dig through the RISC-V specific stuff, but the new CLINT driver probhably deserves a look from one of the clocksource folks. I think the only issue is that the port will be broken between patch 2 and 4, as at that point we won't have an M-mode timer driver. I think it shouldn't be too much to just reorder these, LMK if you want to do it or you want me to. Thanks! > > .../bindings/timer/sifive,clint.txt | 34 +++ > arch/riscv/Kconfig | 2 +- > arch/riscv/include/asm/clint.h | 39 --- > arch/riscv/include/asm/smp.h | 11 + > arch/riscv/include/asm/timex.h | 28 +-- > arch/riscv/kernel/Makefile | 2 +- > arch/riscv/kernel/clint.c | 44 ---- > arch/riscv/kernel/sbi.c | 14 ++ > arch/riscv/kernel/setup.c | 2 - > arch/riscv/kernel/smp.c | 44 ++-- > arch/riscv/kernel/smpboot.c | 4 +- > drivers/clocksource/Kconfig | 12 +- > drivers/clocksource/Makefile | 1 + > drivers/clocksource/timer-clint.c | 229 ++++++++++++++++++ > drivers/clocksource/timer-riscv.c | 17 +- > include/linux/cpuhotplug.h | 1 + > 16 files changed, 337 insertions(+), 147 deletions(-) > create mode 100644 Documentation/devicetree/bindings/timer/sifive,clint.txt > delete mode 100644 arch/riscv/include/asm/clint.h > delete mode 100644 arch/riscv/kernel/clint.c > create mode 100644 drivers/clocksource/timer-clint.c
WARNING: multiple messages have this Message-ID (diff)
From: Palmer Dabbelt <palmer@dabbelt.com> To: Anup Patel <Anup.Patel@wdc.com> Cc: devicetree@vger.kernel.org, Damien Le Moal <Damien.LeMoal@wdc.com>, aou@eecs.berkeley.edu, anup@brainfault.org, daniel.lezcano@linaro.org, linux-kernel@vger.kernel.org, Atish Patra <Atish.Patra@wdc.com>, Anup Patel <Anup.Patel@wdc.com>, robh+dt@kernel.org, Alistair Francis <Alistair.Francis@wdc.com>, Paul Walmsley <paul.walmsley@sifive.com>, tglx@linutronix.de, linux-riscv@lists.infradead.org Subject: Re: [PATCH v2 0/5] Dedicated CLINT timer driver Date: Mon, 13 Jul 2020 16:02:01 -0700 (PDT) [thread overview] Message-ID: <mhng-4d70be69-ef20-4d38-bda4-ec4101530c0a@palmerdabbelt-glaptop1> (raw) In-Reply-To: <20200627161957.134376-1-anup.patel@wdc.com> On Sat, 27 Jun 2020 09:19:52 PDT (-0700), Anup Patel wrote: > The current RISC-V timer driver is convoluted and implements two > distinct timers: > 1. S-mode timer: This is for Linux RISC-V S-mode with MMU. The > clocksource is implemented using TIME CSR and clockevent device > is implemented using SBI Timer calls. > 2. M-mode timer: This is for Linux RISC-V M-mode without MMU. The > clocksource is implemented using CLINT MMIO time register and > clockevent device is implemented using CLINT MMIO timecmp registers. > > This patchset removes clint related code from RISC-V timer driver and > arch/riscv directory. Instead, the series adds a dedicated MMIO based > CLINT driver under drivers/clocksource directory which can be used by > Linux RISC-V M-mode (i.e NoMMU Linux RISC-V). > > The patchset is based up Linux-5.8-rc2 and can be found at riscv_clint_v2 > branch of: https://github.com/avpatel/linux.git > > This series is tested on: > 1. QEMU RV64 virt machine using Linux RISC-V S-mode > 2. QEMU RV32 virt machine using Linux RISC-V S-mode > 3. QEMU RV64 virt machine using Linux RISC-V M-mode (i.e. NoMMU) > > Changes since v1: > - Rebased series on Linux-5.8-rc2 > - Added pr_warn() for case where ipi_ops not available in PATCH1 > - Updated ipi_inject() prototype to use "struct cpumask *" in PATCH1 > - Updated CLINT_TIMER kconfig option to depend on RISCV_M_MODE in PATCH4 > - Added riscv,clint0 compatible string in DT bindings document > > Anup Patel (5): > RISC-V: Add mechanism to provide custom IPI operations > RISC-V: Remove CLINT related code > clocksource/drivers/timer-riscv: Remove MMIO related stuff > clocksource/drivers: Add CLINT timer driver > dt-bindings: timer: Add CLINT bindings This all generally LGTM, though I haven't been through the code line-by-line yet. It touches a bunch of trees, so I'd prefer to have some Acks before merging -- I'll dig through the RISC-V specific stuff, but the new CLINT driver probhably deserves a look from one of the clocksource folks. I think the only issue is that the port will be broken between patch 2 and 4, as at that point we won't have an M-mode timer driver. I think it shouldn't be too much to just reorder these, LMK if you want to do it or you want me to. Thanks! > > .../bindings/timer/sifive,clint.txt | 34 +++ > arch/riscv/Kconfig | 2 +- > arch/riscv/include/asm/clint.h | 39 --- > arch/riscv/include/asm/smp.h | 11 + > arch/riscv/include/asm/timex.h | 28 +-- > arch/riscv/kernel/Makefile | 2 +- > arch/riscv/kernel/clint.c | 44 ---- > arch/riscv/kernel/sbi.c | 14 ++ > arch/riscv/kernel/setup.c | 2 - > arch/riscv/kernel/smp.c | 44 ++-- > arch/riscv/kernel/smpboot.c | 4 +- > drivers/clocksource/Kconfig | 12 +- > drivers/clocksource/Makefile | 1 + > drivers/clocksource/timer-clint.c | 229 ++++++++++++++++++ > drivers/clocksource/timer-riscv.c | 17 +- > include/linux/cpuhotplug.h | 1 + > 16 files changed, 337 insertions(+), 147 deletions(-) > create mode 100644 Documentation/devicetree/bindings/timer/sifive,clint.txt > delete mode 100644 arch/riscv/include/asm/clint.h > delete mode 100644 arch/riscv/kernel/clint.c > create mode 100644 drivers/clocksource/timer-clint.c _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2020-07-13 23:02 UTC|newest] Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-06-27 16:19 [PATCH v2 0/5] Dedicated CLINT timer driver Anup Patel 2020-06-27 16:19 ` Anup Patel 2020-06-27 16:19 ` [PATCH v2 1/5] RISC-V: Add mechanism to provide custom IPI operations Anup Patel 2020-06-27 16:19 ` Anup Patel 2020-06-27 16:19 ` [PATCH v2 2/5] RISC-V: Remove CLINT related code Anup Patel 2020-06-27 16:19 ` Anup Patel 2020-06-27 16:19 ` [PATCH v2 3/5] clocksource/drivers/timer-riscv: Remove MMIO related stuff Anup Patel 2020-06-27 16:19 ` Anup Patel 2020-06-29 16:03 ` kernel test robot 2020-06-27 16:19 ` [PATCH v2 4/5] clocksource/drivers: Add CLINT timer driver Anup Patel 2020-06-27 16:19 ` Anup Patel 2020-06-29 17:44 ` kernel test robot 2020-06-27 16:19 ` [PATCH v2 5/5] dt-bindings: timer: Add CLINT bindings Anup Patel 2020-06-27 16:19 ` Anup Patel 2020-07-14 2:37 ` Rob Herring 2020-07-14 2:37 ` Rob Herring 2020-07-14 3:47 ` Anup Patel 2020-07-14 3:47 ` Anup Patel 2020-07-14 15:04 ` Rob Herring 2020-07-14 15:04 ` Rob Herring 2020-07-13 23:02 ` Palmer Dabbelt [this message] 2020-07-13 23:02 ` [PATCH v2 0/5] Dedicated CLINT timer driver Palmer Dabbelt 2020-07-14 3:49 ` Anup Patel 2020-07-14 3:49 ` Anup Patel
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