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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 14/20] drm/i915: Replace some gamma_mode ifs with switches
Date: Sat, 18 Jul 2020 00:13:39 +0300	[thread overview]
Message-ID: <20200717211345.26851-15-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20200717211345.26851-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Since gamma_mode can have more than two values on ilk+
let's use switch statemnts when interpreting them.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 93 ++++++++++++++++------
 1 file changed, 70 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 886f3f0d873a..d5ce58c3bc11 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -638,10 +638,17 @@ static void ilk_load_luts(const struct intel_crtc_state *crtc_state)
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
 
-	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
+	switch (crtc_state->gamma_mode) {
+	case GAMMA_MODE_MODE_8BIT:
 		ilk_load_lut_8(crtc, gamma_lut);
-	else
+		break;
+	case GAMMA_MODE_MODE_10BIT:
 		ilk_load_lut_10(crtc, gamma_lut);
+		break;
+	default:
+		MISSING_CASE(crtc_state->gamma_mode);
+		break;
+	}
 }
 
 static int ivb_lut_10_size(u32 prec_index)
@@ -745,21 +752,27 @@ static void ivb_load_luts(const struct intel_crtc_state *crtc_state)
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
 	const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
+	const struct drm_property_blob *blob = gamma_lut ?: degamma_lut;
 
-	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
-		ilk_load_lut_8(crtc, gamma_lut);
-	} else if (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) {
+	switch (crtc_state->gamma_mode) {
+	case GAMMA_MODE_MODE_8BIT:
+		ilk_load_lut_8(crtc, blob);
+		break;
+	case GAMMA_MODE_MODE_SPLIT:
 		ivb_load_lut_10(crtc, degamma_lut, PAL_PREC_SPLIT_MODE |
 				PAL_PREC_INDEX_VALUE(0));
 		ivb_load_lut_ext_max(crtc_state);
 		ivb_load_lut_10(crtc, gamma_lut, PAL_PREC_SPLIT_MODE |
 				PAL_PREC_INDEX_VALUE(512));
-	} else {
-		const struct drm_property_blob *blob = gamma_lut ?: degamma_lut;
-
+		break;
+	case GAMMA_MODE_MODE_10BIT:
 		ivb_load_lut_10(crtc, blob,
 				PAL_PREC_INDEX_VALUE(0));
 		ivb_load_lut_ext_max(crtc_state);
+		break;
+	default:
+		MISSING_CASE(crtc_state->gamma_mode);
+		break;
 	}
 }
 
@@ -768,21 +781,27 @@ static void bdw_load_luts(const struct intel_crtc_state *crtc_state)
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
 	const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
+	const struct drm_property_blob *blob = gamma_lut ?: degamma_lut;
 
-	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
-		ilk_load_lut_8(crtc, gamma_lut);
-	} else if (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) {
+	switch (crtc_state->gamma_mode) {
+	case GAMMA_MODE_MODE_8BIT:
+		ilk_load_lut_8(crtc, blob);
+		break;
+	case GAMMA_MODE_MODE_SPLIT:
 		bdw_load_lut_10(crtc, degamma_lut, PAL_PREC_SPLIT_MODE |
 				PAL_PREC_INDEX_VALUE(0));
 		ivb_load_lut_ext_max(crtc_state);
 		bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_SPLIT_MODE |
 				PAL_PREC_INDEX_VALUE(512));
-	} else {
-		const struct drm_property_blob *blob = gamma_lut ?: degamma_lut;
-
+		break;
+	case GAMMA_MODE_MODE_10BIT:
 		bdw_load_lut_10(crtc, blob,
 				PAL_PREC_INDEX_VALUE(0));
 		ivb_load_lut_ext_max(crtc_state);
+		break;
+	default:
+		MISSING_CASE(crtc_state->gamma_mode);
+		break;
 	}
 }
 
@@ -875,11 +894,17 @@ static void glk_load_luts(const struct intel_crtc_state *crtc_state)
 	else
 		glk_load_degamma_lut_linear(crtc_state);
 
-	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
+	switch (crtc_state->gamma_mode) {
+	case GAMMA_MODE_MODE_8BIT:
 		ilk_load_lut_8(crtc, gamma_lut);
-	} else {
+		break;
+	case GAMMA_MODE_MODE_10BIT:
 		bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0));
 		ivb_load_lut_ext_max(crtc_state);
+		break;
+	default:
+		MISSING_CASE(crtc_state->gamma_mode);
+		break;
 	}
 }
 
@@ -1011,9 +1036,13 @@ static void icl_load_luts(const struct intel_crtc_state *crtc_state)
 		icl_program_gamma_superfine_segment(crtc_state);
 		icl_program_gamma_multi_segment(crtc_state);
 		break;
-	default:
+	case GAMMA_MODE_MODE_10BIT:
 		bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0));
 		ivb_load_lut_ext_max(crtc_state);
+		break;
+	default:
+		MISSING_CASE(crtc_state->gamma_mode);
+		break;
 	}
 
 	intel_dsb_commit(crtc_state);
@@ -1744,7 +1773,7 @@ bool intel_color_lut_equal(struct drm_property_blob *blob1,
 		break;
 	default:
 		MISSING_CASE(gamma_mode);
-			return false;
+		return false;
 	}
 
 	return true;
@@ -1953,10 +1982,17 @@ static void ilk_read_luts(struct intel_crtc_state *crtc_state)
 	if ((crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0)
 		return;
 
-	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
+	switch (crtc_state->gamma_mode) {
+	case GAMMA_MODE_MODE_8BIT:
 		crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc);
-	else
+		break;
+	case GAMMA_MODE_MODE_10BIT:
 		crtc_state->hw.gamma_lut = ilk_read_lut_10(crtc);
+		break;
+	default:
+		MISSING_CASE(crtc_state->gamma_mode);
+		break;
+	}
 }
 
 /*
@@ -2149,10 +2185,17 @@ static void glk_read_luts(struct intel_crtc_state *crtc_state)
 	if (!crtc_state->gamma_enable)
 		return;
 
-	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
+	switch (crtc_state->gamma_mode) {
+	case GAMMA_MODE_MODE_8BIT:
 		crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc);
-	else
+		break;
+	case GAMMA_MODE_MODE_10BIT:
 		crtc_state->hw.gamma_lut = bdw_read_lut_10(crtc, PAL_PREC_INDEX_VALUE(0));
+		break;
+	default:
+		MISSING_CASE(crtc_state->gamma_mode);
+		break;
+	}
 }
 
 static struct drm_property_blob *
@@ -2207,11 +2250,15 @@ static void icl_read_luts(struct intel_crtc_state *crtc_state)
 	case GAMMA_MODE_MODE_8BIT:
 		crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc);
 		break;
+	case GAMMA_MODE_MODE_10BIT:
+		crtc_state->hw.gamma_lut = bdw_read_lut_10(crtc, PAL_PREC_INDEX_VALUE(0));
+		break;
 	case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
 		crtc_state->hw.gamma_lut = icl_read_lut_multi_segment(crtc);
 		break;
 	default:
-		crtc_state->hw.gamma_lut = bdw_read_lut_10(crtc, PAL_PREC_INDEX_VALUE(0));
+		MISSING_CASE(crtc_state->gamma_mode);
+		break;
 	}
 }
 
-- 
2.26.2

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  parent reply	other threads:[~2020-07-17 21:14 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-17 21:13 [Intel-gfx] [PATCH 00/20] drm/i915: Finish (de)gamma readout Ville Syrjala
2020-07-17 21:13 ` [Intel-gfx] [PATCH 01/20] drm/i915: Fix state checker hw.active/hw.enable readout Ville Syrjala
2020-09-17 19:20   ` Shankar, Uma
2020-07-17 21:13 ` [Intel-gfx] [PATCH 02/20] drm/i915: Move MST master transcoder dump earlier Ville Syrjala
2020-09-17 19:24   ` Shankar, Uma
2020-07-17 21:13 ` [Intel-gfx] [PATCH 03/20] drm/i915: Include the LUT sizes in the state dump Ville Syrjala
2020-09-17 19:27   ` Shankar, Uma
2020-07-17 21:13 ` [Intel-gfx] [PATCH 04/20] drm/i915: s/glk_read_lut_10/bdw_read_lut_10/ Ville Syrjala
2020-09-17 19:29   ` Shankar, Uma
2020-07-17 21:13 ` [Intel-gfx] [PATCH 05/20] drm/i915: Reset glk degamma index after programming/readout Ville Syrjala
2020-09-17 19:39   ` Shankar, Uma
2020-07-17 21:13 ` [Intel-gfx] [PATCH 06/20] drm/i915: Shuffle chv_cgm_gamma_pack() around a bit Ville Syrjala
2020-09-17 19:42   ` Shankar, Uma
2020-07-17 21:13 ` [Intel-gfx] [PATCH 07/20] drm/i915: Relocate CHV CGM gamma masks Ville Syrjala
2020-09-17 19:46   ` Shankar, Uma
2020-07-17 21:13 ` [Intel-gfx] [PATCH 08/20] drm/i915: Add glk+ degamma readout Ville Syrjala
2020-09-17 19:58   ` Shankar, Uma
2020-07-17 21:13 ` [Intel-gfx] [PATCH 09/20] drm/i915: Read out CHV CGM degamma Ville Syrjala
2020-09-17 20:06   ` Shankar, Uma
2020-07-17 21:13 ` [Intel-gfx] [PATCH 10/20] drm/i915: Add gamma/degamma readout for bdw+ Ville Syrjala
2020-09-17 20:15   ` Shankar, Uma
2020-07-17 21:13 ` [Intel-gfx] [PATCH 11/20] drm/i915: Do degamma+gamma readout in bdw+ split gamma mode Ville Syrjala
2020-09-17 20:40   ` Shankar, Uma
2020-07-17 21:13 ` [Intel-gfx] [PATCH 12/20] drm/i915: Polish bdw_read_lut_10() a bit Ville Syrjala
2020-09-17 20:43   ` Shankar, Uma
2020-07-17 21:13 ` [Intel-gfx] [PATCH 13/20] drm/i915: Add gamma/degamm readout for ivb/hsw Ville Syrjala
2020-09-17 20:46   ` Shankar, Uma
2020-07-17 21:13 ` Ville Syrjala [this message]
2020-09-17 20:52   ` [Intel-gfx] [PATCH 14/20] drm/i915: Replace some gamma_mode ifs with switches Shankar, Uma
2020-07-17 21:13 ` [Intel-gfx] [PATCH 15/20] drm/i915: Make ilk_load_luts() deal with degamma Ville Syrjala
2020-09-17 20:56   ` Shankar, Uma
2020-07-17 21:13 ` [Intel-gfx] [PATCH 16/20] drm/i915: Make ilk_read_luts() capable of degamma readout Ville Syrjala
2020-09-17 20:58   ` Shankar, Uma
2020-07-17 21:13 ` [Intel-gfx] [PATCH 17/20] drm/i915: Make .read_luts() mandatory Ville Syrjala
2020-09-17 21:00   ` Shankar, Uma
2020-07-17 21:13 ` [Intel-gfx] [PATCH 18/20] drm/i915: Extract ilk_crtc_has_gamma() & co Ville Syrjala
2020-09-17 21:03   ` Shankar, Uma
2020-07-17 21:13 ` [Intel-gfx] [PATCH 19/20] drm/i915: Complete the gamma/degamma state checking Ville Syrjala
2020-09-17 21:52   ` Shankar, Uma
2020-07-17 21:13 ` [Intel-gfx] [PATCH 20/20] drm/i915: Add 10bit gamma mode for gen2/3 Ville Syrjala
2020-09-21 19:40   ` Shankar, Uma
2020-07-17 21:21 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Finish (de)gamma readout Patchwork
2020-07-17 21:43 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-07-17 22:46 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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