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From: "Shankar, Uma" <uma.shankar@intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH 11/20] drm/i915: Do degamma+gamma readout in bdw+ split gamma mode
Date: Thu, 17 Sep 2020 20:40:30 +0000	[thread overview]
Message-ID: <63c68a36acb1461d824c69601813d064@intel.com> (raw)
In-Reply-To: <20200717211345.26851-12-ville.syrjala@linux.intel.com>



> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Saturday, July 18, 2020 2:44 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 11/20] drm/i915: Do degamma+gamma readout in
> bdw+ split gamma mode
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Read out both gamma and degamma when usng the split gamma mode on

s/usng/using
With this,
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> bdw+. We can't use the auto increment mode to iterate the LUTs since we want
> to read out less entries than what we stuff into the software LUT.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_color.c | 52 +++++++++++++++++++++-
>  1 file changed, 51 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index 5742ac1af862..f34257922e4d 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -1959,6 +1959,46 @@ static void ilk_read_luts(struct intel_crtc_state
> *crtc_state)
>  		crtc_state->hw.gamma_lut = ilk_read_lut_10(crtc);  }
> 
> +/*
> + * IVB/HSW Bspec / PAL_PREC_INDEX:
> + * "Restriction : Index auto increment mode is not
> + *  supported and must not be enabled."
> + */
> +static struct drm_property_blob *ivb_read_lut_10(struct intel_crtc *crtc,
> +						 u32 prec_index)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	int i, hw_lut_size = ivb_lut_10_size(prec_index);
> +	int lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
> +	enum pipe pipe = crtc->pipe;
> +	struct drm_property_blob *blob;
> +	struct drm_color_lut *lut;/
> +
> +	blob = drm_property_create_blob(&dev_priv->drm,
> +					sizeof(struct drm_color_lut) * lut_size,
> +					NULL);
> +	if (IS_ERR(blob))
> +		return NULL;
> +
> +	lut = blob->data;
> +
> +	for (i = 0; i < lut_size; i++) {
> +		/* We discard half the user entries in split gamma mode */
> +		int index = DIV_ROUND_UP(i * (hw_lut_size - 1), lut_size - 1);
> +		u32 val;
> +
> +		intel_de_write(dev_priv, PREC_PAL_INDEX(pipe),
> +			       prec_index + index);
> +		val = intel_de_read(dev_priv, PREC_PAL_DATA(pipe));
> +
> +		ilk_lut_10_pack(&lut[i], val);
> +	}
> +
> +	intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), 0);
> +
> +	return blob;
> +}
> +
>  /* On BDW+ the index auto increment mode actually works */  static struct
> drm_property_blob *bdw_read_lut_10(struct intel_crtc *crtc,
>  						 u32 prec_index)
> @@ -2006,7 +2046,17 @@ static void bdw_read_luts(struct intel_crtc_state
> *crtc_state)
>  		*blob = ilk_read_lut_8(crtc);
>  		break;
>  	case GAMMA_MODE_MODE_SPLIT:
> -		/* FIXME */
> +		/*
> +		 * Can't use bdw_read_lut_10() with its auto-increment
> +		 * mode here since we want to generate 1024 entry
> +		 * software LUTs from the 512 entry hardware LUTs.
> +		 */
> +		crtc_state->hw.degamma_lut =
> +			ivb_read_lut_10(crtc, PAL_PREC_SPLIT_MODE |
> +					PAL_PREC_INDEX_VALUE(0));
> +		crtc_state->hw.gamma_lut =
> +			ivb_read_lut_10(crtc, PAL_PREC_SPLIT_MODE |
> +					PAL_PREC_INDEX_VALUE(512));
>  		break;
>  	case GAMMA_MODE_MODE_10BIT:
>  		*blob = bdw_read_lut_10(crtc, PAL_PREC_INDEX_VALUE(0));
> --
> 2.26.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
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  reply	other threads:[~2020-09-17 20:40 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-17 21:13 [Intel-gfx] [PATCH 00/20] drm/i915: Finish (de)gamma readout Ville Syrjala
2020-07-17 21:13 ` [Intel-gfx] [PATCH 01/20] drm/i915: Fix state checker hw.active/hw.enable readout Ville Syrjala
2020-09-17 19:20   ` Shankar, Uma
2020-07-17 21:13 ` [Intel-gfx] [PATCH 02/20] drm/i915: Move MST master transcoder dump earlier Ville Syrjala
2020-09-17 19:24   ` Shankar, Uma
2020-07-17 21:13 ` [Intel-gfx] [PATCH 03/20] drm/i915: Include the LUT sizes in the state dump Ville Syrjala
2020-09-17 19:27   ` Shankar, Uma
2020-07-17 21:13 ` [Intel-gfx] [PATCH 04/20] drm/i915: s/glk_read_lut_10/bdw_read_lut_10/ Ville Syrjala
2020-09-17 19:29   ` Shankar, Uma
2020-07-17 21:13 ` [Intel-gfx] [PATCH 05/20] drm/i915: Reset glk degamma index after programming/readout Ville Syrjala
2020-09-17 19:39   ` Shankar, Uma
2020-07-17 21:13 ` [Intel-gfx] [PATCH 06/20] drm/i915: Shuffle chv_cgm_gamma_pack() around a bit Ville Syrjala
2020-09-17 19:42   ` Shankar, Uma
2020-07-17 21:13 ` [Intel-gfx] [PATCH 07/20] drm/i915: Relocate CHV CGM gamma masks Ville Syrjala
2020-09-17 19:46   ` Shankar, Uma
2020-07-17 21:13 ` [Intel-gfx] [PATCH 08/20] drm/i915: Add glk+ degamma readout Ville Syrjala
2020-09-17 19:58   ` Shankar, Uma
2020-07-17 21:13 ` [Intel-gfx] [PATCH 09/20] drm/i915: Read out CHV CGM degamma Ville Syrjala
2020-09-17 20:06   ` Shankar, Uma
2020-07-17 21:13 ` [Intel-gfx] [PATCH 10/20] drm/i915: Add gamma/degamma readout for bdw+ Ville Syrjala
2020-09-17 20:15   ` Shankar, Uma
2020-07-17 21:13 ` [Intel-gfx] [PATCH 11/20] drm/i915: Do degamma+gamma readout in bdw+ split gamma mode Ville Syrjala
2020-09-17 20:40   ` Shankar, Uma [this message]
2020-07-17 21:13 ` [Intel-gfx] [PATCH 12/20] drm/i915: Polish bdw_read_lut_10() a bit Ville Syrjala
2020-09-17 20:43   ` Shankar, Uma
2020-07-17 21:13 ` [Intel-gfx] [PATCH 13/20] drm/i915: Add gamma/degamm readout for ivb/hsw Ville Syrjala
2020-09-17 20:46   ` Shankar, Uma
2020-07-17 21:13 ` [Intel-gfx] [PATCH 14/20] drm/i915: Replace some gamma_mode ifs with switches Ville Syrjala
2020-09-17 20:52   ` Shankar, Uma
2020-07-17 21:13 ` [Intel-gfx] [PATCH 15/20] drm/i915: Make ilk_load_luts() deal with degamma Ville Syrjala
2020-09-17 20:56   ` Shankar, Uma
2020-07-17 21:13 ` [Intel-gfx] [PATCH 16/20] drm/i915: Make ilk_read_luts() capable of degamma readout Ville Syrjala
2020-09-17 20:58   ` Shankar, Uma
2020-07-17 21:13 ` [Intel-gfx] [PATCH 17/20] drm/i915: Make .read_luts() mandatory Ville Syrjala
2020-09-17 21:00   ` Shankar, Uma
2020-07-17 21:13 ` [Intel-gfx] [PATCH 18/20] drm/i915: Extract ilk_crtc_has_gamma() & co Ville Syrjala
2020-09-17 21:03   ` Shankar, Uma
2020-07-17 21:13 ` [Intel-gfx] [PATCH 19/20] drm/i915: Complete the gamma/degamma state checking Ville Syrjala
2020-09-17 21:52   ` Shankar, Uma
2020-07-17 21:13 ` [Intel-gfx] [PATCH 20/20] drm/i915: Add 10bit gamma mode for gen2/3 Ville Syrjala
2020-09-21 19:40   ` Shankar, Uma
2020-07-17 21:21 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Finish (de)gamma readout Patchwork
2020-07-17 21:43 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-07-17 22:46 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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