[PATCH 0/7] Add C66x & C71x DSP nodes on J721E SoCs

[PATCH 0/7] Add C66x & C71x DSP nodes on J721E SoCs

[Suman Anna]

Hi Nishanth, Tero,

The following series adds the base dt nodes for the 2 C66x and 1 C71x
DSP remote processors present in MAIN domain on J721E SoCs, and the
required nodes to boot these successfully on J721E EVM board. The DSP
remoteproc driver and bindings have been merged into 5.9-rc1. The
series uses previously accepted mailbox nodes.

I have validated the IPC functionality using the latest System Firmware.
The series itself is not directly influenced by the SYSFW version, only
the referenced mailbox interrupts properties get modified as part of
the ABI 3.0 changes. These are already handled in a pending pull-request
for 5.9-rc2 [1].

regards
Suman

[1] https://lore.kernel.org/patchwork/patch/1290231/

Suman Anna (7):
  arm64: dts: ti: k3-j721e-main: Add C66x DSP nodes
  arm64: dts: ti: k3-j721e-common-proc-board: Add mailboxes to C66x DSPs
  arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for C66
    DSPs
  arm64: dts: ti: k3-j721e-main: Add C71x DSP node
  arm64: dts: ti: k3-j721e-common-proc-board: Add mailboxes to C71x DSP
  arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for
    C71x DSP
  arm64: dts: ti: k3-j721e-som-p0: Reserve memory for IPC between RTOS
    cores

 .../dts/ti/k3-j721e-common-proc-board.dts     | 12 ++++
 arch/arm64/boot/dts/ti/k3-j721e-main.dtsi     | 38 +++++++++++++
 arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi   | 57 +++++++++++++++++++
 3 files changed, 107 insertions(+)

-- 
2.28.0

[PATCH 0/7] Add C66x & C71x DSP nodes on J721E SoCs

[Suman Anna]

Hi Nishanth, Tero,

The following series adds the base dt nodes for the 2 C66x and 1 C71x
DSP remote processors present in MAIN domain on J721E SoCs, and the
required nodes to boot these successfully on J721E EVM board. The DSP
remoteproc driver and bindings have been merged into 5.9-rc1. The
series uses previously accepted mailbox nodes.

I have validated the IPC functionality using the latest System Firmware.
The series itself is not directly influenced by the SYSFW version, only
the referenced mailbox interrupts properties get modified as part of
the ABI 3.0 changes. These are already handled in a pending pull-request
for 5.9-rc2 [1].

regards
Suman

[1] https://lore.kernel.org/patchwork/patch/1290231/

Suman Anna (7):
  arm64: dts: ti: k3-j721e-main: Add C66x DSP nodes
  arm64: dts: ti: k3-j721e-common-proc-board: Add mailboxes to C66x DSPs
  arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for C66
    DSPs
  arm64: dts: ti: k3-j721e-main: Add C71x DSP node
  arm64: dts: ti: k3-j721e-common-proc-board: Add mailboxes to C71x DSP
  arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for
    C71x DSP
  arm64: dts: ti: k3-j721e-som-p0: Reserve memory for IPC between RTOS
    cores

 .../dts/ti/k3-j721e-common-proc-board.dts     | 12 ++++
 arch/arm64/boot/dts/ti/k3-j721e-main.dtsi     | 38 +++++++++++++
 arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi   | 57 +++++++++++++++++++
 3 files changed, 107 insertions(+)

-- 
2.28.0


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[PATCH 1/7] arm64: dts: ti: k3-j721e-main: Add C66x DSP nodes

[Suman Anna]

The J721E SoCs have two TMS320C66x DSP Core Subsystems (C66x CorePacs)
in the MAIN voltage domain, each with a C66x Fixed/Floating-Point DSP
Core, and 32 KB of L1P & L1D configurable SRAMs/Cache and an additional
288 KB of L2 configurable SRAM/Cache. These subsystems do not have
an MMU but contain a Region Address Translator (RAT) sub-module for
translating 32-bit processor addresses into larger bus addresses.
The inter-processor communication between the main A72 cores and
these processors is achieved through shared memory and Mailboxes.
Add the DT nodes for these DSP processor sub-systems in the common
k3-j721e-main.dtsi file.

The following firmware names are used by default for these cores, and
can be overridden in a board dts file if desired:
    C66x_0 DSP: j7-c66_0-fw
    C66x_1 DSP: j7-c66_1-fw

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 26 +++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index 12ceea9b3c9a..46cde2677e17 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -1326,4 +1326,30 @@ watchdog1: watchdog@2210000 {
 		assigned-clocks = <&k3_clks 253 1>;
 		assigned-clock-parents = <&k3_clks 253 5>;
 	};
+
+	c66_0: dsp@4d80800000 {
+		compatible = "ti,j721e-c66-dsp";
+		reg = <0x4d 0x80800000 0x00 0x00048000>,
+		      <0x4d 0x80e00000 0x00 0x00008000>,
+		      <0x4d 0x80f00000 0x00 0x00008000>;
+		reg-names = "l2sram", "l1pram", "l1dram";
+		ti,sci = <&dmsc>;
+		ti,sci-dev-id = <142>;
+		ti,sci-proc-ids = <0x03 0xff>;
+		resets = <&k3_reset 142 1>;
+		firmware-name = "j7-c66_0-fw";
+	};
+
+	c66_1: dsp@4d81800000 {
+		compatible = "ti,j721e-c66-dsp";
+		reg = <0x4d 0x81800000 0x00 0x00048000>,
+		      <0x4d 0x81e00000 0x00 0x00008000>,
+		      <0x4d 0x81f00000 0x00 0x00008000>;
+		reg-names = "l2sram", "l1pram", "l1dram";
+		ti,sci = <&dmsc>;
+		ti,sci-dev-id = <143>;
+		ti,sci-proc-ids = <0x04 0xff>;
+		resets = <&k3_reset 143 1>;
+		firmware-name = "j7-c66_1-fw";
+	};
 };
-- 
2.28.0

[PATCH 1/7] arm64: dts: ti: k3-j721e-main: Add C66x DSP nodes

[Suman Anna]

The J721E SoCs have two TMS320C66x DSP Core Subsystems (C66x CorePacs)
in the MAIN voltage domain, each with a C66x Fixed/Floating-Point DSP
Core, and 32 KB of L1P & L1D configurable SRAMs/Cache and an additional
288 KB of L2 configurable SRAM/Cache. These subsystems do not have
an MMU but contain a Region Address Translator (RAT) sub-module for
translating 32-bit processor addresses into larger bus addresses.
The inter-processor communication between the main A72 cores and
these processors is achieved through shared memory and Mailboxes.
Add the DT nodes for these DSP processor sub-systems in the common
k3-j721e-main.dtsi file.

The following firmware names are used by default for these cores, and
can be overridden in a board dts file if desired:
    C66x_0 DSP: j7-c66_0-fw
    C66x_1 DSP: j7-c66_1-fw

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 26 +++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index 12ceea9b3c9a..46cde2677e17 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -1326,4 +1326,30 @@ watchdog1: watchdog@2210000 {
 		assigned-clocks = <&k3_clks 253 1>;
 		assigned-clock-parents = <&k3_clks 253 5>;
 	};
+
+	c66_0: dsp@4d80800000 {
+		compatible = "ti,j721e-c66-dsp";
+		reg = <0x4d 0x80800000 0x00 0x00048000>,
+		      <0x4d 0x80e00000 0x00 0x00008000>,
+		      <0x4d 0x80f00000 0x00 0x00008000>;
+		reg-names = "l2sram", "l1pram", "l1dram";
+		ti,sci = <&dmsc>;
+		ti,sci-dev-id = <142>;
+		ti,sci-proc-ids = <0x03 0xff>;
+		resets = <&k3_reset 142 1>;
+		firmware-name = "j7-c66_0-fw";
+	};
+
+	c66_1: dsp@4d81800000 {
+		compatible = "ti,j721e-c66-dsp";
+		reg = <0x4d 0x81800000 0x00 0x00048000>,
+		      <0x4d 0x81e00000 0x00 0x00008000>,
+		      <0x4d 0x81f00000 0x00 0x00008000>;
+		reg-names = "l2sram", "l1pram", "l1dram";
+		ti,sci = <&dmsc>;
+		ti,sci-dev-id = <143>;
+		ti,sci-proc-ids = <0x04 0xff>;
+		resets = <&k3_reset 143 1>;
+		firmware-name = "j7-c66_1-fw";
+	};
 };
-- 
2.28.0


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[PATCH 2/7] arm64: dts: ti: k3-j721e-common-proc-board: Add mailboxes to C66x DSPs

[Suman Anna]

Add the required 'mboxes' property to both the C66x DSP processors on the
TI J721E common processor board. The mailboxes and some shared memory
are required for running the Remote Processor Messaging (RPMsg) stack
between the host processor and each of the R5Fs. The chosen sub-mailboxes
match the values used in the current firmware images. This can be changed,
if needed, as per the system integration needs after making appropriate
changes on the firmware side as well.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index e8fc01d97ada..ff541dc09eca 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -379,6 +379,14 @@ &mailbox0_cluster11 {
 	status = "disabled";
 };
 
+&c66_0 {
+	mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
+};
+
+&c66_1 {
+	mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
+};
+
 &main_sdhci0 {
 	/* eMMC */
 	non-removable;
-- 
2.28.0

[PATCH 2/7] arm64: dts: ti: k3-j721e-common-proc-board: Add mailboxes to C66x DSPs

[Suman Anna]

Add the required 'mboxes' property to both the C66x DSP processors on the
TI J721E common processor board. The mailboxes and some shared memory
are required for running the Remote Processor Messaging (RPMsg) stack
between the host processor and each of the R5Fs. The chosen sub-mailboxes
match the values used in the current firmware images. This can be changed,
if needed, as per the system integration needs after making appropriate
changes on the firmware side as well.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index e8fc01d97ada..ff541dc09eca 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -379,6 +379,14 @@ &mailbox0_cluster11 {
 	status = "disabled";
 };
 
+&c66_0 {
+	mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
+};
+
+&c66_1 {
+	mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
+};
+
 &main_sdhci0 {
 	/* eMMC */
 	non-removable;
-- 
2.28.0


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Re: [PATCH 2/7] arm64: dts: ti: k3-j721e-common-proc-board: Add mailboxes to C66x DSPs

[Nishanth Menon]

On 20:03-20200819, Suman Anna wrote:
> Add the required 'mboxes' property to both the C66x DSP processors on the
> TI J721E common processor board. The mailboxes and some shared memory

I am not sure I understand the logic here. The carveout is added to
p0 SOM - and the mbox is added to common_proc_board. I am not sure I
get the difference. The C66x processors are on the SoC, stack is as
follows: - SoC - SoM - Common Proc board

I am just wondering if the carveouts and mbox linkage should be in the
common processor board? if that makes sense at all? I know we already
have other definitions.. Trying to see if we are making it harder to
understand the definition than that is necessary..

> are required for running the Remote Processor Messaging (RPMsg) stack
> between the host processor and each of the R5Fs. The chosen sub-mailboxes
> match the values used in the current firmware images. This can be changed,
> if needed, as per the system integration needs after making appropriate
> changes on the firmware side as well.
> 
> Signed-off-by: Suman Anna <s-anna@ti.com>
> ---
>  arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
> index e8fc01d97ada..ff541dc09eca 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
> @@ -379,6 +379,14 @@ &mailbox0_cluster11 {
>  	status = "disabled";
>  };
>  
> +&c66_0 {
> +	mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
> +};
> +
> +&c66_1 {
> +	mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
> +};
> +
>  &main_sdhci0 {
>  	/* eMMC */
>  	non-removable;
> -- 
> 2.28.0
> 

-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

Re: [PATCH 2/7] arm64: dts: ti: k3-j721e-common-proc-board: Add mailboxes to C66x DSPs

[Nishanth Menon]

On 20:03-20200819, Suman Anna wrote:
> Add the required 'mboxes' property to both the C66x DSP processors on the
> TI J721E common processor board. The mailboxes and some shared memory

I am not sure I understand the logic here. The carveout is added to
p0 SOM - and the mbox is added to common_proc_board. I am not sure I
get the difference. The C66x processors are on the SoC, stack is as
follows: - SoC - SoM - Common Proc board

I am just wondering if the carveouts and mbox linkage should be in the
common processor board? if that makes sense at all? I know we already
have other definitions.. Trying to see if we are making it harder to
understand the definition than that is necessary..

> are required for running the Remote Processor Messaging (RPMsg) stack
> between the host processor and each of the R5Fs. The chosen sub-mailboxes
> match the values used in the current firmware images. This can be changed,
> if needed, as per the system integration needs after making appropriate
> changes on the firmware side as well.
> 
> Signed-off-by: Suman Anna <s-anna@ti.com>
> ---
>  arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
> index e8fc01d97ada..ff541dc09eca 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
> @@ -379,6 +379,14 @@ &mailbox0_cluster11 {
>  	status = "disabled";
>  };
>  
> +&c66_0 {
> +	mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
> +};
> +
> +&c66_1 {
> +	mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
> +};
> +
>  &main_sdhci0 {
>  	/* eMMC */
>  	non-removable;
> -- 
> 2.28.0
> 

-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

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Re: [PATCH 2/7] arm64: dts: ti: k3-j721e-common-proc-board: Add mailboxes to C66x DSPs

[Suman Anna]

Hi Nishanth,

On 8/20/20 6:42 AM, Nishanth Menon wrote:
> On 20:03-20200819, Suman Anna wrote:
>> Add the required 'mboxes' property to both the C66x DSP processors on the
>> TI J721E common processor board. The mailboxes and some shared memory
> 
> I am not sure I understand the logic here. The carveout is added to
> p0 SOM - and the mbox is added to common_proc_board. I am not sure I
> get the difference. The C66x processors are on the SoC, stack is as
> follows: - SoC - SoM - Common Proc board
> 
> I am just wondering if the carveouts and mbox linkage should be in the
> common processor board? if that makes sense at all? I know we already
> have other definitions.. Trying to see if we are making it harder to
> understand the definition than that is necessary..

In general, I consider these as stuff that needs to be added to the board dts
files. You will see that this is what I have followed on all the TI
AM57xx/DRA7xx boards. For J721E, we have a weird organization as the memory
node, typically a board property, is defined in the som dtsi file, so the
reserved memory nodes are also added in the som dtsi file. The convention I
followed in general is to have the reserved-memory and memory nodes together.

If you think the mailbox nodes should be moved into the SoM dts file, I could do
it as a follow-on cleanup series, but would wait for the ABI 3.0 changes to be
merged first.

regards
Suman

> 
>> are required for running the Remote Processor Messaging (RPMsg) stack
>> between the host processor and each of the R5Fs. The chosen sub-mailboxes
>> match the values used in the current firmware images. This can be changed,
>> if needed, as per the system integration needs after making appropriate
>> changes on the firmware side as well.
>>
>> Signed-off-by: Suman Anna <s-anna@ti.com>
>> ---
>>  arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 8 ++++++++
>>  1 file changed, 8 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
>> index e8fc01d97ada..ff541dc09eca 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
>> @@ -379,6 +379,14 @@ &mailbox0_cluster11 {
>>  	status = "disabled";
>>  };
>>  
>> +&c66_0 {
>> +	mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
>> +};
>> +
>> +&c66_1 {
>> +	mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
>> +};
>> +
>>  &main_sdhci0 {
>>  	/* eMMC */
>>  	non-removable;
>> -- 
>> 2.28.0
>>
> 

Re: [PATCH 2/7] arm64: dts: ti: k3-j721e-common-proc-board: Add mailboxes to C66x DSPs

[Suman Anna]

Hi Nishanth,

On 8/20/20 6:42 AM, Nishanth Menon wrote:
> On 20:03-20200819, Suman Anna wrote:
>> Add the required 'mboxes' property to both the C66x DSP processors on the
>> TI J721E common processor board. The mailboxes and some shared memory
> 
> I am not sure I understand the logic here. The carveout is added to
> p0 SOM - and the mbox is added to common_proc_board. I am not sure I
> get the difference. The C66x processors are on the SoC, stack is as
> follows: - SoC - SoM - Common Proc board
> 
> I am just wondering if the carveouts and mbox linkage should be in the
> common processor board? if that makes sense at all? I know we already
> have other definitions.. Trying to see if we are making it harder to
> understand the definition than that is necessary..

In general, I consider these as stuff that needs to be added to the board dts
files. You will see that this is what I have followed on all the TI
AM57xx/DRA7xx boards. For J721E, we have a weird organization as the memory
node, typically a board property, is defined in the som dtsi file, so the
reserved memory nodes are also added in the som dtsi file. The convention I
followed in general is to have the reserved-memory and memory nodes together.

If you think the mailbox nodes should be moved into the SoM dts file, I could do
it as a follow-on cleanup series, but would wait for the ABI 3.0 changes to be
merged first.

regards
Suman

> 
>> are required for running the Remote Processor Messaging (RPMsg) stack
>> between the host processor and each of the R5Fs. The chosen sub-mailboxes
>> match the values used in the current firmware images. This can be changed,
>> if needed, as per the system integration needs after making appropriate
>> changes on the firmware side as well.
>>
>> Signed-off-by: Suman Anna <s-anna@ti.com>
>> ---
>>  arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 8 ++++++++
>>  1 file changed, 8 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
>> index e8fc01d97ada..ff541dc09eca 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
>> @@ -379,6 +379,14 @@ &mailbox0_cluster11 {
>>  	status = "disabled";
>>  };
>>  
>> +&c66_0 {
>> +	mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
>> +};
>> +
>> +&c66_1 {
>> +	mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
>> +};
>> +
>>  &main_sdhci0 {
>>  	/* eMMC */
>>  	non-removable;
>> -- 
>> 2.28.0
>>
> 


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Re: [PATCH 2/7] arm64: dts: ti: k3-j721e-common-proc-board: Add mailboxes to C66x DSPs

[Nishanth Menon]

On 08:25-20200820, Suman Anna wrote:
[...]
> > I am just wondering if the carveouts and mbox linkage should be in the
> > common processor board? if that makes sense at all? I know we already
> > have other definitions.. Trying to see if we are making it harder to
> > understand the definition than that is necessary..
>
> In general, I consider these as stuff that needs to be added to the board dts
> files. You will see that this is what I have followed on all the TI
> AM57xx/DRA7xx boards. For J721E, we have a weird organization as the memory
> node, typically a board property, is defined in the som dtsi file, so the
> reserved memory nodes are also added in the som dtsi file. The convention I
> followed in general is to have the reserved-memory and memory nodes together.
>
> If you think the mailbox nodes should be moved into the SoM dts file, I could do

I think that might make more sense and less confusing. I'd rather
leave the processor board dts for more signal and interface hookup
related topics as it is done right now. if we do endup with too many
SoM duplication, then we should consider it's own dtsi

> it as a follow-on cleanup series, but would wait for the ABI 3.0 changes to be
> merged first.

Of course. We are expecting this to be part of rc2, please rebase and
post once the tag is out. next-20200820 has it already, if you want a
pre-look.

-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

Re: [PATCH 2/7] arm64: dts: ti: k3-j721e-common-proc-board: Add mailboxes to C66x DSPs

[Nishanth Menon]

On 08:25-20200820, Suman Anna wrote:
[...]
> > I am just wondering if the carveouts and mbox linkage should be in the
> > common processor board? if that makes sense at all? I know we already
> > have other definitions.. Trying to see if we are making it harder to
> > understand the definition than that is necessary..
>
> In general, I consider these as stuff that needs to be added to the board dts
> files. You will see that this is what I have followed on all the TI
> AM57xx/DRA7xx boards. For J721E, we have a weird organization as the memory
> node, typically a board property, is defined in the som dtsi file, so the
> reserved memory nodes are also added in the som dtsi file. The convention I
> followed in general is to have the reserved-memory and memory nodes together.
>
> If you think the mailbox nodes should be moved into the SoM dts file, I could do

I think that might make more sense and less confusing. I'd rather
leave the processor board dts for more signal and interface hookup
related topics as it is done right now. if we do endup with too many
SoM duplication, then we should consider it's own dtsi

> it as a follow-on cleanup series, but would wait for the ABI 3.0 changes to be
> merged first.

Of course. We are expecting this to be part of rc2, please rebase and
post once the tag is out. next-20200820 has it already, if you want a
pre-look.

-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

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Re: [PATCH 2/7] arm64: dts: ti: k3-j721e-common-proc-board: Add mailboxes to C66x DSPs

[Suman Anna]

Hi Nishanth,

On 8/20/20 2:03 PM, Nishanth Menon wrote:
> On 08:25-20200820, Suman Anna wrote:
> [...]
>>> I am just wondering if the carveouts and mbox linkage should be in the
>>> common processor board? if that makes sense at all? I know we already
>>> have other definitions.. Trying to see if we are making it harder to
>>> understand the definition than that is necessary..
>>
>> In general, I consider these as stuff that needs to be added to the board dts
>> files. You will see that this is what I have followed on all the TI
>> AM57xx/DRA7xx boards. For J721E, we have a weird organization as the memory
>> node, typically a board property, is defined in the som dtsi file, so the
>> reserved memory nodes are also added in the som dtsi file. The convention I
>> followed in general is to have the reserved-memory and memory nodes together.
>>
>> If you think the mailbox nodes should be moved into the SoM dts file, I could do
> 
> I think that might make more sense and less confusing. I'd rather
> leave the processor board dts for more signal and interface hookup
> related topics as it is done right now. if we do endup with too many
> SoM duplication, then we should consider it's own dtsi
> 
>> it as a follow-on cleanup series, but would wait for the ABI 3.0 changes to be
>> merged first.
> 
> Of course. We are expecting this to be part of rc2, please rebase and
> post once the tag is out. next-20200820 has it already, if you want a
> pre-look.
> 

So, the ABI 3.0 changes are not part of -rc2, so, I cannot move the unrelated
mailbox nodes/cleanup without conflicting with that series. Are you ok if I just
move these nodes into the SoM dtsi file?

regards
Suman

Re: [PATCH 2/7] arm64: dts: ti: k3-j721e-common-proc-board: Add mailboxes to C66x DSPs

[Suman Anna]

Hi Nishanth,

On 8/20/20 2:03 PM, Nishanth Menon wrote:
> On 08:25-20200820, Suman Anna wrote:
> [...]
>>> I am just wondering if the carveouts and mbox linkage should be in the
>>> common processor board? if that makes sense at all? I know we already
>>> have other definitions.. Trying to see if we are making it harder to
>>> understand the definition than that is necessary..
>>
>> In general, I consider these as stuff that needs to be added to the board dts
>> files. You will see that this is what I have followed on all the TI
>> AM57xx/DRA7xx boards. For J721E, we have a weird organization as the memory
>> node, typically a board property, is defined in the som dtsi file, so the
>> reserved memory nodes are also added in the som dtsi file. The convention I
>> followed in general is to have the reserved-memory and memory nodes together.
>>
>> If you think the mailbox nodes should be moved into the SoM dts file, I could do
> 
> I think that might make more sense and less confusing. I'd rather
> leave the processor board dts for more signal and interface hookup
> related topics as it is done right now. if we do endup with too many
> SoM duplication, then we should consider it's own dtsi
> 
>> it as a follow-on cleanup series, but would wait for the ABI 3.0 changes to be
>> merged first.
> 
> Of course. We are expecting this to be part of rc2, please rebase and
> post once the tag is out. next-20200820 has it already, if you want a
> pre-look.
> 

So, the ABI 3.0 changes are not part of -rc2, so, I cannot move the unrelated
mailbox nodes/cleanup without conflicting with that series. Are you ok if I just
move these nodes into the SoM dtsi file?

regards
Suman



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Re: [PATCH 2/7] arm64: dts: ti: k3-j721e-common-proc-board: Add mailboxes to C66x DSPs

[Nishanth Menon]

On 17:00-20200824, Suman Anna wrote:
> Hi Nishanth,
> 
> On 8/20/20 2:03 PM, Nishanth Menon wrote:
> > On 08:25-20200820, Suman Anna wrote:
> > [...]
> >>> I am just wondering if the carveouts and mbox linkage should be in the
> >>> common processor board? if that makes sense at all? I know we already
> >>> have other definitions.. Trying to see if we are making it harder to
> >>> understand the definition than that is necessary..
> >>
> >> In general, I consider these as stuff that needs to be added to the board dts
> >> files. You will see that this is what I have followed on all the TI
> >> AM57xx/DRA7xx boards. For J721E, we have a weird organization as the memory
> >> node, typically a board property, is defined in the som dtsi file, so the
> >> reserved memory nodes are also added in the som dtsi file. The convention I
> >> followed in general is to have the reserved-memory and memory nodes together.
> >>
> >> If you think the mailbox nodes should be moved into the SoM dts file, I could do
> > 
> > I think that might make more sense and less confusing. I'd rather
> > leave the processor board dts for more signal and interface hookup
> > related topics as it is done right now. if we do endup with too many
> > SoM duplication, then we should consider it's own dtsi
> > 
> >> it as a follow-on cleanup series, but would wait for the ABI 3.0 changes to be
> >> merged first.
> > 
> > Of course. We are expecting this to be part of rc2, please rebase and
> > post once the tag is out. next-20200820 has it already, if you want a
> > pre-look.
> > 
> 
> So, the ABI 3.0 changes are not part of -rc2, so, I cannot move the unrelated
> mailbox nodes/cleanup without conflicting with that series. Are you ok if I just
> move these nodes into the SoM dtsi file?

Lets introduce things properly: First cleanup rather creating a
kludgy intermediate state (half of r5 mbox nodes in proc, half of c6x
node in SoM etc).

-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

Re: [PATCH 2/7] arm64: dts: ti: k3-j721e-common-proc-board: Add mailboxes to C66x DSPs

[Nishanth Menon]

On 17:00-20200824, Suman Anna wrote:
> Hi Nishanth,
> 
> On 8/20/20 2:03 PM, Nishanth Menon wrote:
> > On 08:25-20200820, Suman Anna wrote:
> > [...]
> >>> I am just wondering if the carveouts and mbox linkage should be in the
> >>> common processor board? if that makes sense at all? I know we already
> >>> have other definitions.. Trying to see if we are making it harder to
> >>> understand the definition than that is necessary..
> >>
> >> In general, I consider these as stuff that needs to be added to the board dts
> >> files. You will see that this is what I have followed on all the TI
> >> AM57xx/DRA7xx boards. For J721E, we have a weird organization as the memory
> >> node, typically a board property, is defined in the som dtsi file, so the
> >> reserved memory nodes are also added in the som dtsi file. The convention I
> >> followed in general is to have the reserved-memory and memory nodes together.
> >>
> >> If you think the mailbox nodes should be moved into the SoM dts file, I could do
> > 
> > I think that might make more sense and less confusing. I'd rather
> > leave the processor board dts for more signal and interface hookup
> > related topics as it is done right now. if we do endup with too many
> > SoM duplication, then we should consider it's own dtsi
> > 
> >> it as a follow-on cleanup series, but would wait for the ABI 3.0 changes to be
> >> merged first.
> > 
> > Of course. We are expecting this to be part of rc2, please rebase and
> > post once the tag is out. next-20200820 has it already, if you want a
> > pre-look.
> > 
> 
> So, the ABI 3.0 changes are not part of -rc2, so, I cannot move the unrelated
> mailbox nodes/cleanup without conflicting with that series. Are you ok if I just
> move these nodes into the SoM dtsi file?

Lets introduce things properly: First cleanup rather creating a
kludgy intermediate state (half of r5 mbox nodes in proc, half of c6x
node in SoM etc).

-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

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Re: [PATCH 2/7] arm64: dts: ti: k3-j721e-common-proc-board: Add mailboxes to C66x DSPs

[Suman Anna]

On 8/25/20 5:42 AM, Nishanth Menon wrote:
> On 17:00-20200824, Suman Anna wrote:
>> Hi Nishanth,
>>
>> On 8/20/20 2:03 PM, Nishanth Menon wrote:
>>> On 08:25-20200820, Suman Anna wrote:
>>> [...]
>>>>> I am just wondering if the carveouts and mbox linkage should be in the
>>>>> common processor board? if that makes sense at all? I know we already
>>>>> have other definitions.. Trying to see if we are making it harder to
>>>>> understand the definition than that is necessary..
>>>>
>>>> In general, I consider these as stuff that needs to be added to the board dts
>>>> files. You will see that this is what I have followed on all the TI
>>>> AM57xx/DRA7xx boards. For J721E, we have a weird organization as the memory
>>>> node, typically a board property, is defined in the som dtsi file, so the
>>>> reserved memory nodes are also added in the som dtsi file. The convention I
>>>> followed in general is to have the reserved-memory and memory nodes together.
>>>>
>>>> If you think the mailbox nodes should be moved into the SoM dts file, I could do
>>>
>>> I think that might make more sense and less confusing. I'd rather
>>> leave the processor board dts for more signal and interface hookup
>>> related topics as it is done right now. if we do endup with too many
>>> SoM duplication, then we should consider it's own dtsi
>>>
>>>> it as a follow-on cleanup series, but would wait for the ABI 3.0 changes to be
>>>> merged first.
>>>
>>> Of course. We are expecting this to be part of rc2, please rebase and
>>> post once the tag is out. next-20200820 has it already, if you want a
>>> pre-look.
>>>
>>
>> So, the ABI 3.0 changes are not part of -rc2, so, I cannot move the unrelated
>> mailbox nodes/cleanup without conflicting with that series. Are you ok if I just
>> move these nodes into the SoM dtsi file?
> 
> Lets introduce things properly: First cleanup rather creating a
> kludgy intermediate state (half of r5 mbox nodes in proc, half of c6x
> node in SoM etc).

OK, posted a v2 [1] with the cleanup first. It does create a dependency on the
pending ABI 3.0 PR.

regards
Suman

[1] https://patchwork.kernel.org/cover/11736095/

Re: [PATCH 2/7] arm64: dts: ti: k3-j721e-common-proc-board: Add mailboxes to C66x DSPs

[Suman Anna]

On 8/25/20 5:42 AM, Nishanth Menon wrote:
> On 17:00-20200824, Suman Anna wrote:
>> Hi Nishanth,
>>
>> On 8/20/20 2:03 PM, Nishanth Menon wrote:
>>> On 08:25-20200820, Suman Anna wrote:
>>> [...]
>>>>> I am just wondering if the carveouts and mbox linkage should be in the
>>>>> common processor board? if that makes sense at all? I know we already
>>>>> have other definitions.. Trying to see if we are making it harder to
>>>>> understand the definition than that is necessary..
>>>>
>>>> In general, I consider these as stuff that needs to be added to the board dts
>>>> files. You will see that this is what I have followed on all the TI
>>>> AM57xx/DRA7xx boards. For J721E, we have a weird organization as the memory
>>>> node, typically a board property, is defined in the som dtsi file, so the
>>>> reserved memory nodes are also added in the som dtsi file. The convention I
>>>> followed in general is to have the reserved-memory and memory nodes together.
>>>>
>>>> If you think the mailbox nodes should be moved into the SoM dts file, I could do
>>>
>>> I think that might make more sense and less confusing. I'd rather
>>> leave the processor board dts for more signal and interface hookup
>>> related topics as it is done right now. if we do endup with too many
>>> SoM duplication, then we should consider it's own dtsi
>>>
>>>> it as a follow-on cleanup series, but would wait for the ABI 3.0 changes to be
>>>> merged first.
>>>
>>> Of course. We are expecting this to be part of rc2, please rebase and
>>> post once the tag is out. next-20200820 has it already, if you want a
>>> pre-look.
>>>
>>
>> So, the ABI 3.0 changes are not part of -rc2, so, I cannot move the unrelated
>> mailbox nodes/cleanup without conflicting with that series. Are you ok if I just
>> move these nodes into the SoM dtsi file?
> 
> Lets introduce things properly: First cleanup rather creating a
> kludgy intermediate state (half of r5 mbox nodes in proc, half of c6x
> node in SoM etc).

OK, posted a v2 [1] with the cleanup first. It does create a dependency on the
pending ABI 3.0 PR.

regards
Suman

[1] https://patchwork.kernel.org/cover/11736095/

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[PATCH 3/7] arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for C66 DSPs

[Suman Anna]

Two carveout reserved memory nodes each have been added for each of the
C66x DSP remote processor devices present within the MAIN voltage domain
for the TI J721E EVM boards. These nodes are assigned to the respective
rproc device nodes as well. The first region will be used as the DMA pool
for the rproc devices, and the second region will furnish the static
carveout regions for the firmware memory.

The minimum granularity on the Cache settings on C66x DSP cores is 16 MB,
so the DMA memory regions are chosen such that they are in separate 16 MB
regions for each DSP, while reserving a total of 16 MB for each DSP and
not changing the overall DSP remoteproc carveouts.

The current carveout addresses and sizes are defined statically for each
device. The C66x DSP processors do not have an MMU, and as such require the
exact memory used by the firmwares to be set-aside. The firmware images
do not require any RSC_CARVEOUT entries in their resource tables to
allocate the memory for firmware memory segments.

The reserved memory nodes can be disabled later on if there is no use-case
defined to use the corresponding remote processor.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 34 +++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
index 8fa3361e5e45..f1a8190e3b5a 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
@@ -25,6 +25,30 @@ secure_ddr: optee@9e800000 {
 			alignment = <0x1000>;
 			no-map;
 		};
+
+		c66_1_dma_memory_region: c66-dma-memory@a6000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa6000000 0x00 0x100000>;
+			no-map;
+		};
+
+		c66_0_memory_region: c66-memory@a6100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa6100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		c66_0_dma_memory_region: c66-dma-memory@a7000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa7000000 0x00 0x100000>;
+			no-map;
+		};
+
+		c66_1_memory_region: c66-memory@a7100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa7100000 0x00 0xf00000>;
+			no-map;
+		};
 	};
 };
 
@@ -72,3 +96,13 @@ flash@0{
 		#size-cells = <1>;
 	};
 };
+
+&c66_0 {
+	memory-region = <&c66_0_dma_memory_region>,
+			<&c66_0_memory_region>;
+};
+
+&c66_1 {
+	memory-region = <&c66_1_dma_memory_region>,
+			<&c66_1_memory_region>;
+};
-- 
2.28.0

[PATCH 3/7] arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for C66 DSPs

[Suman Anna]

Two carveout reserved memory nodes each have been added for each of the
C66x DSP remote processor devices present within the MAIN voltage domain
for the TI J721E EVM boards. These nodes are assigned to the respective
rproc device nodes as well. The first region will be used as the DMA pool
for the rproc devices, and the second region will furnish the static
carveout regions for the firmware memory.

The minimum granularity on the Cache settings on C66x DSP cores is 16 MB,
so the DMA memory regions are chosen such that they are in separate 16 MB
regions for each DSP, while reserving a total of 16 MB for each DSP and
not changing the overall DSP remoteproc carveouts.

The current carveout addresses and sizes are defined statically for each
device. The C66x DSP processors do not have an MMU, and as such require the
exact memory used by the firmwares to be set-aside. The firmware images
do not require any RSC_CARVEOUT entries in their resource tables to
allocate the memory for firmware memory segments.

The reserved memory nodes can be disabled later on if there is no use-case
defined to use the corresponding remote processor.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 34 +++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
index 8fa3361e5e45..f1a8190e3b5a 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
@@ -25,6 +25,30 @@ secure_ddr: optee@9e800000 {
 			alignment = <0x1000>;
 			no-map;
 		};
+
+		c66_1_dma_memory_region: c66-dma-memory@a6000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa6000000 0x00 0x100000>;
+			no-map;
+		};
+
+		c66_0_memory_region: c66-memory@a6100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa6100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		c66_0_dma_memory_region: c66-dma-memory@a7000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa7000000 0x00 0x100000>;
+			no-map;
+		};
+
+		c66_1_memory_region: c66-memory@a7100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa7100000 0x00 0xf00000>;
+			no-map;
+		};
 	};
 };
 
@@ -72,3 +96,13 @@ flash@0{
 		#size-cells = <1>;
 	};
 };
+
+&c66_0 {
+	memory-region = <&c66_0_dma_memory_region>,
+			<&c66_0_memory_region>;
+};
+
+&c66_1 {
+	memory-region = <&c66_1_dma_memory_region>,
+			<&c66_1_memory_region>;
+};
-- 
2.28.0


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[PATCH 4/7] arm64: dts: ti: k3-j721e-main: Add C71x DSP node

[Suman Anna]

The J721E SoCs have a single TMS320C71x DSP Subsystem in the MAIN
voltage domain containing the next-generation C711 CPU core. The
subsystem has 32 KB of L1D configurable SRAM/Cache and 512 KB of
L2 configurable SRAM/Cache. This subsystem has a CMMU but is not
used currently. The inter-processor communication between the main
A72 cores and the C711 processor is achieved through shared memory
and a Mailbox. Add the DT node for this DSP processor sub-system
in the common k3-j721e-main.dtsi file.

The following firmware name is used by default for the C71x core,
and can be overridden in a board dts file if desired:
    C71x_0 DSP: j7-c71_0-fw

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index 46cde2677e17..4ba5d356655a 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -1352,4 +1352,16 @@ c66_1: dsp@4d81800000 {
 		resets = <&k3_reset 143 1>;
 		firmware-name = "j7-c66_1-fw";
 	};
+
+	c71_0: dsp@64800000 {
+		compatible = "ti,j721e-c71-dsp";
+		reg = <0x00 0x64800000 0x00 0x00080000>,
+		      <0x00 0x64e00000 0x00 0x0000c000>;
+		reg-names = "l2sram", "l1dram";
+		ti,sci = <&dmsc>;
+		ti,sci-dev-id = <15>;
+		ti,sci-proc-ids = <0x30 0xff>;
+		resets = <&k3_reset 15 1>;
+		firmware-name = "j7-c71_0-fw";
+	};
 };
-- 
2.28.0

[PATCH 4/7] arm64: dts: ti: k3-j721e-main: Add C71x DSP node

[Suman Anna]

The J721E SoCs have a single TMS320C71x DSP Subsystem in the MAIN
voltage domain containing the next-generation C711 CPU core. The
subsystem has 32 KB of L1D configurable SRAM/Cache and 512 KB of
L2 configurable SRAM/Cache. This subsystem has a CMMU but is not
used currently. The inter-processor communication between the main
A72 cores and the C711 processor is achieved through shared memory
and a Mailbox. Add the DT node for this DSP processor sub-system
in the common k3-j721e-main.dtsi file.

The following firmware name is used by default for the C71x core,
and can be overridden in a board dts file if desired:
    C71x_0 DSP: j7-c71_0-fw

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index 46cde2677e17..4ba5d356655a 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -1352,4 +1352,16 @@ c66_1: dsp@4d81800000 {
 		resets = <&k3_reset 143 1>;
 		firmware-name = "j7-c66_1-fw";
 	};
+
+	c71_0: dsp@64800000 {
+		compatible = "ti,j721e-c71-dsp";
+		reg = <0x00 0x64800000 0x00 0x00080000>,
+		      <0x00 0x64e00000 0x00 0x0000c000>;
+		reg-names = "l2sram", "l1dram";
+		ti,sci = <&dmsc>;
+		ti,sci-dev-id = <15>;
+		ti,sci-proc-ids = <0x30 0xff>;
+		resets = <&k3_reset 15 1>;
+		firmware-name = "j7-c71_0-fw";
+	};
 };
-- 
2.28.0


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[PATCH 5/7] arm64: dts: ti: k3-j721e-common-proc-board: Add mailboxes to C71x DSP

[Suman Anna]

Add the required 'mboxes' property to the C71x DSP processor on the TI
J721E common processor board. The mailboxes and some shared memory are
required for running the Remote Processor Messaging (RPMsg) stack between
the host processor and each of the R5Fs. The chosen sub-mailboxes match
the values used in the current firmware images. This can be changed,
if needed, as per the system integration needs after making appropriate
changes on the firmware side as well.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index ff541dc09eca..acdae1f260a2 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -387,6 +387,10 @@ &c66_1 {
 	mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
 };
 
+&c71_0 {
+	mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
+};
+
 &main_sdhci0 {
 	/* eMMC */
 	non-removable;
-- 
2.28.0

[PATCH 5/7] arm64: dts: ti: k3-j721e-common-proc-board: Add mailboxes to C71x DSP

[Suman Anna]

Add the required 'mboxes' property to the C71x DSP processor on the TI
J721E common processor board. The mailboxes and some shared memory are
required for running the Remote Processor Messaging (RPMsg) stack between
the host processor and each of the R5Fs. The chosen sub-mailboxes match
the values used in the current firmware images. This can be changed,
if needed, as per the system integration needs after making appropriate
changes on the firmware side as well.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index ff541dc09eca..acdae1f260a2 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -387,6 +387,10 @@ &c66_1 {
 	mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
 };
 
+&c71_0 {
+	mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
+};
+
 &main_sdhci0 {
 	/* eMMC */
 	non-removable;
-- 
2.28.0


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[PATCH 6/7] arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for C71x DSP

[Suman Anna]

Two carveout reserved memory nodes have been added for the lone C71x DSP
remote processor device present within the MAIN voltage domain for the TI
J721E EVM boards. These nodes are assigned to the respective rproc device
node as well. The first region will be used as the DMA pool for the rproc
device, and the second region will furnish the static carveout regions for
the firmware memory.

The current carveout addresses and sizes are defined statically for each
device. The C71x DSP processor does support a MMU called CMMU, but is not
currently supported and as such requires the exact memory used by the
firmware to be set-aside. The firmware images currently do not need any
RSC_CARVEOUT entries either in their resource tables to allocate the
memory for firmware memory segments.

The reserved memory nodes can be disabled later on if there is no use-case
defined to use the C71x DSP remoteproc processor.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
index f1a8190e3b5a..600586cc22e5 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
@@ -49,6 +49,18 @@ c66_1_memory_region: c66-memory@a7100000 {
 			reg = <0x00 0xa7100000 0x00 0xf00000>;
 			no-map;
 		};
+
+		c71_0_dma_memory_region: c71-dma-memory@a8000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa8000000 0x00 0x100000>;
+			no-map;
+		};
+
+		c71_0_memory_region: c71-memory@a8100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa8100000 0x00 0xf00000>;
+			no-map;
+		};
 	};
 };
 
@@ -106,3 +118,8 @@ &c66_1 {
 	memory-region = <&c66_1_dma_memory_region>,
 			<&c66_1_memory_region>;
 };
+
+&c71_0 {
+	memory-region = <&c71_0_dma_memory_region>,
+			<&c71_0_memory_region>;
+};
-- 
2.28.0

[PATCH 6/7] arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for C71x DSP

[Suman Anna]

Two carveout reserved memory nodes have been added for the lone C71x DSP
remote processor device present within the MAIN voltage domain for the TI
J721E EVM boards. These nodes are assigned to the respective rproc device
node as well. The first region will be used as the DMA pool for the rproc
device, and the second region will furnish the static carveout regions for
the firmware memory.

The current carveout addresses and sizes are defined statically for each
device. The C71x DSP processor does support a MMU called CMMU, but is not
currently supported and as such requires the exact memory used by the
firmware to be set-aside. The firmware images currently do not need any
RSC_CARVEOUT entries either in their resource tables to allocate the
memory for firmware memory segments.

The reserved memory nodes can be disabled later on if there is no use-case
defined to use the C71x DSP remoteproc processor.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
index f1a8190e3b5a..600586cc22e5 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
@@ -49,6 +49,18 @@ c66_1_memory_region: c66-memory@a7100000 {
 			reg = <0x00 0xa7100000 0x00 0xf00000>;
 			no-map;
 		};
+
+		c71_0_dma_memory_region: c71-dma-memory@a8000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa8000000 0x00 0x100000>;
+			no-map;
+		};
+
+		c71_0_memory_region: c71-memory@a8100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa8100000 0x00 0xf00000>;
+			no-map;
+		};
 	};
 };
 
@@ -106,3 +118,8 @@ &c66_1 {
 	memory-region = <&c66_1_dma_memory_region>,
 			<&c66_1_memory_region>;
 };
+
+&c71_0 {
+	memory-region = <&c71_0_dma_memory_region>,
+			<&c71_0_memory_region>;
+};
-- 
2.28.0


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[PATCH 7/7] arm64: dts: ti: k3-j721e-som-p0: Reserve memory for IPC between RTOS cores

[Suman Anna]

Add a reserved memory node to reserve a portion of the DDR memory to be
used for performing inter-processor communication between all the remote
processors running RTOS on the TI J721E EVM boards. 28 MB of memory is
reserved for this purpose, and this accounts for all the vrings and vring
buffers between all the possible pairs of remote processors.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
index 600586cc22e5..d30a06248027 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
@@ -61,6 +61,12 @@ c71_0_memory_region: c71-memory@a8100000 {
 			reg = <0x00 0xa8100000 0x00 0xf00000>;
 			no-map;
 		};
+
+		rtos_ipc_memory_region: ipc-memories@aa000000 {
+			reg = <0x00 0xaa000000 0x00 0x01c00000>;
+			alignment = <0x1000>;
+			no-map;
+		};
 	};
 };
 
-- 
2.28.0

[PATCH 7/7] arm64: dts: ti: k3-j721e-som-p0: Reserve memory for IPC between RTOS cores

[Suman Anna]

Add a reserved memory node to reserve a portion of the DDR memory to be
used for performing inter-processor communication between all the remote
processors running RTOS on the TI J721E EVM boards. 28 MB of memory is
reserved for this purpose, and this accounts for all the vrings and vring
buffers between all the possible pairs of remote processors.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
index 600586cc22e5..d30a06248027 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
@@ -61,6 +61,12 @@ c71_0_memory_region: c71-memory@a8100000 {
 			reg = <0x00 0xa8100000 0x00 0xf00000>;
 			no-map;
 		};
+
+		rtos_ipc_memory_region: ipc-memories@aa000000 {
+			reg = <0x00 0xaa000000 0x00 0x01c00000>;
+			alignment = <0x1000>;
+			no-map;
+		};
 	};
 };
 
-- 
2.28.0


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