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* [PATCH v8] ARM: dts: qcom: ipq4019: add USB devicetree nodes
@ 2020-09-09 16:38 Robert Marko
  2020-10-02 17:39 ` Robert Marko
                   ` (2 more replies)
  0 siblings, 3 replies; 4+ messages in thread
From: Robert Marko @ 2020-09-09 16:38 UTC (permalink / raw)
  To: agross, bjorn.andersson, robh+dt, linux-arm-msm, devicetree,
	linux-kernel
  Cc: John Crispin, Robert Marko, Luka Perkov, Vinod Koul

From: John Crispin <john@phrozen.org>

Since we now have driver for the USB PHY, and USB controller is already supported by the DWC3 driver lets add the necessary nodes to DTSI.

Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
---
Changes from v7 to v8:
* Add labels for usb2 and usb3 nodes
Changes from v6 to v7:
* Remove changes to qcom-ipq4019-ap.dk01.1.dtsi
It has slipped in unwanted, we only want to add
nodes to the DTSI.

 arch/arm/boot/dts/qcom-ipq4019.dtsi | 74 +++++++++++++++++++++++++++++
 1 file changed, 74 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 74d8e2c8e4b3..4a973253024a 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -605,5 +605,79 @@ ethphy4: ethernet-phy@4 {
 				reg = <4>;
 			};
 		};
+
+		usb3_ss_phy: ssphy@9a000 {
+			compatible = "qcom,usb-ss-ipq4019-phy";
+			#phy-cells = <0>;
+			reg = <0x9a000 0x800>;
+			reg-names = "phy_base";
+			resets = <&gcc USB3_UNIPHY_PHY_ARES>;
+			reset-names = "por_rst";
+			status = "disabled";
+		};
+
+		usb3_hs_phy: hsphy@a6000 {
+			compatible = "qcom,usb-hs-ipq4019-phy";
+			#phy-cells = <0>;
+			reg = <0xa6000 0x40>;
+			reg-names = "phy_base";
+			resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>;
+			reset-names = "por_rst", "srif_rst";
+			status = "disabled";
+		};
+
+		usb3: usb3@8af8800 {
+			compatible = "qcom,dwc3";
+			reg = <0x8af8800 0x100>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			clocks = <&gcc GCC_USB3_MASTER_CLK>,
+				 <&gcc GCC_USB3_SLEEP_CLK>,
+				 <&gcc GCC_USB3_MOCK_UTMI_CLK>;
+			clock-names = "master", "sleep", "mock_utmi";
+			ranges;
+			status = "disabled";
+
+			dwc3@8a00000 {
+				compatible = "snps,dwc3";
+				reg = <0x8a00000 0xf8000>;
+				interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+				phys = <&usb3_hs_phy>, <&usb3_ss_phy>;
+				phy-names = "usb2-phy", "usb3-phy";
+				dr_mode = "host";
+			};
+		};
+
+		usb2_hs_phy: hsphy@a8000 {
+			compatible = "qcom,usb-hs-ipq4019-phy";
+			#phy-cells = <0>;
+			reg = <0xa8000 0x40>;
+			reg-names = "phy_base";
+			resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>;
+			reset-names = "por_rst", "srif_rst";
+			status = "disabled";
+		};
+
+		usb2: usb2@60f8800 {
+			compatible = "qcom,dwc3";
+			reg = <0x60f8800 0x100>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			clocks = <&gcc GCC_USB2_MASTER_CLK>,
+				 <&gcc GCC_USB2_SLEEP_CLK>,
+				 <&gcc GCC_USB2_MOCK_UTMI_CLK>;
+			clock-names = "master", "sleep", "mock_utmi";
+			ranges;
+			status = "disabled";
+
+			dwc3@6000000 {
+				compatible = "snps,dwc3";
+				reg = <0x6000000 0xf8000>;
+				interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+				phys = <&usb2_hs_phy>;
+				phy-names = "usb2-phy";
+				dr_mode = "host";
+			};
+		};
 	};
 };
-- 
2.26.2


^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH v8] ARM: dts: qcom: ipq4019: add USB devicetree nodes
  2020-09-09 16:38 [PATCH v8] ARM: dts: qcom: ipq4019: add USB devicetree nodes Robert Marko
@ 2020-10-02 17:39 ` Robert Marko
  2020-11-04 13:44 ` Robert Marko
  2021-01-22 21:40 ` patchwork-bot+linux-arm-msm
  2 siblings, 0 replies; 4+ messages in thread
From: Robert Marko @ 2020-10-02 17:39 UTC (permalink / raw)
  To: Andy Gross, Bjorn Andersson, robh+dt, linux-arm-msm, devicetree,
	linux-kernel
  Cc: John Crispin, Luka Perkov, Vinod Koul

On Wed, Sep 9, 2020 at 6:38 PM Robert Marko <robert.marko@sartura.hr> wrote:
>
> From: John Crispin <john@phrozen.org>
>
> Since we now have driver for the USB PHY, and USB controller is already supported by the DWC3 driver lets add the necessary nodes to DTSI.
>
> Signed-off-by: John Crispin <john@phrozen.org>
> Signed-off-by: Robert Marko <robert.marko@sartura.hr>
> Cc: Luka Perkov <luka.perkov@sartura.hr>
> Reviewed-by: Vinod Koul <vkoul@kernel.org>
> ---
> Changes from v7 to v8:
> * Add labels for usb2 and usb3 nodes
> Changes from v6 to v7:
> * Remove changes to qcom-ipq4019-ap.dk01.1.dtsi
> It has slipped in unwanted, we only want to add
> nodes to the DTSI.
>
>  arch/arm/boot/dts/qcom-ipq4019.dtsi | 74 +++++++++++++++++++++++++++++
>  1 file changed, 74 insertions(+)
>
> diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
> index 74d8e2c8e4b3..4a973253024a 100644
> --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
> +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
> @@ -605,5 +605,79 @@ ethphy4: ethernet-phy@4 {
>                                 reg = <4>;
>                         };
>                 };
> +
> +               usb3_ss_phy: ssphy@9a000 {
> +                       compatible = "qcom,usb-ss-ipq4019-phy";
> +                       #phy-cells = <0>;
> +                       reg = <0x9a000 0x800>;
> +                       reg-names = "phy_base";
> +                       resets = <&gcc USB3_UNIPHY_PHY_ARES>;
> +                       reset-names = "por_rst";
> +                       status = "disabled";
> +               };
> +
> +               usb3_hs_phy: hsphy@a6000 {
> +                       compatible = "qcom,usb-hs-ipq4019-phy";
> +                       #phy-cells = <0>;
> +                       reg = <0xa6000 0x40>;
> +                       reg-names = "phy_base";
> +                       resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>;
> +                       reset-names = "por_rst", "srif_rst";
> +                       status = "disabled";
> +               };
> +
> +               usb3: usb3@8af8800 {
> +                       compatible = "qcom,dwc3";
> +                       reg = <0x8af8800 0x100>;
> +                       #address-cells = <1>;
> +                       #size-cells = <1>;
> +                       clocks = <&gcc GCC_USB3_MASTER_CLK>,
> +                                <&gcc GCC_USB3_SLEEP_CLK>,
> +                                <&gcc GCC_USB3_MOCK_UTMI_CLK>;
> +                       clock-names = "master", "sleep", "mock_utmi";
> +                       ranges;
> +                       status = "disabled";
> +
> +                       dwc3@8a00000 {
> +                               compatible = "snps,dwc3";
> +                               reg = <0x8a00000 0xf8000>;
> +                               interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
> +                               phys = <&usb3_hs_phy>, <&usb3_ss_phy>;
> +                               phy-names = "usb2-phy", "usb3-phy";
> +                               dr_mode = "host";
> +                       };
> +               };
> +
> +               usb2_hs_phy: hsphy@a8000 {
> +                       compatible = "qcom,usb-hs-ipq4019-phy";
> +                       #phy-cells = <0>;
> +                       reg = <0xa8000 0x40>;
> +                       reg-names = "phy_base";
> +                       resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>;
> +                       reset-names = "por_rst", "srif_rst";
> +                       status = "disabled";
> +               };
> +
> +               usb2: usb2@60f8800 {
> +                       compatible = "qcom,dwc3";
> +                       reg = <0x60f8800 0x100>;
> +                       #address-cells = <1>;
> +                       #size-cells = <1>;
> +                       clocks = <&gcc GCC_USB2_MASTER_CLK>,
> +                                <&gcc GCC_USB2_SLEEP_CLK>,
> +                                <&gcc GCC_USB2_MOCK_UTMI_CLK>;
> +                       clock-names = "master", "sleep", "mock_utmi";
> +                       ranges;
> +                       status = "disabled";
> +
> +                       dwc3@6000000 {
> +                               compatible = "snps,dwc3";
> +                               reg = <0x6000000 0xf8000>;
> +                               interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
> +                               phys = <&usb2_hs_phy>;
> +                               phy-names = "usb2-phy";
> +                               dr_mode = "host";
> +                       };
> +               };
>         };
>  };
> --
> 2.26.2
>

Hi,
Is there an issue with the patch preventing the review?

Regards,
Robert

^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH v8] ARM: dts: qcom: ipq4019: add USB devicetree nodes
  2020-09-09 16:38 [PATCH v8] ARM: dts: qcom: ipq4019: add USB devicetree nodes Robert Marko
  2020-10-02 17:39 ` Robert Marko
@ 2020-11-04 13:44 ` Robert Marko
  2021-01-22 21:40 ` patchwork-bot+linux-arm-msm
  2 siblings, 0 replies; 4+ messages in thread
From: Robert Marko @ 2020-11-04 13:44 UTC (permalink / raw)
  To: Andy Gross, Bjorn Andersson, robh+dt, linux-arm-msm, devicetree,
	linux-kernel
  Cc: John Crispin, Luka Perkov, Vinod Koul

On Wed, Sep 9, 2020 at 6:38 PM Robert Marko <robert.marko@sartura.hr> wrote:
>
> From: John Crispin <john@phrozen.org>
>
> Since we now have driver for the USB PHY, and USB controller is already supported by the DWC3 driver lets add the necessary nodes to DTSI.
>
> Signed-off-by: John Crispin <john@phrozen.org>
> Signed-off-by: Robert Marko <robert.marko@sartura.hr>
> Cc: Luka Perkov <luka.perkov@sartura.hr>
> Reviewed-by: Vinod Koul <vkoul@kernel.org>
> ---
> Changes from v7 to v8:
> * Add labels for usb2 and usb3 nodes
> Changes from v6 to v7:
> * Remove changes to qcom-ipq4019-ap.dk01.1.dtsi
> It has slipped in unwanted, we only want to add
> nodes to the DTSI.
>
>  arch/arm/boot/dts/qcom-ipq4019.dtsi | 74 +++++++++++++++++++++++++++++
>  1 file changed, 74 insertions(+)
>
> diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
> index 74d8e2c8e4b3..4a973253024a 100644
> --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
> +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
> @@ -605,5 +605,79 @@ ethphy4: ethernet-phy@4 {
>                                 reg = <4>;
>                         };
>                 };
> +
> +               usb3_ss_phy: ssphy@9a000 {
> +                       compatible = "qcom,usb-ss-ipq4019-phy";
> +                       #phy-cells = <0>;
> +                       reg = <0x9a000 0x800>;
> +                       reg-names = "phy_base";
> +                       resets = <&gcc USB3_UNIPHY_PHY_ARES>;
> +                       reset-names = "por_rst";
> +                       status = "disabled";
> +               };
> +
> +               usb3_hs_phy: hsphy@a6000 {
> +                       compatible = "qcom,usb-hs-ipq4019-phy";
> +                       #phy-cells = <0>;
> +                       reg = <0xa6000 0x40>;
> +                       reg-names = "phy_base";
> +                       resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>;
> +                       reset-names = "por_rst", "srif_rst";
> +                       status = "disabled";
> +               };
> +
> +               usb3: usb3@8af8800 {
> +                       compatible = "qcom,dwc3";
> +                       reg = <0x8af8800 0x100>;
> +                       #address-cells = <1>;
> +                       #size-cells = <1>;
> +                       clocks = <&gcc GCC_USB3_MASTER_CLK>,
> +                                <&gcc GCC_USB3_SLEEP_CLK>,
> +                                <&gcc GCC_USB3_MOCK_UTMI_CLK>;
> +                       clock-names = "master", "sleep", "mock_utmi";
> +                       ranges;
> +                       status = "disabled";
> +
> +                       dwc3@8a00000 {
> +                               compatible = "snps,dwc3";
> +                               reg = <0x8a00000 0xf8000>;
> +                               interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
> +                               phys = <&usb3_hs_phy>, <&usb3_ss_phy>;
> +                               phy-names = "usb2-phy", "usb3-phy";
> +                               dr_mode = "host";
> +                       };
> +               };
> +
> +               usb2_hs_phy: hsphy@a8000 {
> +                       compatible = "qcom,usb-hs-ipq4019-phy";
> +                       #phy-cells = <0>;
> +                       reg = <0xa8000 0x40>;
> +                       reg-names = "phy_base";
> +                       resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>;
> +                       reset-names = "por_rst", "srif_rst";
> +                       status = "disabled";
> +               };
> +
> +               usb2: usb2@60f8800 {
> +                       compatible = "qcom,dwc3";
> +                       reg = <0x60f8800 0x100>;
> +                       #address-cells = <1>;
> +                       #size-cells = <1>;
> +                       clocks = <&gcc GCC_USB2_MASTER_CLK>,
> +                                <&gcc GCC_USB2_SLEEP_CLK>,
> +                                <&gcc GCC_USB2_MOCK_UTMI_CLK>;
> +                       clock-names = "master", "sleep", "mock_utmi";
> +                       ranges;
> +                       status = "disabled";
> +
> +                       dwc3@6000000 {
> +                               compatible = "snps,dwc3";
> +                               reg = <0x6000000 0xf8000>;
> +                               interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
> +                               phys = <&usb2_hs_phy>;
> +                               phy-names = "usb2-phy";
> +                               dr_mode = "host";
> +                       };
> +               };
>         };
>  };
> --
> 2.26.2

Hi,
Any chance of reviewing this?

Regards,
Robert
>

^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH v8] ARM: dts: qcom: ipq4019: add USB devicetree nodes
  2020-09-09 16:38 [PATCH v8] ARM: dts: qcom: ipq4019: add USB devicetree nodes Robert Marko
  2020-10-02 17:39 ` Robert Marko
  2020-11-04 13:44 ` Robert Marko
@ 2021-01-22 21:40 ` patchwork-bot+linux-arm-msm
  2 siblings, 0 replies; 4+ messages in thread
From: patchwork-bot+linux-arm-msm @ 2021-01-22 21:40 UTC (permalink / raw)
  To: Robert Marko; +Cc: linux-arm-msm

Hello:

This patch was applied to qcom/linux.git (refs/heads/for-next):

On Wed,  9 Sep 2020 18:38:31 +0200 you wrote:
> From: John Crispin <john@phrozen.org>
> 
> Since we now have driver for the USB PHY, and USB controller is already supported by the DWC3 driver lets add the necessary nodes to DTSI.
> 
> Signed-off-by: John Crispin <john@phrozen.org>
> Signed-off-by: Robert Marko <robert.marko@sartura.hr>
> Cc: Luka Perkov <luka.perkov@sartura.hr>
> Reviewed-by: Vinod Koul <vkoul@kernel.org>
> 
> [...]

Here is the summary with links:
  - [v8] ARM: dts: qcom: ipq4019: add USB devicetree nodes
    https://git.kernel.org/qcom/c/b8afc254b401

You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html



^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2021-01-22 21:41 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-09-09 16:38 [PATCH v8] ARM: dts: qcom: ipq4019: add USB devicetree nodes Robert Marko
2020-10-02 17:39 ` Robert Marko
2020-11-04 13:44 ` Robert Marko
2021-01-22 21:40 ` patchwork-bot+linux-arm-msm

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