* [PULL 01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap
2020-09-10 18:09 [PULL 00/30] riscv-to-apply queue Alistair Francis
@ 2020-09-10 18:09 ` Alistair Francis
2020-09-10 18:09 ` [PULL 02/30] riscv: sifive_test: Allow 16-bit writes to memory region Alistair Francis
` (29 subsequent siblings)
30 siblings, 0 replies; 34+ messages in thread
From: Alistair Francis @ 2020-09-10 18:09 UTC (permalink / raw)
To: peter.maydell, qemu-devel
Cc: alistair23, Alistair Francis, Yifei Jiang, Yipeng Yin
From: Yifei Jiang <jiangyifei@huawei.com>
When the cause number is equal to or greater than 23, print "(unknown)" in
trace_riscv_trap. The max valid number of riscv_excp_names is 23, so the last
excpetion "guest_store_page_fault" can not be printed.
In addition, the current check of cause is invalid for riscv_intr_names. So
introduce riscv_cpu_get_trap_name to get the trap cause name.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200814035819.1214-1-jiangyifei@huawei.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 1 +
target/riscv/cpu.c | 11 +++++++++++
target/riscv/cpu_helper.c | 4 ++--
3 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 383808bf88..d3589ae6ea 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -312,6 +312,7 @@ extern const char * const riscv_fpr_regnames[];
extern const char * const riscv_excp_names[];
extern const char * const riscv_intr_names[];
+const char *riscv_cpu_get_trap_name(target_ulong cause, bool async);
void riscv_cpu_do_interrupt(CPUState *cpu);
int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 228b9bdb5d..bcdce85c5e 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -96,6 +96,17 @@ const char * const riscv_intr_names[] = {
"reserved"
};
+const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
+{
+ if (async) {
+ return (cause < ARRAY_SIZE(riscv_intr_names)) ?
+ riscv_intr_names[cause] : "(unknown)";
+ } else {
+ return (cause < ARRAY_SIZE(riscv_excp_names)) ?
+ riscv_excp_names[cause] : "(unknown)";
+ }
+}
+
static void set_misa(CPURISCVState *env, target_ulong misa)
{
env->misa_mask = env->misa = misa;
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index dc7ae3e7b1..005880627e 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -892,8 +892,8 @@ void riscv_cpu_do_interrupt(CPUState *cs)
}
}
- trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, cause < 23 ?
- (async ? riscv_intr_names : riscv_excp_names)[cause] : "(unknown)");
+ trace_riscv_trap(env->mhartid, async, cause, env->pc, tval,
+ riscv_cpu_get_trap_name(cause, async));
if (env->priv <= PRV_S &&
cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) {
--
2.28.0
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PULL 02/30] riscv: sifive_test: Allow 16-bit writes to memory region
2020-09-10 18:09 [PULL 00/30] riscv-to-apply queue Alistair Francis
2020-09-10 18:09 ` [PULL 01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap Alistair Francis
@ 2020-09-10 18:09 ` Alistair Francis
2020-09-10 18:09 ` [PULL 03/30] target/riscv: cpu: Add a new 'resetvec' property Alistair Francis
` (28 subsequent siblings)
30 siblings, 0 replies; 34+ messages in thread
From: Alistair Francis @ 2020-09-10 18:09 UTC (permalink / raw)
To: peter.maydell, qemu-devel
Cc: alistair23, Nathan Chancellor, Alistair Francis, qemu-stable,
Michael S . Tsirkin
From: Nathan Chancellor <natechancellor@gmail.com>
When shutting down the machine running a mainline Linux kernel, the
following error happens:
$ build/riscv64-softmmu/qemu-system-riscv64 -bios default -M virt \
-display none -initrd rootfs.cpio -kernel Image -m 512m \
-nodefaults -serial mon:stdio
...
Requesting system poweroff
[ 4.999630] reboot: Power down
sbi_trap_error: hart0: trap handler failed (error -2)
sbi_trap_error: hart0: mcause=0x0000000000000007 mtval=0x0000000000100000
sbi_trap_error: hart0: mepc=0x000000008000d4cc mstatus=0x0000000000001822
sbi_trap_error: hart0: ra=0x000000008000999e sp=0x0000000080015c78
sbi_trap_error: hart0: gp=0xffffffe000e76610 tp=0xffffffe0081b89c0
sbi_trap_error: hart0: s0=0x0000000080015c88 s1=0x0000000000000040
sbi_trap_error: hart0: a0=0x0000000000000000 a1=0x0000000080004024
sbi_trap_error: hart0: a2=0x0000000080004024 a3=0x0000000080004024
sbi_trap_error: hart0: a4=0x0000000000100000 a5=0x0000000000005555
sbi_trap_error: hart0: a6=0x0000000000004024 a7=0x0000000080011158
sbi_trap_error: hart0: s2=0x0000000000000000 s3=0x0000000080016000
sbi_trap_error: hart0: s4=0x0000000000000000 s5=0x0000000000000000
sbi_trap_error: hart0: s6=0x0000000000000001 s7=0x0000000000000000
sbi_trap_error: hart0: s8=0x0000000000000000 s9=0x0000000000000000
sbi_trap_error: hart0: s10=0x0000000000000000 s11=0x0000000000000008
sbi_trap_error: hart0: t0=0x0000000000000000 t1=0x0000000000000000
sbi_trap_error: hart0: t2=0x0000000000000000 t3=0x0000000000000000
sbi_trap_error: hart0: t4=0x0000000000000000 t5=0x0000000000000000
sbi_trap_error: hart0: t6=0x0000000000000000
The kernel does a 16-bit write when powering off the machine, which
was allowed before commit 5d971f9e67 ("memory: Revert "memory: accept
mismatching sizes in memory_region_access_valid""). Make min_access_size
match reality so that the machine can shut down properly now.
Cc: qemu-stable@nongnu.org
Fixes: 88a07990fa ("SiFive RISC-V Test Finisher")
Fixes: 5d971f9e67 ("memory: Revert "memory: accept mismatching sizes in memory_region_access_valid"")
Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200901055822.2721209-1-natechancellor@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/sifive_test.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_test.c b/hw/riscv/sifive_test.c
index 0c78fb2c93..8c70dd69df 100644
--- a/hw/riscv/sifive_test.c
+++ b/hw/riscv/sifive_test.c
@@ -59,7 +59,7 @@ static const MemoryRegionOps sifive_test_ops = {
.write = sifive_test_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.valid = {
- .min_access_size = 4,
+ .min_access_size = 2,
.max_access_size = 4
}
};
--
2.28.0
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PULL 03/30] target/riscv: cpu: Add a new 'resetvec' property
2020-09-10 18:09 [PULL 00/30] riscv-to-apply queue Alistair Francis
2020-09-10 18:09 ` [PULL 01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap Alistair Francis
2020-09-10 18:09 ` [PULL 02/30] riscv: sifive_test: Allow 16-bit writes to memory region Alistair Francis
@ 2020-09-10 18:09 ` Alistair Francis
2020-09-10 18:09 ` [PULL 04/30] hw/riscv: hart: " Alistair Francis
` (27 subsequent siblings)
30 siblings, 0 replies; 34+ messages in thread
From: Alistair Francis @ 2020-09-10 18:09 UTC (permalink / raw)
To: peter.maydell, qemu-devel
Cc: alistair23, Bin Meng, Alistair Francis, Philippe Mathieu-Daudé
From: Bin Meng <bin.meng@windriver.com>
Currently the reset vector address is hard-coded in a RISC-V CPU's
instance_init() routine. In a real world we can have 2 exact same
CPUs except for the reset vector address, which is pretty common in
the RISC-V core IP licensing business.
Normally reset vector address is a configurable parameter. Let's
create a 64-bit property to store the reset vector address which
covers both 32-bit and 64-bit CPUs.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <1598924352-89526-2-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 1 +
target/riscv/cpu.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index d3589ae6ea..0d1728a8cd 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -291,6 +291,7 @@ typedef struct RISCVCPU {
uint16_t elen;
bool mmu;
bool pmp;
+ uint64_t resetvec;
} cfg;
} RISCVCPU;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index bcdce85c5e..f6aeecac15 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -529,6 +529,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
+ DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
DEFINE_PROP_END_OF_LIST(),
};
--
2.28.0
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PULL 04/30] hw/riscv: hart: Add a new 'resetvec' property
2020-09-10 18:09 [PULL 00/30] riscv-to-apply queue Alistair Francis
` (2 preceding siblings ...)
2020-09-10 18:09 ` [PULL 03/30] target/riscv: cpu: Add a new 'resetvec' property Alistair Francis
@ 2020-09-10 18:09 ` Alistair Francis
2020-09-10 18:09 ` [PULL 05/30] target/riscv: cpu: Set reset vector based on the configured property value Alistair Francis
` (26 subsequent siblings)
30 siblings, 0 replies; 34+ messages in thread
From: Alistair Francis @ 2020-09-10 18:09 UTC (permalink / raw)
To: peter.maydell, qemu-devel
Cc: alistair23, Bin Meng, Alistair Francis, Philippe Mathieu-Daudé
From: Bin Meng <bin.meng@windriver.com>
RISC-V machines do not instantiate RISC-V CPUs directly, instead
they do that via the hart array. Add a new property for the reset
vector address to allow the value to be passed to the CPU, before
CPU is realized.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <1598924352-89526-3-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/riscv_hart.h | 1 +
hw/riscv/riscv_hart.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h
index c75856fa73..77aa4bc948 100644
--- a/include/hw/riscv/riscv_hart.h
+++ b/include/hw/riscv/riscv_hart.h
@@ -37,6 +37,7 @@ typedef struct RISCVHartArrayState {
uint32_t num_harts;
uint32_t hartid_base;
char *cpu_type;
+ uint64_t resetvec;
RISCVCPU *harts;
} RISCVHartArrayState;
diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c
index f59fe52f0f..613ea2aaa0 100644
--- a/hw/riscv/riscv_hart.c
+++ b/hw/riscv/riscv_hart.c
@@ -31,6 +31,8 @@ static Property riscv_harts_props[] = {
DEFINE_PROP_UINT32("num-harts", RISCVHartArrayState, num_harts, 1),
DEFINE_PROP_UINT32("hartid-base", RISCVHartArrayState, hartid_base, 0),
DEFINE_PROP_STRING("cpu-type", RISCVHartArrayState, cpu_type),
+ DEFINE_PROP_UINT64("resetvec", RISCVHartArrayState, resetvec,
+ DEFAULT_RSTVEC),
DEFINE_PROP_END_OF_LIST(),
};
@@ -44,6 +46,7 @@ static bool riscv_hart_realize(RISCVHartArrayState *s, int idx,
char *cpu_type, Error **errp)
{
object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx], cpu_type);
+ qdev_prop_set_uint64(DEVICE(&s->harts[idx]), "resetvec", s->resetvec);
s->harts[idx].env.mhartid = s->hartid_base + idx;
qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]);
return qdev_realize(DEVICE(&s->harts[idx]), NULL, errp);
--
2.28.0
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PULL 05/30] target/riscv: cpu: Set reset vector based on the configured property value
2020-09-10 18:09 [PULL 00/30] riscv-to-apply queue Alistair Francis
` (3 preceding siblings ...)
2020-09-10 18:09 ` [PULL 04/30] hw/riscv: hart: " Alistair Francis
@ 2020-09-10 18:09 ` Alistair Francis
2020-09-10 18:09 ` [PULL 06/30] hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board Alistair Francis
` (25 subsequent siblings)
30 siblings, 0 replies; 34+ messages in thread
From: Alistair Francis @ 2020-09-10 18:09 UTC (permalink / raw)
To: peter.maydell, qemu-devel
Cc: alistair23, Bin Meng, Alistair Francis, Philippe Mathieu-Daudé
From: Bin Meng <bin.meng@windriver.com>
Now that we have the newly introduced 'resetvec' property in the
RISC-V CPU and HART, instead of hard-coding the reset vector addr
in the CPU's instance_init(), move that to riscv_cpu_realize()
based on the configured property value from the RISC-V machines.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <1598924352-89526-4-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/opentitan.c | 1 +
hw/riscv/sifive_e.c | 1 +
hw/riscv/sifive_u.c | 2 ++
target/riscv/cpu.c | 7 ++-----
4 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index 23ba3b4bfc..0531bd879b 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -111,6 +111,7 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
&error_abort);
object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
&error_abort);
+ object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8090, &error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
/* Boot ROM */
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index ca55cc438a..cd7560d8ec 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -177,6 +177,7 @@ static void sifive_e_soc_init(Object *obj)
object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);
object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
&error_abort);
+ object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x1004, &error_abort);
object_initialize_child(obj, "riscv.sifive.e.gpio0", &s->gpio,
TYPE_SIFIVE_GPIO);
}
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index a48046c6a0..404d5e6918 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -611,6 +611,7 @@ static void sifive_u_soc_instance_init(Object *obj)
qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1);
qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0);
qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU);
+ qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", 0x1004);
object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER);
qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1);
@@ -620,6 +621,7 @@ static void sifive_u_soc_instance_init(Object *obj)
qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1);
qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1);
qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", SIFIVE_U_CPU);
+ qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004);
object_initialize_child(obj, "prci", &s->prci, TYPE_SIFIVE_U_PRCI);
object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP);
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f6aeecac15..57c006df5d 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -139,7 +139,6 @@ static void riscv_any_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env;
set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
set_priv_version(env, PRIV_VERSION_1_11_0);
- set_resetvec(env, DEFAULT_RSTVEC);
}
static void riscv_base_cpu_init(Object *obj)
@@ -147,7 +146,6 @@ static void riscv_base_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env;
/* We set this in the realise function */
set_misa(env, 0);
- set_resetvec(env, DEFAULT_RSTVEC);
}
static void rvxx_sifive_u_cpu_init(Object *obj)
@@ -155,7 +153,6 @@ static void rvxx_sifive_u_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env;
set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
set_priv_version(env, PRIV_VERSION_1_10_0);
- set_resetvec(env, 0x1004);
}
static void rvxx_sifive_e_cpu_init(Object *obj)
@@ -163,7 +160,6 @@ static void rvxx_sifive_e_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env;
set_misa(env, RVXLEN | RVI | RVM | RVA | RVC | RVU);
set_priv_version(env, PRIV_VERSION_1_10_0);
- set_resetvec(env, 0x1004);
qdev_prop_set_bit(DEVICE(obj), "mmu", false);
}
@@ -174,7 +170,6 @@ static void rv32_ibex_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env;
set_misa(env, RV32 | RVI | RVM | RVC | RVU);
set_priv_version(env, PRIV_VERSION_1_10_0);
- set_resetvec(env, 0x8090);
qdev_prop_set_bit(DEVICE(obj), "mmu", false);
}
@@ -384,6 +379,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
set_feature(env, RISCV_FEATURE_PMP);
}
+ set_resetvec(env, cpu->cfg.resetvec);
+
/* If misa isn't set (rv32 and rv64 machines) set it here */
if (!env->misa) {
/* Do some ISA extension error checking */
--
2.28.0
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PULL 06/30] hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board
2020-09-10 18:09 [PULL 00/30] riscv-to-apply queue Alistair Francis
` (4 preceding siblings ...)
2020-09-10 18:09 ` [PULL 05/30] target/riscv: cpu: Set reset vector based on the configured property value Alistair Francis
@ 2020-09-10 18:09 ` Alistair Francis
2020-09-10 18:09 ` [PULL 07/30] hw/char: Add Microchip PolarFire SoC MMUART emulation Alistair Francis
` (24 subsequent siblings)
30 siblings, 0 replies; 34+ messages in thread
From: Alistair Francis @ 2020-09-10 18:09 UTC (permalink / raw)
To: peter.maydell, qemu-devel; +Cc: alistair23, Bin Meng, Alistair Francis
From: Bin Meng <bin.meng@windriver.com>
This is an initial support for Microchip PolarFire SoC Icicle Kit.
The Icicle Kit board integrates a PolarFire SoC, with one SiFive's
E51 plus four U54 cores and many on-chip peripherals and an FPGA.
For more details about Microchip PolarFire Soc, please see:
https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga
Unlike SiFive FU540, the RISC-V core resect vector is at 0x20220000.
The following perepherals are created as an unimplemented device:
- Bus Error Uint 0/1/2/3/4
- L2 cache controller
- SYSREG
- MPUCFG
- IOSCBCFG
More devices will be added later.
The BIOS image used by this machine is hss.bin, aka Hart Software
Services, which can be built from:
https://github.com/polarfire-soc/hart-software-services
To launch this machine:
$ qemu-system-riscv64 -nographic -M microchip-icicle-kit
The memory is set to 1 GiB by default to match the hardware.
A sanity check on ram size is performed in the machine init routine
to prompt user to increase the RAM size to > 1 GiB when less than
1 GiB ram is detected.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-5-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
default-configs/riscv64-softmmu.mak | 1 +
include/hw/riscv/microchip_pfsoc.h | 88 ++++++++
hw/riscv/microchip_pfsoc.c | 312 ++++++++++++++++++++++++++++
MAINTAINERS | 7 +
hw/riscv/Kconfig | 6 +
hw/riscv/meson.build | 1 +
6 files changed, 415 insertions(+)
create mode 100644 include/hw/riscv/microchip_pfsoc.h
create mode 100644 hw/riscv/microchip_pfsoc.c
diff --git a/default-configs/riscv64-softmmu.mak b/default-configs/riscv64-softmmu.mak
index aaf6d735bb..76b6195648 100644
--- a/default-configs/riscv64-softmmu.mak
+++ b/default-configs/riscv64-softmmu.mak
@@ -10,3 +10,4 @@ CONFIG_SPIKE=y
CONFIG_SIFIVE_E=y
CONFIG_SIFIVE_U=y
CONFIG_RISCV_VIRT=y
+CONFIG_MICROCHIP_PFSOC=y
diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
new file mode 100644
index 0000000000..1953ef1464
--- /dev/null
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -0,0 +1,88 @@
+/*
+ * Microchip PolarFire SoC machine interface
+ *
+ * Copyright (c) 2020 Wind River Systems, Inc.
+ *
+ * Author:
+ * Bin Meng <bin.meng@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_MICROCHIP_PFSOC_H
+#define HW_MICROCHIP_PFSOC_H
+
+typedef struct MicrochipPFSoCState {
+ /*< private >*/
+ DeviceState parent_obj;
+
+ /*< public >*/
+ CPUClusterState e_cluster;
+ CPUClusterState u_cluster;
+ RISCVHartArrayState e_cpus;
+ RISCVHartArrayState u_cpus;
+ DeviceState *plic;
+} MicrochipPFSoCState;
+
+#define TYPE_MICROCHIP_PFSOC "microchip.pfsoc"
+#define MICROCHIP_PFSOC(obj) \
+ OBJECT_CHECK(MicrochipPFSoCState, (obj), TYPE_MICROCHIP_PFSOC)
+
+typedef struct MicrochipIcicleKitState {
+ /*< private >*/
+ MachineState parent_obj;
+
+ /*< public >*/
+ MicrochipPFSoCState soc;
+} MicrochipIcicleKitState;
+
+#define TYPE_MICROCHIP_ICICLE_KIT_MACHINE \
+ MACHINE_TYPE_NAME("microchip-icicle-kit")
+#define MICROCHIP_ICICLE_KIT_MACHINE(obj) \
+ OBJECT_CHECK(MicrochipIcicleKitState, (obj), \
+ TYPE_MICROCHIP_ICICLE_KIT_MACHINE)
+
+enum {
+ MICROCHIP_PFSOC_DEBUG,
+ MICROCHIP_PFSOC_E51_DTIM,
+ MICROCHIP_PFSOC_BUSERR_UNIT0,
+ MICROCHIP_PFSOC_BUSERR_UNIT1,
+ MICROCHIP_PFSOC_BUSERR_UNIT2,
+ MICROCHIP_PFSOC_BUSERR_UNIT3,
+ MICROCHIP_PFSOC_BUSERR_UNIT4,
+ MICROCHIP_PFSOC_CLINT,
+ MICROCHIP_PFSOC_L2CC,
+ MICROCHIP_PFSOC_L2LIM,
+ MICROCHIP_PFSOC_PLIC,
+ MICROCHIP_PFSOC_SYSREG,
+ MICROCHIP_PFSOC_MPUCFG,
+ MICROCHIP_PFSOC_ENVM_CFG,
+ MICROCHIP_PFSOC_ENVM_DATA,
+ MICROCHIP_PFSOC_IOSCB_CFG,
+ MICROCHIP_PFSOC_DRAM,
+};
+
+#define MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT 1
+#define MICROCHIP_PFSOC_COMPUTE_CPU_COUNT 4
+
+#define MICROCHIP_PFSOC_PLIC_HART_CONFIG "MS"
+#define MICROCHIP_PFSOC_PLIC_NUM_SOURCES 185
+#define MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES 7
+#define MICROCHIP_PFSOC_PLIC_PRIORITY_BASE 0x04
+#define MICROCHIP_PFSOC_PLIC_PENDING_BASE 0x1000
+#define MICROCHIP_PFSOC_PLIC_ENABLE_BASE 0x2000
+#define MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE 0x80
+#define MICROCHIP_PFSOC_PLIC_CONTEXT_BASE 0x200000
+#define MICROCHIP_PFSOC_PLIC_CONTEXT_STRIDE 0x1000
+
+#endif /* HW_MICROCHIP_PFSOC_H */
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
new file mode 100644
index 0000000000..d946b2aae5
--- /dev/null
+++ b/hw/riscv/microchip_pfsoc.c
@@ -0,0 +1,312 @@
+/*
+ * QEMU RISC-V Board Compatible with Microchip PolarFire SoC Icicle Kit
+ *
+ * Copyright (c) 2020 Wind River Systems, Inc.
+ *
+ * Author:
+ * Bin Meng <bin.meng@windriver.com>
+ *
+ * Provides a board compatible with the Microchip PolarFire SoC Icicle Kit
+ *
+ * 0) CLINT (Core Level Interruptor)
+ * 1) PLIC (Platform Level Interrupt Controller)
+ * 2) eNVM (Embedded Non-Volatile Memory)
+ *
+ * This board currently generates devicetree dynamically that indicates at least
+ * two harts and up to five harts.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/error-report.h"
+#include "qemu/log.h"
+#include "qemu/units.h"
+#include "qemu/cutils.h"
+#include "qapi/error.h"
+#include "hw/boards.h"
+#include "hw/irq.h"
+#include "hw/loader.h"
+#include "hw/sysbus.h"
+#include "hw/cpu/cluster.h"
+#include "target/riscv/cpu.h"
+#include "hw/misc/unimp.h"
+#include "hw/riscv/boot.h"
+#include "hw/riscv/riscv_hart.h"
+#include "hw/riscv/sifive_clint.h"
+#include "hw/riscv/sifive_plic.h"
+#include "hw/riscv/microchip_pfsoc.h"
+
+/*
+ * The BIOS image used by this machine is called Hart Software Services (HSS).
+ * See https://github.com/polarfire-soc/hart-software-services
+ */
+#define BIOS_FILENAME "hss.bin"
+#define RESET_VECTOR 0x20220000
+
+static const struct MemmapEntry {
+ hwaddr base;
+ hwaddr size;
+} microchip_pfsoc_memmap[] = {
+ [MICROCHIP_PFSOC_DEBUG] = { 0x0, 0x1000 },
+ [MICROCHIP_PFSOC_E51_DTIM] = { 0x1000000, 0x2000 },
+ [MICROCHIP_PFSOC_BUSERR_UNIT0] = { 0x1700000, 0x1000 },
+ [MICROCHIP_PFSOC_BUSERR_UNIT1] = { 0x1701000, 0x1000 },
+ [MICROCHIP_PFSOC_BUSERR_UNIT2] = { 0x1702000, 0x1000 },
+ [MICROCHIP_PFSOC_BUSERR_UNIT3] = { 0x1703000, 0x1000 },
+ [MICROCHIP_PFSOC_BUSERR_UNIT4] = { 0x1704000, 0x1000 },
+ [MICROCHIP_PFSOC_CLINT] = { 0x2000000, 0x10000 },
+ [MICROCHIP_PFSOC_L2CC] = { 0x2010000, 0x1000 },
+ [MICROCHIP_PFSOC_L2LIM] = { 0x8000000, 0x2000000 },
+ [MICROCHIP_PFSOC_PLIC] = { 0xc000000, 0x4000000 },
+ [MICROCHIP_PFSOC_SYSREG] = { 0x20002000, 0x2000 },
+ [MICROCHIP_PFSOC_MPUCFG] = { 0x20005000, 0x1000 },
+ [MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 },
+ [MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 },
+ [MICROCHIP_PFSOC_IOSCB_CFG] = { 0x37080000, 0x1000 },
+ [MICROCHIP_PFSOC_DRAM] = { 0x80000000, 0x0 },
+};
+
+static void microchip_pfsoc_soc_instance_init(Object *obj)
+{
+ MachineState *ms = MACHINE(qdev_get_machine());
+ MicrochipPFSoCState *s = MICROCHIP_PFSOC(obj);
+
+ object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER);
+ qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0);
+
+ object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus,
+ TYPE_RISCV_HART_ARRAY);
+ qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1);
+ qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0);
+ qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type",
+ TYPE_RISCV_CPU_SIFIVE_E51);
+ qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", RESET_VECTOR);
+
+ object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER);
+ qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1);
+
+ object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus,
+ TYPE_RISCV_HART_ARRAY);
+ qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1);
+ qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1);
+ qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type",
+ TYPE_RISCV_CPU_SIFIVE_U54);
+ qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", RESET_VECTOR);
+}
+
+static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
+{
+ MachineState *ms = MACHINE(qdev_get_machine());
+ MicrochipPFSoCState *s = MICROCHIP_PFSOC(dev);
+ const struct MemmapEntry *memmap = microchip_pfsoc_memmap;
+ MemoryRegion *system_memory = get_system_memory();
+ MemoryRegion *e51_dtim_mem = g_new(MemoryRegion, 1);
+ MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
+ MemoryRegion *envm_data = g_new(MemoryRegion, 1);
+ char *plic_hart_config;
+ size_t plic_hart_config_len;
+ int i;
+
+ sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort);
+ /*
+ * The cluster must be realized after the RISC-V hart array container,
+ * as the container's CPU object is only created on realize, and the
+ * CPU must exist and have been parented into the cluster before the
+ * cluster is realized.
+ */
+ qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort);
+ qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort);
+
+ /* E51 DTIM */
+ memory_region_init_ram(e51_dtim_mem, NULL, "microchip.pfsoc.e51_dtim_mem",
+ memmap[MICROCHIP_PFSOC_E51_DTIM].size, &error_fatal);
+ memory_region_add_subregion(system_memory,
+ memmap[MICROCHIP_PFSOC_E51_DTIM].base,
+ e51_dtim_mem);
+
+ /* Bus Error Units */
+ create_unimplemented_device("microchip.pfsoc.buserr_unit0_mem",
+ memmap[MICROCHIP_PFSOC_BUSERR_UNIT0].base,
+ memmap[MICROCHIP_PFSOC_BUSERR_UNIT0].size);
+ create_unimplemented_device("microchip.pfsoc.buserr_unit1_mem",
+ memmap[MICROCHIP_PFSOC_BUSERR_UNIT1].base,
+ memmap[MICROCHIP_PFSOC_BUSERR_UNIT1].size);
+ create_unimplemented_device("microchip.pfsoc.buserr_unit2_mem",
+ memmap[MICROCHIP_PFSOC_BUSERR_UNIT2].base,
+ memmap[MICROCHIP_PFSOC_BUSERR_UNIT2].size);
+ create_unimplemented_device("microchip.pfsoc.buserr_unit3_mem",
+ memmap[MICROCHIP_PFSOC_BUSERR_UNIT3].base,
+ memmap[MICROCHIP_PFSOC_BUSERR_UNIT3].size);
+ create_unimplemented_device("microchip.pfsoc.buserr_unit4_mem",
+ memmap[MICROCHIP_PFSOC_BUSERR_UNIT4].base,
+ memmap[MICROCHIP_PFSOC_BUSERR_UNIT4].size);
+
+ /* CLINT */
+ sifive_clint_create(memmap[MICROCHIP_PFSOC_CLINT].base,
+ memmap[MICROCHIP_PFSOC_CLINT].size, 0, ms->smp.cpus,
+ SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
+
+ /* L2 cache controller */
+ create_unimplemented_device("microchip.pfsoc.l2cc",
+ memmap[MICROCHIP_PFSOC_L2CC].base, memmap[MICROCHIP_PFSOC_L2CC].size);
+
+ /*
+ * Add L2-LIM at reset size.
+ * This should be reduced in size as the L2 Cache Controller WayEnable
+ * register is incremented. Unfortunately I don't see a nice (or any) way
+ * to handle reducing or blocking out the L2 LIM while still allowing it
+ * be re returned to all enabled after a reset. For the time being, just
+ * leave it enabled all the time. This won't break anything, but will be
+ * too generous to misbehaving guests.
+ */
+ memory_region_init_ram(l2lim_mem, NULL, "microchip.pfsoc.l2lim",
+ memmap[MICROCHIP_PFSOC_L2LIM].size, &error_fatal);
+ memory_region_add_subregion(system_memory,
+ memmap[MICROCHIP_PFSOC_L2LIM].base,
+ l2lim_mem);
+
+ /* create PLIC hart topology configuration string */
+ plic_hart_config_len = (strlen(MICROCHIP_PFSOC_PLIC_HART_CONFIG) + 1) *
+ ms->smp.cpus;
+ plic_hart_config = g_malloc0(plic_hart_config_len);
+ for (i = 0; i < ms->smp.cpus; i++) {
+ if (i != 0) {
+ strncat(plic_hart_config, "," MICROCHIP_PFSOC_PLIC_HART_CONFIG,
+ plic_hart_config_len);
+ } else {
+ strncat(plic_hart_config, "M", plic_hart_config_len);
+ }
+ plic_hart_config_len -= (strlen(MICROCHIP_PFSOC_PLIC_HART_CONFIG) + 1);
+ }
+
+ /* PLIC */
+ s->plic = sifive_plic_create(memmap[MICROCHIP_PFSOC_PLIC].base,
+ plic_hart_config, 0,
+ MICROCHIP_PFSOC_PLIC_NUM_SOURCES,
+ MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES,
+ MICROCHIP_PFSOC_PLIC_PRIORITY_BASE,
+ MICROCHIP_PFSOC_PLIC_PENDING_BASE,
+ MICROCHIP_PFSOC_PLIC_ENABLE_BASE,
+ MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE,
+ MICROCHIP_PFSOC_PLIC_CONTEXT_BASE,
+ MICROCHIP_PFSOC_PLIC_CONTEXT_STRIDE,
+ memmap[MICROCHIP_PFSOC_PLIC].size);
+ g_free(plic_hart_config);
+
+ /* SYSREG */
+ create_unimplemented_device("microchip.pfsoc.sysreg",
+ memmap[MICROCHIP_PFSOC_SYSREG].base,
+ memmap[MICROCHIP_PFSOC_SYSREG].size);
+
+ /* MPUCFG */
+ create_unimplemented_device("microchip.pfsoc.mpucfg",
+ memmap[MICROCHIP_PFSOC_MPUCFG].base,
+ memmap[MICROCHIP_PFSOC_MPUCFG].size);
+
+ /* eNVM */
+ memory_region_init_rom(envm_data, OBJECT(dev), "microchip.pfsoc.envm.data",
+ memmap[MICROCHIP_PFSOC_ENVM_DATA].size,
+ &error_fatal);
+ memory_region_add_subregion(system_memory,
+ memmap[MICROCHIP_PFSOC_ENVM_DATA].base,
+ envm_data);
+
+ /* IOSCBCFG */
+ create_unimplemented_device("microchip.pfsoc.ioscb.cfg",
+ memmap[MICROCHIP_PFSOC_IOSCB_CFG].base,
+ memmap[MICROCHIP_PFSOC_IOSCB_CFG].size);
+}
+
+static void microchip_pfsoc_soc_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = microchip_pfsoc_soc_realize;
+ /* Reason: Uses serial_hds in realize function, thus can't be used twice */
+ dc->user_creatable = false;
+}
+
+static const TypeInfo microchip_pfsoc_soc_type_info = {
+ .name = TYPE_MICROCHIP_PFSOC,
+ .parent = TYPE_DEVICE,
+ .instance_size = sizeof(MicrochipPFSoCState),
+ .instance_init = microchip_pfsoc_soc_instance_init,
+ .class_init = microchip_pfsoc_soc_class_init,
+};
+
+static void microchip_pfsoc_soc_register_types(void)
+{
+ type_register_static(µchip_pfsoc_soc_type_info);
+}
+
+type_init(microchip_pfsoc_soc_register_types)
+
+static void microchip_icicle_kit_machine_init(MachineState *machine)
+{
+ MachineClass *mc = MACHINE_GET_CLASS(machine);
+ const struct MemmapEntry *memmap = microchip_pfsoc_memmap;
+ MicrochipIcicleKitState *s = MICROCHIP_ICICLE_KIT_MACHINE(machine);
+ MemoryRegion *system_memory = get_system_memory();
+ MemoryRegion *main_mem = g_new(MemoryRegion, 1);
+
+ /* Sanity check on RAM size */
+ if (machine->ram_size < mc->default_ram_size) {
+ char *sz = size_to_str(mc->default_ram_size);
+ error_report("Invalid RAM size, should be bigger than %s", sz);
+ g_free(sz);
+ exit(EXIT_FAILURE);
+ }
+
+ /* Initialize SoC */
+ object_initialize_child(OBJECT(machine), "soc", &s->soc,
+ TYPE_MICROCHIP_PFSOC);
+ qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
+
+ /* Register RAM */
+ memory_region_init_ram(main_mem, NULL, "microchip.icicle.kit.ram",
+ machine->ram_size, &error_fatal);
+ memory_region_add_subregion(system_memory,
+ memmap[MICROCHIP_PFSOC_DRAM].base, main_mem);
+
+ /* Load the firmware */
+ riscv_find_and_load_firmware(machine, BIOS_FILENAME, RESET_VECTOR, NULL);
+}
+
+static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+
+ mc->desc = "Microchip PolarFire SoC Icicle Kit";
+ mc->init = microchip_icicle_kit_machine_init;
+ mc->max_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT +
+ MICROCHIP_PFSOC_COMPUTE_CPU_COUNT;
+ mc->min_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + 1;
+ mc->default_cpus = mc->min_cpus;
+ mc->default_ram_size = 1 * GiB;
+}
+
+static const TypeInfo microchip_icicle_kit_machine_typeinfo = {
+ .name = MACHINE_TYPE_NAME("microchip-icicle-kit"),
+ .parent = TYPE_MACHINE,
+ .class_init = microchip_icicle_kit_machine_class_init,
+ .instance_size = sizeof(MicrochipIcicleKitState),
+};
+
+static void microchip_icicle_kit_machine_init_register_types(void)
+{
+ type_register_static(µchip_icicle_kit_machine_typeinfo);
+}
+
+type_init(microchip_icicle_kit_machine_init_register_types)
diff --git a/MAINTAINERS b/MAINTAINERS
index 7d0a5e91e4..9641ed37e2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1316,6 +1316,13 @@ F: include/hw/riscv/opentitan.h
F: include/hw/char/ibex_uart.h
F: include/hw/intc/ibex_plic.h
+Microchip PolarFire SoC Icicle Kit
+M: Bin Meng <bin.meng@windriver.com>
+L: qemu-riscv@nongnu.org
+S: Supported
+F: hw/riscv/microchip_pfsoc.c
+F: include/hw/riscv/microchip_pfsoc.h
+
RX Machines
-----------
rx-gdbsim
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index 28947ef3e0..3292faef27 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -48,3 +48,9 @@ config RISCV_VIRT
select PCI_EXPRESS_GENERIC_BRIDGE
select PFLASH_CFI01
select SIFIVE
+
+config MICROCHIP_PFSOC
+ bool
+ select HART
+ select SIFIVE
+ select UNIMP
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index fe2ea75f65..c29a48c3f1 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -16,5 +16,6 @@ riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_otp.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_prci.c'))
riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('riscv_htif.c'))
riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
+riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
hw_arch += {'riscv': riscv_ss}
--
2.28.0
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PULL 07/30] hw/char: Add Microchip PolarFire SoC MMUART emulation
2020-09-10 18:09 [PULL 00/30] riscv-to-apply queue Alistair Francis
` (5 preceding siblings ...)
2020-09-10 18:09 ` [PULL 06/30] hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board Alistair Francis
@ 2020-09-10 18:09 ` Alistair Francis
2021-09-18 16:55 ` Philippe Mathieu-Daudé
2020-09-10 18:09 ` [PULL 08/30] hw/riscv: microchip_pfsoc: Connect 5 MMUARTs Alistair Francis
` (23 subsequent siblings)
30 siblings, 1 reply; 34+ messages in thread
From: Alistair Francis @ 2020-09-10 18:09 UTC (permalink / raw)
To: peter.maydell, qemu-devel; +Cc: alistair23, Bin Meng, Alistair Francis
From: Bin Meng <bin.meng@windriver.com>
Microchip PolarFire SoC MMUART is ns16550 compatible, with some
additional registers. Create a simple MMUART model built on top
of the existing ns16550 model.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-6-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/char/mchp_pfsoc_mmuart.h | 61 ++++++++++++++++++++
hw/char/mchp_pfsoc_mmuart.c | 86 +++++++++++++++++++++++++++++
MAINTAINERS | 2 +
hw/char/Kconfig | 3 +
hw/char/meson.build | 1 +
5 files changed, 153 insertions(+)
create mode 100644 include/hw/char/mchp_pfsoc_mmuart.h
create mode 100644 hw/char/mchp_pfsoc_mmuart.c
diff --git a/include/hw/char/mchp_pfsoc_mmuart.h b/include/hw/char/mchp_pfsoc_mmuart.h
new file mode 100644
index 0000000000..f61990215f
--- /dev/null
+++ b/include/hw/char/mchp_pfsoc_mmuart.h
@@ -0,0 +1,61 @@
+/*
+ * Microchip PolarFire SoC MMUART emulation
+ *
+ * Copyright (c) 2020 Wind River Systems, Inc.
+ *
+ * Author:
+ * Bin Meng <bin.meng@windriver.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_MCHP_PFSOC_MMUART_H
+#define HW_MCHP_PFSOC_MMUART_H
+
+#include "hw/char/serial.h"
+
+#define MCHP_PFSOC_MMUART_REG_SIZE 52
+
+typedef struct MchpPfSoCMMUartState {
+ MemoryRegion iomem;
+ hwaddr base;
+ qemu_irq irq;
+
+ SerialMM *serial;
+
+ uint32_t reg[MCHP_PFSOC_MMUART_REG_SIZE / sizeof(uint32_t)];
+} MchpPfSoCMMUartState;
+
+/**
+ * mchp_pfsoc_mmuart_create - Create a Microchip PolarFire SoC MMUART
+ *
+ * This is a helper routine for board to create a MMUART device that is
+ * compatible with Microchip PolarFire SoC.
+ *
+ * @sysmem: system memory region to map
+ * @base: base address of the MMUART registers
+ * @irq: IRQ number of the MMUART device
+ * @chr: character device to associate to
+ *
+ * @return: a pointer to the device specific control structure
+ */
+MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem,
+ hwaddr base, qemu_irq irq, Chardev *chr);
+
+#endif /* HW_MCHP_PFSOC_MMUART_H */
diff --git a/hw/char/mchp_pfsoc_mmuart.c b/hw/char/mchp_pfsoc_mmuart.c
new file mode 100644
index 0000000000..8a002b0a19
--- /dev/null
+++ b/hw/char/mchp_pfsoc_mmuart.c
@@ -0,0 +1,86 @@
+/*
+ * Microchip PolarFire SoC MMUART emulation
+ *
+ * Copyright (c) 2020 Wind River Systems, Inc.
+ *
+ * Author:
+ * Bin Meng <bin.meng@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 or
+ * (at your option) version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "chardev/char.h"
+#include "exec/address-spaces.h"
+#include "hw/char/mchp_pfsoc_mmuart.h"
+
+static uint64_t mchp_pfsoc_mmuart_read(void *opaque, hwaddr addr, unsigned size)
+{
+ MchpPfSoCMMUartState *s = opaque;
+
+ if (addr >= MCHP_PFSOC_MMUART_REG_SIZE) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: read: addr=0x%" HWADDR_PRIx "\n",
+ __func__, addr);
+ return 0;
+ }
+
+ return s->reg[addr / sizeof(uint32_t)];
+}
+
+static void mchp_pfsoc_mmuart_write(void *opaque, hwaddr addr,
+ uint64_t value, unsigned size)
+{
+ MchpPfSoCMMUartState *s = opaque;
+ uint32_t val32 = (uint32_t)value;
+
+ if (addr >= MCHP_PFSOC_MMUART_REG_SIZE) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%" HWADDR_PRIx
+ " v=0x%x\n", __func__, addr, val32);
+ return;
+ }
+
+ s->reg[addr / sizeof(uint32_t)] = val32;
+}
+
+static const MemoryRegionOps mchp_pfsoc_mmuart_ops = {
+ .read = mchp_pfsoc_mmuart_read,
+ .write = mchp_pfsoc_mmuart_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .impl = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+};
+
+MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem,
+ hwaddr base, qemu_irq irq, Chardev *chr)
+{
+ MchpPfSoCMMUartState *s;
+
+ s = g_new0(MchpPfSoCMMUartState, 1);
+
+ memory_region_init_io(&s->iomem, NULL, &mchp_pfsoc_mmuart_ops, s,
+ "mchp.pfsoc.mmuart", 0x1000);
+
+ s->base = base;
+ s->irq = irq;
+
+ s->serial = serial_mm_init(sysmem, base, 2, irq, 399193, chr,
+ DEVICE_LITTLE_ENDIAN);
+
+ memory_region_add_subregion(sysmem, base + 0x20, &s->iomem);
+
+ return s;
+}
diff --git a/MAINTAINERS b/MAINTAINERS
index 9641ed37e2..d17b08fad9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1321,7 +1321,9 @@ M: Bin Meng <bin.meng@windriver.com>
L: qemu-riscv@nongnu.org
S: Supported
F: hw/riscv/microchip_pfsoc.c
+F: hw/char/mchp_pfsoc_mmuart.c
F: include/hw/riscv/microchip_pfsoc.h
+F: include/hw/char/mchp_pfsoc_mmuart.h
RX Machines
-----------
diff --git a/hw/char/Kconfig b/hw/char/Kconfig
index b7e0e4d5fa..1d645554c7 100644
--- a/hw/char/Kconfig
+++ b/hw/char/Kconfig
@@ -52,3 +52,6 @@ config RENESAS_SCI
config AVR_USART
bool
+
+config MCHP_PFSOC_MMUART
+ bool
diff --git a/hw/char/meson.build b/hw/char/meson.build
index e888215145..ae27932d00 100644
--- a/hw/char/meson.build
+++ b/hw/char/meson.build
@@ -32,6 +32,7 @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_aux.c'))
softmmu_ss.add(when: 'CONFIG_RENESAS_SCI', if_true: files('renesas_sci.c'))
softmmu_ss.add(when: 'CONFIG_SH4', if_true: files('sh_serial.c'))
softmmu_ss.add(when: 'CONFIG_STM32F2XX_USART', if_true: files('stm32f2xx_usart.c'))
+softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_MMUART', if_true: files('mchp_pfsoc_mmuart.c'))
specific_ss.add(when: 'CONFIG_TERMINAL3270', if_true: files('terminal3270.c'))
specific_ss.add(when: 'CONFIG_VIRTIO', if_true: files('virtio-serial-bus.c'))
--
2.28.0
^ permalink raw reply related [flat|nested] 34+ messages in thread* Re: [PULL 07/30] hw/char: Add Microchip PolarFire SoC MMUART emulation
2020-09-10 18:09 ` [PULL 07/30] hw/char: Add Microchip PolarFire SoC MMUART emulation Alistair Francis
@ 2021-09-18 16:55 ` Philippe Mathieu-Daudé
2021-09-19 23:03 ` Alistair Francis
0 siblings, 1 reply; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-09-18 16:55 UTC (permalink / raw)
To: Alistair Francis
Cc: Peter Maydell, Bin Meng, qemu-devel@nongnu.org Developers,
Alistair Francis
On Thu, Sep 10, 2020 at 8:29 PM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> Microchip PolarFire SoC MMUART is ns16550 compatible, with some
> additional registers. Create a simple MMUART model built on top
> of the existing ns16550 model.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> Message-Id: <1598924352-89526-6-git-send-email-bmeng.cn@gmail.com>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> include/hw/char/mchp_pfsoc_mmuart.h | 61 ++++++++++++++++++++
> hw/char/mchp_pfsoc_mmuart.c | 86 +++++++++++++++++++++++++++++
> MAINTAINERS | 2 +
> hw/char/Kconfig | 3 +
> hw/char/meson.build | 1 +
> 5 files changed, 153 insertions(+)
> create mode 100644 include/hw/char/mchp_pfsoc_mmuart.h
> create mode 100644 hw/char/mchp_pfsoc_mmuart.c
>
> diff --git a/include/hw/char/mchp_pfsoc_mmuart.h b/include/hw/char/mchp_pfsoc_mmuart.h
> new file mode 100644
> index 0000000000..f61990215f
> --- /dev/null
> +++ b/include/hw/char/mchp_pfsoc_mmuart.h
> @@ -0,0 +1,61 @@
> +/*
> + * Microchip PolarFire SoC MMUART emulation
> + *
> + * Copyright (c) 2020 Wind River Systems, Inc.
> + *
> + * Author:
> + * Bin Meng <bin.meng@windriver.com>
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#ifndef HW_MCHP_PFSOC_MMUART_H
> +#define HW_MCHP_PFSOC_MMUART_H
> +
> +#include "hw/char/serial.h"
> +
> +#define MCHP_PFSOC_MMUART_REG_SIZE 52
> +
> +typedef struct MchpPfSoCMMUartState {
> + MemoryRegion iomem;
> + hwaddr base;
> + qemu_irq irq;
> +
> + SerialMM *serial;
> +
> + uint32_t reg[MCHP_PFSOC_MMUART_REG_SIZE / sizeof(uint32_t)];
> +} MchpPfSoCMMUartState;
> +
> +/**
> + * mchp_pfsoc_mmuart_create - Create a Microchip PolarFire SoC MMUART
> + *
> + * This is a helper routine for board to create a MMUART device that is
> + * compatible with Microchip PolarFire SoC.
> + *
> + * @sysmem: system memory region to map
> + * @base: base address of the MMUART registers
> + * @irq: IRQ number of the MMUART device
> + * @chr: character device to associate to
> + *
> + * @return: a pointer to the device specific control structure
> + */
> +MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem,
> + hwaddr base, qemu_irq irq, Chardev *chr);
> +
> +#endif /* HW_MCHP_PFSOC_MMUART_H */
> diff --git a/hw/char/mchp_pfsoc_mmuart.c b/hw/char/mchp_pfsoc_mmuart.c
> new file mode 100644
> index 0000000000..8a002b0a19
> --- /dev/null
> +++ b/hw/char/mchp_pfsoc_mmuart.c
> @@ -0,0 +1,86 @@
> +/*
> + * Microchip PolarFire SoC MMUART emulation
> + *
> + * Copyright (c) 2020 Wind River Systems, Inc.
> + *
> + * Author:
> + * Bin Meng <bin.meng@windriver.com>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 or
> + * (at your option) version 3 of the License.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu/log.h"
> +#include "chardev/char.h"
> +#include "exec/address-spaces.h"
> +#include "hw/char/mchp_pfsoc_mmuart.h"
> +
> +static uint64_t mchp_pfsoc_mmuart_read(void *opaque, hwaddr addr, unsigned size)
> +{
> + MchpPfSoCMMUartState *s = opaque;
> +
> + if (addr >= MCHP_PFSOC_MMUART_REG_SIZE) {
> + qemu_log_mask(LOG_GUEST_ERROR, "%s: read: addr=0x%" HWADDR_PRIx "\n",
> + __func__, addr);
> + return 0;
> + }
> +
> + return s->reg[addr / sizeof(uint32_t)];
> +}
> +
> +static void mchp_pfsoc_mmuart_write(void *opaque, hwaddr addr,
> + uint64_t value, unsigned size)
> +{
> + MchpPfSoCMMUartState *s = opaque;
> + uint32_t val32 = (uint32_t)value;
> +
> + if (addr >= MCHP_PFSOC_MMUART_REG_SIZE) {
> + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%" HWADDR_PRIx
> + " v=0x%x\n", __func__, addr, val32);
> + return;
> + }
> +
> + s->reg[addr / sizeof(uint32_t)] = val32;
> +}
> +
> +static const MemoryRegionOps mchp_pfsoc_mmuart_ops = {
> + .read = mchp_pfsoc_mmuart_read,
> + .write = mchp_pfsoc_mmuart_write,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> + .impl = {
> + .min_access_size = 4,
> + .max_access_size = 4,
> + },
> +};
> +
> +MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem,
> + hwaddr base, qemu_irq irq, Chardev *chr)
> +{
> + MchpPfSoCMMUartState *s;
> +
> + s = g_new0(MchpPfSoCMMUartState, 1);
Please stop adding non-QOM devices, we try hard to get rid of them.
> +
> + memory_region_init_io(&s->iomem, NULL, &mchp_pfsoc_mmuart_ops, s,
> + "mchp.pfsoc.mmuart", 0x1000);
> +
> + s->base = base;
> + s->irq = irq;
> +
> + s->serial = serial_mm_init(sysmem, base, 2, irq, 399193, chr,
> + DEVICE_LITTLE_ENDIAN);
> +
> + memory_region_add_subregion(sysmem, base + 0x20, &s->iomem);
> +
> + return s;
> +}
^ permalink raw reply [flat|nested] 34+ messages in thread* Re: [PULL 07/30] hw/char: Add Microchip PolarFire SoC MMUART emulation
2021-09-18 16:55 ` Philippe Mathieu-Daudé
@ 2021-09-19 23:03 ` Alistair Francis
0 siblings, 0 replies; 34+ messages in thread
From: Alistair Francis @ 2021-09-19 23:03 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Peter Maydell, Bin Meng, Alistair Francis,
qemu-devel@nongnu.org Developers
On Sun, Sep 19, 2021 at 2:55 AM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> On Thu, Sep 10, 2020 at 8:29 PM Alistair Francis
> <alistair.francis@wdc.com> wrote:
> >
> > From: Bin Meng <bin.meng@windriver.com>
> >
> > Microchip PolarFire SoC MMUART is ns16550 compatible, with some
> > additional registers. Create a simple MMUART model built on top
> > of the existing ns16550 model.
> >
> > Signed-off-by: Bin Meng <bin.meng@windriver.com>
> > Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> > Message-Id: <1598924352-89526-6-git-send-email-bmeng.cn@gmail.com>
> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > ---
> > include/hw/char/mchp_pfsoc_mmuart.h | 61 ++++++++++++++++++++
> > hw/char/mchp_pfsoc_mmuart.c | 86 +++++++++++++++++++++++++++++
> > MAINTAINERS | 2 +
> > hw/char/Kconfig | 3 +
> > hw/char/meson.build | 1 +
> > 5 files changed, 153 insertions(+)
> > create mode 100644 include/hw/char/mchp_pfsoc_mmuart.h
> > create mode 100644 hw/char/mchp_pfsoc_mmuart.c
> >
> > diff --git a/include/hw/char/mchp_pfsoc_mmuart.h b/include/hw/char/mchp_pfsoc_mmuart.h
> > new file mode 100644
> > index 0000000000..f61990215f
> > --- /dev/null
> > +++ b/include/hw/char/mchp_pfsoc_mmuart.h
> > @@ -0,0 +1,61 @@
> > +/*
> > + * Microchip PolarFire SoC MMUART emulation
> > + *
> > + * Copyright (c) 2020 Wind River Systems, Inc.
> > + *
> > + * Author:
> > + * Bin Meng <bin.meng@windriver.com>
> > + *
> > + * Permission is hereby granted, free of charge, to any person obtaining a copy
> > + * of this software and associated documentation files (the "Software"), to deal
> > + * in the Software without restriction, including without limitation the rights
> > + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> > + * copies of the Software, and to permit persons to whom the Software is
> > + * furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice shall be included in
> > + * all copies or substantial portions of the Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> > + * THE SOFTWARE.
> > + */
> > +
> > +#ifndef HW_MCHP_PFSOC_MMUART_H
> > +#define HW_MCHP_PFSOC_MMUART_H
> > +
> > +#include "hw/char/serial.h"
> > +
> > +#define MCHP_PFSOC_MMUART_REG_SIZE 52
> > +
> > +typedef struct MchpPfSoCMMUartState {
> > + MemoryRegion iomem;
> > + hwaddr base;
> > + qemu_irq irq;
> > +
> > + SerialMM *serial;
> > +
> > + uint32_t reg[MCHP_PFSOC_MMUART_REG_SIZE / sizeof(uint32_t)];
> > +} MchpPfSoCMMUartState;
> > +
> > +/**
> > + * mchp_pfsoc_mmuart_create - Create a Microchip PolarFire SoC MMUART
> > + *
> > + * This is a helper routine for board to create a MMUART device that is
> > + * compatible with Microchip PolarFire SoC.
> > + *
> > + * @sysmem: system memory region to map
> > + * @base: base address of the MMUART registers
> > + * @irq: IRQ number of the MMUART device
> > + * @chr: character device to associate to
> > + *
> > + * @return: a pointer to the device specific control structure
> > + */
> > +MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem,
> > + hwaddr base, qemu_irq irq, Chardev *chr);
> > +
> > +#endif /* HW_MCHP_PFSOC_MMUART_H */
> > diff --git a/hw/char/mchp_pfsoc_mmuart.c b/hw/char/mchp_pfsoc_mmuart.c
> > new file mode 100644
> > index 0000000000..8a002b0a19
> > --- /dev/null
> > +++ b/hw/char/mchp_pfsoc_mmuart.c
> > @@ -0,0 +1,86 @@
> > +/*
> > + * Microchip PolarFire SoC MMUART emulation
> > + *
> > + * Copyright (c) 2020 Wind River Systems, Inc.
> > + *
> > + * Author:
> > + * Bin Meng <bin.meng@windriver.com>
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 or
> > + * (at your option) version 3 of the License.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License along
> > + * with this program; if not, see <http://www.gnu.org/licenses/>.
> > + */
> > +
> > +#include "qemu/osdep.h"
> > +#include "qemu/log.h"
> > +#include "chardev/char.h"
> > +#include "exec/address-spaces.h"
> > +#include "hw/char/mchp_pfsoc_mmuart.h"
> > +
> > +static uint64_t mchp_pfsoc_mmuart_read(void *opaque, hwaddr addr, unsigned size)
> > +{
> > + MchpPfSoCMMUartState *s = opaque;
> > +
> > + if (addr >= MCHP_PFSOC_MMUART_REG_SIZE) {
> > + qemu_log_mask(LOG_GUEST_ERROR, "%s: read: addr=0x%" HWADDR_PRIx "\n",
> > + __func__, addr);
> > + return 0;
> > + }
> > +
> > + return s->reg[addr / sizeof(uint32_t)];
> > +}
> > +
> > +static void mchp_pfsoc_mmuart_write(void *opaque, hwaddr addr,
> > + uint64_t value, unsigned size)
> > +{
> > + MchpPfSoCMMUartState *s = opaque;
> > + uint32_t val32 = (uint32_t)value;
> > +
> > + if (addr >= MCHP_PFSOC_MMUART_REG_SIZE) {
> > + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%" HWADDR_PRIx
> > + " v=0x%x\n", __func__, addr, val32);
> > + return;
> > + }
> > +
> > + s->reg[addr / sizeof(uint32_t)] = val32;
> > +}
> > +
> > +static const MemoryRegionOps mchp_pfsoc_mmuart_ops = {
> > + .read = mchp_pfsoc_mmuart_read,
> > + .write = mchp_pfsoc_mmuart_write,
> > + .endianness = DEVICE_LITTLE_ENDIAN,
> > + .impl = {
> > + .min_access_size = 4,
> > + .max_access_size = 4,
> > + },
> > +};
> > +
> > +MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem,
> > + hwaddr base, qemu_irq irq, Chardev *chr)
> > +{
> > + MchpPfSoCMMUartState *s;
> > +
> > + s = g_new0(MchpPfSoCMMUartState, 1);
>
> Please stop adding non-QOM devices, we try hard to get rid of them.
Sorry, because of serial_mm_init() I thought this would be ok
Alistair
^ permalink raw reply [flat|nested] 34+ messages in thread
* [PULL 08/30] hw/riscv: microchip_pfsoc: Connect 5 MMUARTs
2020-09-10 18:09 [PULL 00/30] riscv-to-apply queue Alistair Francis
` (6 preceding siblings ...)
2020-09-10 18:09 ` [PULL 07/30] hw/char: Add Microchip PolarFire SoC MMUART emulation Alistair Francis
@ 2020-09-10 18:09 ` Alistair Francis
2020-09-10 18:09 ` [PULL 09/30] hw/sd: Add Cadence SDHCI emulation Alistair Francis
` (22 subsequent siblings)
30 siblings, 0 replies; 34+ messages in thread
From: Alistair Francis @ 2020-09-10 18:09 UTC (permalink / raw)
To: peter.maydell, qemu-devel; +Cc: alistair23, Bin Meng, Alistair Francis
From: Bin Meng <bin.meng@windriver.com>
Microchip PolarFire SoC has 5 MMUARTs, and the Icicle Kit board
wires 4 of them out. Let's connect all 5 MMUARTs.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-7-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/microchip_pfsoc.h | 20 ++++++++++++++++++++
hw/riscv/microchip_pfsoc.c | 30 ++++++++++++++++++++++++++++++
hw/riscv/Kconfig | 1 +
3 files changed, 51 insertions(+)
diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
index 1953ef1464..a5efa1dcb8 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -22,6 +22,8 @@
#ifndef HW_MICROCHIP_PFSOC_H
#define HW_MICROCHIP_PFSOC_H
+#include "hw/char/mchp_pfsoc_mmuart.h"
+
typedef struct MicrochipPFSoCState {
/*< private >*/
DeviceState parent_obj;
@@ -32,6 +34,11 @@ typedef struct MicrochipPFSoCState {
RISCVHartArrayState e_cpus;
RISCVHartArrayState u_cpus;
DeviceState *plic;
+ MchpPfSoCMMUartState *serial0;
+ MchpPfSoCMMUartState *serial1;
+ MchpPfSoCMMUartState *serial2;
+ MchpPfSoCMMUartState *serial3;
+ MchpPfSoCMMUartState *serial4;
} MicrochipPFSoCState;
#define TYPE_MICROCHIP_PFSOC "microchip.pfsoc"
@@ -64,14 +71,27 @@ enum {
MICROCHIP_PFSOC_L2CC,
MICROCHIP_PFSOC_L2LIM,
MICROCHIP_PFSOC_PLIC,
+ MICROCHIP_PFSOC_MMUART0,
MICROCHIP_PFSOC_SYSREG,
MICROCHIP_PFSOC_MPUCFG,
+ MICROCHIP_PFSOC_MMUART1,
+ MICROCHIP_PFSOC_MMUART2,
+ MICROCHIP_PFSOC_MMUART3,
+ MICROCHIP_PFSOC_MMUART4,
MICROCHIP_PFSOC_ENVM_CFG,
MICROCHIP_PFSOC_ENVM_DATA,
MICROCHIP_PFSOC_IOSCB_CFG,
MICROCHIP_PFSOC_DRAM,
};
+enum {
+ MICROCHIP_PFSOC_MMUART0_IRQ = 90,
+ MICROCHIP_PFSOC_MMUART1_IRQ = 91,
+ MICROCHIP_PFSOC_MMUART2_IRQ = 92,
+ MICROCHIP_PFSOC_MMUART3_IRQ = 93,
+ MICROCHIP_PFSOC_MMUART4_IRQ = 94,
+};
+
#define MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT 1
#define MICROCHIP_PFSOC_COMPUTE_CPU_COUNT 4
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index d946b2aae5..cee959a5e0 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -11,6 +11,7 @@
* 0) CLINT (Core Level Interruptor)
* 1) PLIC (Platform Level Interrupt Controller)
* 2) eNVM (Embedded Non-Volatile Memory)
+ * 3) MMUARTs (Multi-Mode UART)
*
* This board currently generates devicetree dynamically that indicates at least
* two harts and up to five harts.
@@ -38,6 +39,7 @@
#include "hw/irq.h"
#include "hw/loader.h"
#include "hw/sysbus.h"
+#include "chardev/char.h"
#include "hw/cpu/cluster.h"
#include "target/riscv/cpu.h"
#include "hw/misc/unimp.h"
@@ -46,6 +48,7 @@
#include "hw/riscv/sifive_clint.h"
#include "hw/riscv/sifive_plic.h"
#include "hw/riscv/microchip_pfsoc.h"
+#include "sysemu/sysemu.h"
/*
* The BIOS image used by this machine is called Hart Software Services (HSS).
@@ -69,8 +72,13 @@ static const struct MemmapEntry {
[MICROCHIP_PFSOC_L2CC] = { 0x2010000, 0x1000 },
[MICROCHIP_PFSOC_L2LIM] = { 0x8000000, 0x2000000 },
[MICROCHIP_PFSOC_PLIC] = { 0xc000000, 0x4000000 },
+ [MICROCHIP_PFSOC_MMUART0] = { 0x20000000, 0x1000 },
[MICROCHIP_PFSOC_SYSREG] = { 0x20002000, 0x2000 },
[MICROCHIP_PFSOC_MPUCFG] = { 0x20005000, 0x1000 },
+ [MICROCHIP_PFSOC_MMUART1] = { 0x20100000, 0x1000 },
+ [MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 },
+ [MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 },
+ [MICROCHIP_PFSOC_MMUART4] = { 0x20106000, 0x1000 },
[MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 },
[MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 },
[MICROCHIP_PFSOC_IOSCB_CFG] = { 0x37080000, 0x1000 },
@@ -215,6 +223,28 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
memmap[MICROCHIP_PFSOC_MPUCFG].base,
memmap[MICROCHIP_PFSOC_MPUCFG].size);
+ /* MMUARTs */
+ s->serial0 = mchp_pfsoc_mmuart_create(system_memory,
+ memmap[MICROCHIP_PFSOC_MMUART0].base,
+ qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART0_IRQ),
+ serial_hd(0));
+ s->serial1 = mchp_pfsoc_mmuart_create(system_memory,
+ memmap[MICROCHIP_PFSOC_MMUART1].base,
+ qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART1_IRQ),
+ serial_hd(1));
+ s->serial2 = mchp_pfsoc_mmuart_create(system_memory,
+ memmap[MICROCHIP_PFSOC_MMUART2].base,
+ qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART2_IRQ),
+ serial_hd(2));
+ s->serial3 = mchp_pfsoc_mmuart_create(system_memory,
+ memmap[MICROCHIP_PFSOC_MMUART3].base,
+ qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART3_IRQ),
+ serial_hd(3));
+ s->serial4 = mchp_pfsoc_mmuart_create(system_memory,
+ memmap[MICROCHIP_PFSOC_MMUART4].base,
+ qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART4_IRQ),
+ serial_hd(4));
+
/* eNVM */
memory_region_init_rom(envm_data, OBJECT(dev), "microchip.pfsoc.envm.data",
memmap[MICROCHIP_PFSOC_ENVM_DATA].size,
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index 3292faef27..ceb7c166a3 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -54,3 +54,4 @@ config MICROCHIP_PFSOC
select HART
select SIFIVE
select UNIMP
+ select MCHP_PFSOC_MMUART
--
2.28.0
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PULL 09/30] hw/sd: Add Cadence SDHCI emulation
2020-09-10 18:09 [PULL 00/30] riscv-to-apply queue Alistair Francis
` (7 preceding siblings ...)
2020-09-10 18:09 ` [PULL 08/30] hw/riscv: microchip_pfsoc: Connect 5 MMUARTs Alistair Francis
@ 2020-09-10 18:09 ` Alistair Francis
2020-09-10 18:09 ` [PULL 10/30] hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card Alistair Francis
` (21 subsequent siblings)
30 siblings, 0 replies; 34+ messages in thread
From: Alistair Francis @ 2020-09-10 18:09 UTC (permalink / raw)
To: peter.maydell, qemu-devel
Cc: alistair23, Bin Meng, Alistair Francis, Philippe Mathieu-Daudé
From: Bin Meng <bin.meng@windriver.com>
Cadence SD/SDIO/eMMC Host Controller (SD4HC) is an SDHCI compatible
controller. The SDHCI compatible registers start from offset 0x200,
which are called Slot Register Set (SRS) in its datasheet.
This creates a Cadence SDHCI model built on top of the existing
generic SDHCI model. Cadence specific Host Register Set (HRS) is
implemented to make guest software happy.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-8-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/sd/cadence_sdhci.h | 47 +++++++++
hw/sd/cadence_sdhci.c | 193 ++++++++++++++++++++++++++++++++++
hw/sd/Kconfig | 4 +
hw/sd/meson.build | 1 +
4 files changed, 245 insertions(+)
create mode 100644 include/hw/sd/cadence_sdhci.h
create mode 100644 hw/sd/cadence_sdhci.c
diff --git a/include/hw/sd/cadence_sdhci.h b/include/hw/sd/cadence_sdhci.h
new file mode 100644
index 0000000000..cd8288b7d8
--- /dev/null
+++ b/include/hw/sd/cadence_sdhci.h
@@ -0,0 +1,47 @@
+/*
+ * Cadence SDHCI emulation
+ *
+ * Copyright (c) 2020 Wind River Systems, Inc.
+ *
+ * Author:
+ * Bin Meng <bin.meng@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 or
+ * (at your option) version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef CADENCE_SDHCI_H
+#define CADENCE_SDHCI_H
+
+#include "hw/sd/sdhci.h"
+
+#define CADENCE_SDHCI_REG_SIZE 0x100
+#define CADENCE_SDHCI_NUM_REGS (CADENCE_SDHCI_REG_SIZE / sizeof(uint32_t))
+
+typedef struct CadenceSDHCIState {
+ SysBusDevice parent;
+
+ MemoryRegion container;
+ MemoryRegion iomem;
+ BusState *bus;
+
+ uint32_t regs[CADENCE_SDHCI_NUM_REGS];
+
+ SDHCIState sdhci;
+} CadenceSDHCIState;
+
+#define TYPE_CADENCE_SDHCI "cadence.sdhci"
+#define CADENCE_SDHCI(obj) OBJECT_CHECK(CadenceSDHCIState, (obj), \
+ TYPE_CADENCE_SDHCI)
+
+#endif /* CADENCE_SDHCI_H */
diff --git a/hw/sd/cadence_sdhci.c b/hw/sd/cadence_sdhci.c
new file mode 100644
index 0000000000..0b371c843d
--- /dev/null
+++ b/hw/sd/cadence_sdhci.c
@@ -0,0 +1,193 @@
+/*
+ * Cadence SDHCI emulation
+ *
+ * Copyright (c) 2020 Wind River Systems, Inc.
+ *
+ * Author:
+ * Bin Meng <bin.meng@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 or
+ * (at your option) version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/bitops.h"
+#include "qemu/error-report.h"
+#include "qemu/log.h"
+#include "qapi/error.h"
+#include "migration/vmstate.h"
+#include "hw/irq.h"
+#include "hw/sd/cadence_sdhci.h"
+#include "sdhci-internal.h"
+
+/* HRS - Host Register Set (specific to Cadence) */
+
+#define CADENCE_SDHCI_HRS00 0x00 /* general information */
+#define CADENCE_SDHCI_HRS00_SWR BIT(0)
+#define CADENCE_SDHCI_HRS00_POR_VAL 0x00010000
+
+#define CADENCE_SDHCI_HRS04 0x10 /* PHY access port */
+#define CADENCE_SDHCI_HRS04_WR BIT(24)
+#define CADENCE_SDHCI_HRS04_RD BIT(25)
+#define CADENCE_SDHCI_HRS04_ACK BIT(26)
+
+#define CADENCE_SDHCI_HRS06 0x18 /* eMMC control */
+#define CADENCE_SDHCI_HRS06_TUNE_UP BIT(15)
+
+/* SRS - Slot Register Set (SDHCI-compatible) */
+
+#define CADENCE_SDHCI_SRS_BASE 0x200
+
+#define TO_REG(addr) ((addr) / sizeof(uint32_t))
+
+static void cadence_sdhci_instance_init(Object *obj)
+{
+ CadenceSDHCIState *s = CADENCE_SDHCI(obj);
+
+ object_initialize_child(OBJECT(s), "generic-sdhci",
+ &s->sdhci, TYPE_SYSBUS_SDHCI);
+}
+
+static void cadence_sdhci_reset(DeviceState *dev)
+{
+ CadenceSDHCIState *s = CADENCE_SDHCI(dev);
+
+ memset(s->regs, 0, CADENCE_SDHCI_REG_SIZE);
+ s->regs[TO_REG(CADENCE_SDHCI_HRS00)] = CADENCE_SDHCI_HRS00_POR_VAL;
+
+ device_cold_reset(DEVICE(&s->sdhci));
+}
+
+static uint64_t cadence_sdhci_read(void *opaque, hwaddr addr, unsigned int size)
+{
+ CadenceSDHCIState *s = opaque;
+ uint32_t val;
+
+ val = s->regs[TO_REG(addr)];
+
+ return (uint64_t)val;
+}
+
+static void cadence_sdhci_write(void *opaque, hwaddr addr, uint64_t val,
+ unsigned int size)
+{
+ CadenceSDHCIState *s = opaque;
+ uint32_t val32 = (uint32_t)val;
+
+ switch (addr) {
+ case CADENCE_SDHCI_HRS00:
+ /*
+ * The only writable bit is SWR (software reset) and it automatically
+ * clears to zero, so essentially this register remains unchanged.
+ */
+ if (val32 & CADENCE_SDHCI_HRS00_SWR) {
+ cadence_sdhci_reset(DEVICE(s));
+ }
+
+ break;
+ case CADENCE_SDHCI_HRS04:
+ /*
+ * Only emulate the ACK bit behavior when read or write transaction
+ * are requested.
+ */
+ if (val32 & (CADENCE_SDHCI_HRS04_WR | CADENCE_SDHCI_HRS04_RD)) {
+ val32 |= CADENCE_SDHCI_HRS04_ACK;
+ } else {
+ val32 &= ~CADENCE_SDHCI_HRS04_ACK;
+ }
+
+ s->regs[TO_REG(addr)] = val32;
+ break;
+ case CADENCE_SDHCI_HRS06:
+ if (val32 & CADENCE_SDHCI_HRS06_TUNE_UP) {
+ val32 &= ~CADENCE_SDHCI_HRS06_TUNE_UP;
+ }
+
+ s->regs[TO_REG(addr)] = val32;
+ break;
+ default:
+ s->regs[TO_REG(addr)] = val32;
+ break;
+ }
+}
+
+static const MemoryRegionOps cadence_sdhci_ops = {
+ .read = cadence_sdhci_read,
+ .write = cadence_sdhci_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .impl = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ }
+};
+
+static void cadence_sdhci_realize(DeviceState *dev, Error **errp)
+{
+ CadenceSDHCIState *s = CADENCE_SDHCI(dev);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+ SysBusDevice *sbd_sdhci = SYS_BUS_DEVICE(&s->sdhci);
+
+ memory_region_init(&s->container, OBJECT(s),
+ "cadence.sdhci-container", 0x1000);
+ sysbus_init_mmio(sbd, &s->container);
+
+ memory_region_init_io(&s->iomem, OBJECT(s), &cadence_sdhci_ops,
+ s, TYPE_CADENCE_SDHCI, CADENCE_SDHCI_REG_SIZE);
+ memory_region_add_subregion(&s->container, 0, &s->iomem);
+
+ sysbus_realize(sbd_sdhci, errp);
+ memory_region_add_subregion(&s->container, CADENCE_SDHCI_SRS_BASE,
+ sysbus_mmio_get_region(sbd_sdhci, 0));
+
+ /* propagate irq and "sd-bus" from generic-sdhci */
+ sysbus_pass_irq(sbd, sbd_sdhci);
+ s->bus = qdev_get_child_bus(DEVICE(sbd_sdhci), "sd-bus");
+}
+
+static const VMStateDescription vmstate_cadence_sdhci = {
+ .name = TYPE_CADENCE_SDHCI,
+ .version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(regs, CadenceSDHCIState, CADENCE_SDHCI_NUM_REGS),
+ VMSTATE_END_OF_LIST(),
+ },
+};
+
+static void cadence_sdhci_class_init(ObjectClass *classp, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(classp);
+
+ dc->desc = "Cadence SD/SDIO/eMMC Host Controller (SD4HC)";
+ dc->realize = cadence_sdhci_realize;
+ dc->reset = cadence_sdhci_reset;
+ dc->vmsd = &vmstate_cadence_sdhci;
+}
+
+static TypeInfo cadence_sdhci_info = {
+ .name = TYPE_CADENCE_SDHCI,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(CadenceSDHCIState),
+ .instance_init = cadence_sdhci_instance_init,
+ .class_init = cadence_sdhci_class_init,
+};
+
+static void cadence_sdhci_register_types(void)
+{
+ type_register_static(&cadence_sdhci_info);
+}
+
+type_init(cadence_sdhci_register_types)
diff --git a/hw/sd/Kconfig b/hw/sd/Kconfig
index c5e1e5581c..633b9afec9 100644
--- a/hw/sd/Kconfig
+++ b/hw/sd/Kconfig
@@ -19,3 +19,7 @@ config SDHCI_PCI
default y if PCI_DEVICES
depends on PCI
select SDHCI
+
+config CADENCE_SDHCI
+ bool
+ select SDHCI
diff --git a/hw/sd/meson.build b/hw/sd/meson.build
index b43e59bd00..9c29691e13 100644
--- a/hw/sd/meson.build
+++ b/hw/sd/meson.build
@@ -10,3 +10,4 @@ softmmu_ss.add(when: 'CONFIG_PXA2XX', if_true: files('pxa2xx_mmci.c'))
softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_sdhost.c'))
softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_sdhci.c'))
softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-sdhost.c'))
+softmmu_ss.add(when: 'CONFIG_CADENCE_SDHCI', if_true: files('cadence_sdhci.c'))
--
2.28.0
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PULL 10/30] hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card
2020-09-10 18:09 [PULL 00/30] riscv-to-apply queue Alistair Francis
` (8 preceding siblings ...)
2020-09-10 18:09 ` [PULL 09/30] hw/sd: Add Cadence SDHCI emulation Alistair Francis
@ 2020-09-10 18:09 ` Alistair Francis
2020-09-10 18:09 ` [PULL 11/30] hw/dma: Add SiFive platform DMA controller emulation Alistair Francis
` (20 subsequent siblings)
30 siblings, 0 replies; 34+ messages in thread
From: Alistair Francis @ 2020-09-10 18:09 UTC (permalink / raw)
To: peter.maydell, qemu-devel
Cc: alistair23, Bin Meng, Alistair Francis, Philippe Mathieu-Daudé
From: Bin Meng <bin.meng@windriver.com>
Microchip PolarFire SoC integrates one Cadence SDHCI controller.
On the Icicle Kit board, one eMMC chip and an external SD card
connect to this controller depending on different configuration.
As QEMU does not support eMMC yet, we just emulate the SD card
configuration. To test this, the Hart Software Services (HSS)
should choose the SD card configuration:
$ cp boards/icicle-kit-es/def_config.sdcard .config
$ make BOARD=icicle-kit-es
The SD card image can be built from the Yocto BSP at:
https://github.com/polarfire-soc/meta-polarfire-soc-yocto-bsp
Note the generated SD card image should be resized before use:
$ qemu-img resize /path/to/sdcard.img 4G
Launch QEMU with the following command:
$ qemu-system-riscv64 -nographic -M microchip-icicle-kit -sd sdcard.img
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-9-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/microchip_pfsoc.h | 4 ++++
hw/riscv/microchip_pfsoc.c | 23 +++++++++++++++++++++++
hw/riscv/Kconfig | 1 +
3 files changed, 28 insertions(+)
diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
index a5efa1dcb8..d810ee8484 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -23,6 +23,7 @@
#define HW_MICROCHIP_PFSOC_H
#include "hw/char/mchp_pfsoc_mmuart.h"
+#include "hw/sd/cadence_sdhci.h"
typedef struct MicrochipPFSoCState {
/*< private >*/
@@ -39,6 +40,7 @@ typedef struct MicrochipPFSoCState {
MchpPfSoCMMUartState *serial2;
MchpPfSoCMMUartState *serial3;
MchpPfSoCMMUartState *serial4;
+ CadenceSDHCIState sdhci;
} MicrochipPFSoCState;
#define TYPE_MICROCHIP_PFSOC "microchip.pfsoc"
@@ -74,6 +76,7 @@ enum {
MICROCHIP_PFSOC_MMUART0,
MICROCHIP_PFSOC_SYSREG,
MICROCHIP_PFSOC_MPUCFG,
+ MICROCHIP_PFSOC_EMMC_SD,
MICROCHIP_PFSOC_MMUART1,
MICROCHIP_PFSOC_MMUART2,
MICROCHIP_PFSOC_MMUART3,
@@ -85,6 +88,7 @@ enum {
};
enum {
+ MICROCHIP_PFSOC_EMMC_SD_IRQ = 88,
MICROCHIP_PFSOC_MMUART0_IRQ = 90,
MICROCHIP_PFSOC_MMUART1_IRQ = 91,
MICROCHIP_PFSOC_MMUART2_IRQ = 92,
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index cee959a5e0..0b2e9ca175 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -12,6 +12,7 @@
* 1) PLIC (Platform Level Interrupt Controller)
* 2) eNVM (Embedded Non-Volatile Memory)
* 3) MMUARTs (Multi-Mode UART)
+ * 4) Cadence eMMC/SDHC controller and an SD card connected to it
*
* This board currently generates devicetree dynamically that indicates at least
* two harts and up to five harts.
@@ -75,6 +76,7 @@ static const struct MemmapEntry {
[MICROCHIP_PFSOC_MMUART0] = { 0x20000000, 0x1000 },
[MICROCHIP_PFSOC_SYSREG] = { 0x20002000, 0x2000 },
[MICROCHIP_PFSOC_MPUCFG] = { 0x20005000, 0x1000 },
+ [MICROCHIP_PFSOC_EMMC_SD] = { 0x20008000, 0x1000 },
[MICROCHIP_PFSOC_MMUART1] = { 0x20100000, 0x1000 },
[MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 },
[MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 },
@@ -111,6 +113,9 @@ static void microchip_pfsoc_soc_instance_init(Object *obj)
qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type",
TYPE_RISCV_CPU_SIFIVE_U54);
qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", RESET_VECTOR);
+
+ object_initialize_child(obj, "sd-controller", &s->sdhci,
+ TYPE_CADENCE_SDHCI);
}
static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
@@ -223,6 +228,13 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
memmap[MICROCHIP_PFSOC_MPUCFG].base,
memmap[MICROCHIP_PFSOC_MPUCFG].size);
+ /* SDHCI */
+ sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0,
+ memmap[MICROCHIP_PFSOC_EMMC_SD].base);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
+ qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_EMMC_SD_IRQ));
+
/* MMUARTs */
s->serial0 = mchp_pfsoc_mmuart_create(system_memory,
memmap[MICROCHIP_PFSOC_MMUART0].base,
@@ -290,6 +302,7 @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
MicrochipIcicleKitState *s = MICROCHIP_ICICLE_KIT_MACHINE(machine);
MemoryRegion *system_memory = get_system_memory();
MemoryRegion *main_mem = g_new(MemoryRegion, 1);
+ DriveInfo *dinfo = drive_get_next(IF_SD);
/* Sanity check on RAM size */
if (machine->ram_size < mc->default_ram_size) {
@@ -312,6 +325,16 @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
/* Load the firmware */
riscv_find_and_load_firmware(machine, BIOS_FILENAME, RESET_VECTOR, NULL);
+
+ /* Attach an SD card */
+ if (dinfo) {
+ CadenceSDHCIState *sdhci = &(s->soc.sdhci);
+ DeviceState *card = qdev_new(TYPE_SD_CARD);
+
+ qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
+ &error_fatal);
+ qdev_realize_and_unref(card, sdhci->bus, &error_fatal);
+ }
}
static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, void *data)
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index ceb7c166a3..7412db9ad7 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -55,3 +55,4 @@ config MICROCHIP_PFSOC
select SIFIVE
select UNIMP
select MCHP_PFSOC_MMUART
+ select CADENCE_SDHCI
--
2.28.0
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PULL 11/30] hw/dma: Add SiFive platform DMA controller emulation
2020-09-10 18:09 [PULL 00/30] riscv-to-apply queue Alistair Francis
` (9 preceding siblings ...)
2020-09-10 18:09 ` [PULL 10/30] hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card Alistair Francis
@ 2020-09-10 18:09 ` Alistair Francis
2020-09-10 18:09 ` [PULL 12/30] hw/riscv: microchip_pfsoc: Connect a DMA controller Alistair Francis
` (19 subsequent siblings)
30 siblings, 0 replies; 34+ messages in thread
From: Alistair Francis @ 2020-09-10 18:09 UTC (permalink / raw)
To: peter.maydell, qemu-devel; +Cc: alistair23, Bin Meng, Alistair Francis
From: Bin Meng <bin.meng@windriver.com>
Microchip PolarFire SoC integrates a DMA engine that supports:
* Independent concurrent DMA transfers using 4 DMA channels
* Generation of interrupts on various conditions during execution
which is actually an IP reused from the SiFive FU540 chip.
This creates a model to support both polling and interrupt modes.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-10-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/dma/sifive_pdma.h | 57 +++++++
hw/dma/sifive_pdma.c | 313 +++++++++++++++++++++++++++++++++++
hw/dma/Kconfig | 3 +
hw/dma/meson.build | 1 +
4 files changed, 374 insertions(+)
create mode 100644 include/hw/dma/sifive_pdma.h
create mode 100644 hw/dma/sifive_pdma.c
diff --git a/include/hw/dma/sifive_pdma.h b/include/hw/dma/sifive_pdma.h
new file mode 100644
index 0000000000..e319bbd6c4
--- /dev/null
+++ b/include/hw/dma/sifive_pdma.h
@@ -0,0 +1,57 @@
+/*
+ * SiFive Platform DMA emulation
+ *
+ * Copyright (c) 2020 Wind River Systems, Inc.
+ *
+ * Author:
+ * Bin Meng <bin.meng@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 or
+ * (at your option) version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef SIFIVE_PDMA_H
+#define SIFIVE_PDMA_H
+
+struct sifive_pdma_chan {
+ uint32_t control;
+ uint32_t next_config;
+ uint64_t next_bytes;
+ uint64_t next_dst;
+ uint64_t next_src;
+ uint32_t exec_config;
+ uint64_t exec_bytes;
+ uint64_t exec_dst;
+ uint64_t exec_src;
+ int state;
+};
+
+#define SIFIVE_PDMA_CHANS 4
+#define SIFIVE_PDMA_IRQS (SIFIVE_PDMA_CHANS * 2)
+#define SIFIVE_PDMA_REG_SIZE 0x100000
+#define SIFIVE_PDMA_CHAN_NO(reg) ((reg & (SIFIVE_PDMA_REG_SIZE - 1)) >> 12)
+
+typedef struct SiFivePDMAState {
+ SysBusDevice parent;
+ MemoryRegion iomem;
+ qemu_irq irq[SIFIVE_PDMA_IRQS];
+
+ struct sifive_pdma_chan chan[SIFIVE_PDMA_CHANS];
+} SiFivePDMAState;
+
+#define TYPE_SIFIVE_PDMA "sifive.pdma"
+
+#define SIFIVE_PDMA(obj) \
+ OBJECT_CHECK(SiFivePDMAState, (obj), TYPE_SIFIVE_PDMA)
+
+#endif /* SIFIVE_PDMA_H */
diff --git a/hw/dma/sifive_pdma.c b/hw/dma/sifive_pdma.c
new file mode 100644
index 0000000000..e1f6fedbda
--- /dev/null
+++ b/hw/dma/sifive_pdma.c
@@ -0,0 +1,313 @@
+/*
+ * SiFive Platform DMA emulation
+ *
+ * Copyright (c) 2020 Wind River Systems, Inc.
+ *
+ * Author:
+ * Bin Meng <bin.meng@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 or
+ * (at your option) version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/bitops.h"
+#include "qemu/log.h"
+#include "qapi/error.h"
+#include "hw/hw.h"
+#include "hw/irq.h"
+#include "hw/qdev-properties.h"
+#include "hw/sysbus.h"
+#include "migration/vmstate.h"
+#include "sysemu/dma.h"
+#include "hw/dma/sifive_pdma.h"
+
+#define DMA_CONTROL 0x000
+#define CONTROL_CLAIM BIT(0)
+#define CONTROL_RUN BIT(1)
+#define CONTROL_DONE_IE BIT(14)
+#define CONTROL_ERR_IE BIT(15)
+#define CONTROL_DONE BIT(30)
+#define CONTROL_ERR BIT(31)
+
+#define DMA_NEXT_CONFIG 0x004
+#define CONFIG_REPEAT BIT(2)
+#define CONFIG_ORDER BIT(3)
+#define CONFIG_WRSZ_SHIFT 24
+#define CONFIG_RDSZ_SHIFT 28
+#define CONFIG_SZ_MASK 0xf
+
+#define DMA_NEXT_BYTES 0x008
+#define DMA_NEXT_DST 0x010
+#define DMA_NEXT_SRC 0x018
+#define DMA_EXEC_CONFIG 0x104
+#define DMA_EXEC_BYTES 0x108
+#define DMA_EXEC_DST 0x110
+#define DMA_EXEC_SRC 0x118
+
+enum dma_chan_state {
+ DMA_CHAN_STATE_IDLE,
+ DMA_CHAN_STATE_STARTED,
+ DMA_CHAN_STATE_ERROR,
+ DMA_CHAN_STATE_DONE
+};
+
+static void sifive_pdma_run(SiFivePDMAState *s, int ch)
+{
+ uint64_t bytes = s->chan[ch].next_bytes;
+ uint64_t dst = s->chan[ch].next_dst;
+ uint64_t src = s->chan[ch].next_src;
+ uint32_t config = s->chan[ch].next_config;
+ int wsize, rsize, size;
+ uint8_t buf[64];
+ int n;
+
+ /* do nothing if bytes to transfer is zero */
+ if (!bytes) {
+ goto error;
+ }
+
+ /*
+ * The manual does not describe how the hardware behaviors when
+ * config.wsize and config.rsize are given different values.
+ * A common case is memory to memory DMA, and in this case they
+ * are normally the same. Abort if this expectation fails.
+ */
+ wsize = (config >> CONFIG_WRSZ_SHIFT) & CONFIG_SZ_MASK;
+ rsize = (config >> CONFIG_RDSZ_SHIFT) & CONFIG_SZ_MASK;
+ if (wsize != rsize) {
+ goto error;
+ }
+
+ /*
+ * Calculate the transaction size
+ *
+ * size field is base 2 logarithm of DMA transaction size,
+ * but there is an upper limit of 64 bytes per transaction.
+ */
+ size = wsize;
+ if (size > 6) {
+ size = 6;
+ }
+ size = 1 << size;
+
+ /* the bytes to transfer should be multiple of transaction size */
+ if (bytes % size) {
+ goto error;
+ }
+
+ /* indicate a DMA transfer is started */
+ s->chan[ch].state = DMA_CHAN_STATE_STARTED;
+ s->chan[ch].control &= ~CONTROL_DONE;
+ s->chan[ch].control &= ~CONTROL_ERR;
+
+ /* load the next_ registers into their exec_ counterparts */
+ s->chan[ch].exec_config = config;
+ s->chan[ch].exec_bytes = bytes;
+ s->chan[ch].exec_dst = dst;
+ s->chan[ch].exec_src = src;
+
+ for (n = 0; n < bytes / size; n++) {
+ cpu_physical_memory_read(s->chan[ch].exec_src, buf, size);
+ cpu_physical_memory_write(s->chan[ch].exec_dst, buf, size);
+ s->chan[ch].exec_src += size;
+ s->chan[ch].exec_dst += size;
+ s->chan[ch].exec_bytes -= size;
+ }
+
+ /* indicate a DMA transfer is done */
+ s->chan[ch].state = DMA_CHAN_STATE_DONE;
+ s->chan[ch].control &= ~CONTROL_RUN;
+ s->chan[ch].control |= CONTROL_DONE;
+
+ /* reload exec_ registers if repeat is required */
+ if (s->chan[ch].next_config & CONFIG_REPEAT) {
+ s->chan[ch].exec_bytes = bytes;
+ s->chan[ch].exec_dst = dst;
+ s->chan[ch].exec_src = src;
+ }
+
+ return;
+
+error:
+ s->chan[ch].state = DMA_CHAN_STATE_ERROR;
+ s->chan[ch].control |= CONTROL_ERR;
+ return;
+}
+
+static inline void sifive_pdma_update_irq(SiFivePDMAState *s, int ch)
+{
+ bool done_ie, err_ie;
+
+ done_ie = !!(s->chan[ch].control & CONTROL_DONE_IE);
+ err_ie = !!(s->chan[ch].control & CONTROL_ERR_IE);
+
+ if (done_ie && (s->chan[ch].control & CONTROL_DONE)) {
+ qemu_irq_raise(s->irq[ch * 2]);
+ } else {
+ qemu_irq_lower(s->irq[ch * 2]);
+ }
+
+ if (err_ie && (s->chan[ch].control & CONTROL_ERR)) {
+ qemu_irq_raise(s->irq[ch * 2 + 1]);
+ } else {
+ qemu_irq_lower(s->irq[ch * 2 + 1]);
+ }
+
+ s->chan[ch].state = DMA_CHAN_STATE_IDLE;
+}
+
+static uint64_t sifive_pdma_read(void *opaque, hwaddr offset, unsigned size)
+{
+ SiFivePDMAState *s = opaque;
+ int ch = SIFIVE_PDMA_CHAN_NO(offset);
+ uint64_t val = 0;
+
+ if (ch >= SIFIVE_PDMA_CHANS) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid channel no %d\n",
+ __func__, ch);
+ return 0;
+ }
+
+ offset &= 0xfff;
+ switch (offset) {
+ case DMA_CONTROL:
+ val = s->chan[ch].control;
+ break;
+ case DMA_NEXT_CONFIG:
+ val = s->chan[ch].next_config;
+ break;
+ case DMA_NEXT_BYTES:
+ val = s->chan[ch].next_bytes;
+ break;
+ case DMA_NEXT_DST:
+ val = s->chan[ch].next_dst;
+ break;
+ case DMA_NEXT_SRC:
+ val = s->chan[ch].next_src;
+ break;
+ case DMA_EXEC_CONFIG:
+ val = s->chan[ch].exec_config;
+ break;
+ case DMA_EXEC_BYTES:
+ val = s->chan[ch].exec_bytes;
+ break;
+ case DMA_EXEC_DST:
+ val = s->chan[ch].exec_dst;
+ break;
+ case DMA_EXEC_SRC:
+ val = s->chan[ch].exec_src;
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
+ __func__, offset);
+ break;
+ }
+
+ return val;
+}
+
+static void sifive_pdma_write(void *opaque, hwaddr offset,
+ uint64_t value, unsigned size)
+{
+ SiFivePDMAState *s = opaque;
+ int ch = SIFIVE_PDMA_CHAN_NO(offset);
+
+ if (ch >= SIFIVE_PDMA_CHANS) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid channel no %d\n",
+ __func__, ch);
+ return;
+ }
+
+ offset &= 0xfff;
+ switch (offset) {
+ case DMA_CONTROL:
+ s->chan[ch].control = value;
+
+ if (value & CONTROL_RUN) {
+ sifive_pdma_run(s, ch);
+ }
+
+ sifive_pdma_update_irq(s, ch);
+ break;
+ case DMA_NEXT_CONFIG:
+ s->chan[ch].next_config = value;
+ break;
+ case DMA_NEXT_BYTES:
+ s->chan[ch].next_bytes = value;
+ break;
+ case DMA_NEXT_DST:
+ s->chan[ch].next_dst = value;
+ break;
+ case DMA_NEXT_SRC:
+ s->chan[ch].next_src = value;
+ break;
+ case DMA_EXEC_CONFIG:
+ case DMA_EXEC_BYTES:
+ case DMA_EXEC_DST:
+ case DMA_EXEC_SRC:
+ /* these are read-only registers */
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
+ __func__, offset);
+ break;
+ }
+}
+
+static const MemoryRegionOps sifive_pdma_ops = {
+ .read = sifive_pdma_read,
+ .write = sifive_pdma_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ /* there are 32-bit and 64-bit wide registers */
+ .impl = {
+ .min_access_size = 4,
+ .max_access_size = 8,
+ }
+};
+
+static void sifive_pdma_realize(DeviceState *dev, Error **errp)
+{
+ SiFivePDMAState *s = SIFIVE_PDMA(dev);
+ int i;
+
+ memory_region_init_io(&s->iomem, OBJECT(dev), &sifive_pdma_ops, s,
+ TYPE_SIFIVE_PDMA, SIFIVE_PDMA_REG_SIZE);
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
+
+ for (i = 0; i < SIFIVE_PDMA_IRQS; i++) {
+ sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]);
+ }
+}
+
+static void sifive_pdma_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->desc = "SiFive Platform DMA controller";
+ dc->realize = sifive_pdma_realize;
+}
+
+static const TypeInfo sifive_pdma_info = {
+ .name = TYPE_SIFIVE_PDMA,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(SiFivePDMAState),
+ .class_init = sifive_pdma_class_init,
+};
+
+static void sifive_pdma_register_types(void)
+{
+ type_register_static(&sifive_pdma_info);
+}
+
+type_init(sifive_pdma_register_types)
diff --git a/hw/dma/Kconfig b/hw/dma/Kconfig
index 5c61b67bc0..d67492d36c 100644
--- a/hw/dma/Kconfig
+++ b/hw/dma/Kconfig
@@ -20,3 +20,6 @@ config ZYNQ_DEVCFG
config STP2000
bool
+
+config SIFIVE_PDMA
+ bool
diff --git a/hw/dma/meson.build b/hw/dma/meson.build
index ff5bb3748f..b991d7698c 100644
--- a/hw/dma/meson.build
+++ b/hw/dma/meson.build
@@ -13,3 +13,4 @@ softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zdma.c'))
softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_dma.c', 'soc_dma.c'))
softmmu_ss.add(when: 'CONFIG_PXA2XX', if_true: files('pxa2xx_dma.c'))
softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_dma.c'))
+softmmu_ss.add(when: 'CONFIG_SIFIVE_PDMA', if_true: files('sifive_pdma.c'))
--
2.28.0
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PULL 12/30] hw/riscv: microchip_pfsoc: Connect a DMA controller
2020-09-10 18:09 [PULL 00/30] riscv-to-apply queue Alistair Francis
` (10 preceding siblings ...)
2020-09-10 18:09 ` [PULL 11/30] hw/dma: Add SiFive platform DMA controller emulation Alistair Francis
@ 2020-09-10 18:09 ` Alistair Francis
2020-09-10 18:09 ` [PULL 13/30] hw/net: cadence_gem: Add a new 'phy-addr' property Alistair Francis
` (18 subsequent siblings)
30 siblings, 0 replies; 34+ messages in thread
From: Alistair Francis @ 2020-09-10 18:09 UTC (permalink / raw)
To: peter.maydell, qemu-devel; +Cc: alistair23, Bin Meng, Alistair Francis
From: Bin Meng <bin.meng@windriver.com>
On the Icicle Kit board, the HSS firmware utilizes the on-chip DMA
controller to move the 2nd stage bootloader in the system memory.
Let's connect a DMA controller to Microchip PolarFire SoC.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-11-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/microchip_pfsoc.h | 11 +++++++++++
hw/riscv/microchip_pfsoc.c | 15 +++++++++++++++
hw/riscv/Kconfig | 1 +
3 files changed, 27 insertions(+)
diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
index d810ee8484..63e786052a 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -23,6 +23,7 @@
#define HW_MICROCHIP_PFSOC_H
#include "hw/char/mchp_pfsoc_mmuart.h"
+#include "hw/dma/sifive_pdma.h"
#include "hw/sd/cadence_sdhci.h"
typedef struct MicrochipPFSoCState {
@@ -40,6 +41,7 @@ typedef struct MicrochipPFSoCState {
MchpPfSoCMMUartState *serial2;
MchpPfSoCMMUartState *serial3;
MchpPfSoCMMUartState *serial4;
+ SiFivePDMAState dma;
CadenceSDHCIState sdhci;
} MicrochipPFSoCState;
@@ -71,6 +73,7 @@ enum {
MICROCHIP_PFSOC_BUSERR_UNIT4,
MICROCHIP_PFSOC_CLINT,
MICROCHIP_PFSOC_L2CC,
+ MICROCHIP_PFSOC_DMA,
MICROCHIP_PFSOC_L2LIM,
MICROCHIP_PFSOC_PLIC,
MICROCHIP_PFSOC_MMUART0,
@@ -88,6 +91,14 @@ enum {
};
enum {
+ MICROCHIP_PFSOC_DMA_IRQ0 = 5,
+ MICROCHIP_PFSOC_DMA_IRQ1 = 6,
+ MICROCHIP_PFSOC_DMA_IRQ2 = 7,
+ MICROCHIP_PFSOC_DMA_IRQ3 = 8,
+ MICROCHIP_PFSOC_DMA_IRQ4 = 9,
+ MICROCHIP_PFSOC_DMA_IRQ5 = 10,
+ MICROCHIP_PFSOC_DMA_IRQ6 = 11,
+ MICROCHIP_PFSOC_DMA_IRQ7 = 12,
MICROCHIP_PFSOC_EMMC_SD_IRQ = 88,
MICROCHIP_PFSOC_MMUART0_IRQ = 90,
MICROCHIP_PFSOC_MMUART1_IRQ = 91,
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index 0b2e9ca175..d8ec973958 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -13,6 +13,7 @@
* 2) eNVM (Embedded Non-Volatile Memory)
* 3) MMUARTs (Multi-Mode UART)
* 4) Cadence eMMC/SDHC controller and an SD card connected to it
+ * 5) SiFive Platform DMA (Direct Memory Access Controller)
*
* This board currently generates devicetree dynamically that indicates at least
* two harts and up to five harts.
@@ -71,6 +72,7 @@ static const struct MemmapEntry {
[MICROCHIP_PFSOC_BUSERR_UNIT4] = { 0x1704000, 0x1000 },
[MICROCHIP_PFSOC_CLINT] = { 0x2000000, 0x10000 },
[MICROCHIP_PFSOC_L2CC] = { 0x2010000, 0x1000 },
+ [MICROCHIP_PFSOC_DMA] = { 0x3000000, 0x100000 },
[MICROCHIP_PFSOC_L2LIM] = { 0x8000000, 0x2000000 },
[MICROCHIP_PFSOC_PLIC] = { 0xc000000, 0x4000000 },
[MICROCHIP_PFSOC_MMUART0] = { 0x20000000, 0x1000 },
@@ -114,6 +116,9 @@ static void microchip_pfsoc_soc_instance_init(Object *obj)
TYPE_RISCV_CPU_SIFIVE_U54);
qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", RESET_VECTOR);
+ object_initialize_child(obj, "dma-controller", &s->dma,
+ TYPE_SIFIVE_PDMA);
+
object_initialize_child(obj, "sd-controller", &s->sdhci,
TYPE_CADENCE_SDHCI);
}
@@ -218,6 +223,16 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
memmap[MICROCHIP_PFSOC_PLIC].size);
g_free(plic_hart_config);
+ /* DMA */
+ sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0,
+ memmap[MICROCHIP_PFSOC_DMA].base);
+ for (i = 0; i < SIFIVE_PDMA_IRQS; i++) {
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i,
+ qdev_get_gpio_in(DEVICE(s->plic),
+ MICROCHIP_PFSOC_DMA_IRQ0 + i));
+ }
+
/* SYSREG */
create_unimplemented_device("microchip.pfsoc.sysreg",
memmap[MICROCHIP_PFSOC_SYSREG].base,
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index 7412db9ad7..9032cb0cbd 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -55,4 +55,5 @@ config MICROCHIP_PFSOC
select SIFIVE
select UNIMP
select MCHP_PFSOC_MMUART
+ select SIFIVE_PDMA
select CADENCE_SDHCI
--
2.28.0
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PULL 13/30] hw/net: cadence_gem: Add a new 'phy-addr' property
2020-09-10 18:09 [PULL 00/30] riscv-to-apply queue Alistair Francis
` (11 preceding siblings ...)
2020-09-10 18:09 ` [PULL 12/30] hw/riscv: microchip_pfsoc: Connect a DMA controller Alistair Francis
@ 2020-09-10 18:09 ` Alistair Francis
2020-09-10 18:09 ` [PULL 14/30] hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23 Alistair Francis
` (17 subsequent siblings)
30 siblings, 0 replies; 34+ messages in thread
From: Alistair Francis @ 2020-09-10 18:09 UTC (permalink / raw)
To: peter.maydell, qemu-devel
Cc: Edgar E . Iglesias, alistair23, Bin Meng, Alistair Francis,
Philippe Mathieu-Daudé
From: Bin Meng <bin.meng@windriver.com>
At present the PHY address of the PHY connected to GEM is hard-coded
to either 23 (BOARD_PHY_ADDRESS) or 0. This might not be the case for
all boards. Add a new 'phy-addr' property so that board can specify
the PHY address for each GEM instance.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-12-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/net/cadence_gem.h | 2 ++
hw/net/cadence_gem.c | 5 +++--
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h
index 54e646ff79..01c6189a24 100644
--- a/include/hw/net/cadence_gem.h
+++ b/include/hw/net/cadence_gem.h
@@ -73,6 +73,8 @@ typedef struct CadenceGEMState {
/* Mask of register bits which are write 1 to clear */
uint32_t regs_w1c[CADENCE_GEM_MAXREG];
+ /* PHY address */
+ uint8_t phy_addr;
/* PHY registers backing store */
uint16_t phy_regs[32];
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index a93b5c07ce..d80096bbe8 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -1446,7 +1446,7 @@ static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size)
uint32_t phy_addr, reg_num;
phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
- if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) {
+ if (phy_addr == s->phy_addr || phy_addr == 0) {
reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
retval &= 0xFFFF0000;
retval |= gem_phy_read(s, reg_num);
@@ -1569,7 +1569,7 @@ static void gem_write(void *opaque, hwaddr offset, uint64_t val,
uint32_t phy_addr, reg_num;
phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
- if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) {
+ if (phy_addr == s->phy_addr || phy_addr == 0) {
reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
gem_phy_write(s, reg_num, val);
}
@@ -1682,6 +1682,7 @@ static Property gem_properties[] = {
DEFINE_NIC_PROPERTIES(CadenceGEMState, conf),
DEFINE_PROP_UINT32("revision", CadenceGEMState, revision,
GEM_MODID_VALUE),
+ DEFINE_PROP_UINT8("phy-addr", CadenceGEMState, phy_addr, BOARD_PHY_ADDRESS),
DEFINE_PROP_UINT8("num-priority-queues", CadenceGEMState,
num_priority_queues, 1),
DEFINE_PROP_UINT8("num-type1-screeners", CadenceGEMState,
--
2.28.0
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PULL 14/30] hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23
2020-09-10 18:09 [PULL 00/30] riscv-to-apply queue Alistair Francis
` (12 preceding siblings ...)
2020-09-10 18:09 ` [PULL 13/30] hw/net: cadence_gem: Add a new 'phy-addr' property Alistair Francis
@ 2020-09-10 18:09 ` Alistair Francis
2020-09-10 18:09 ` [PULL 15/30] hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs Alistair Francis
` (16 subsequent siblings)
30 siblings, 0 replies; 34+ messages in thread
From: Alistair Francis @ 2020-09-10 18:09 UTC (permalink / raw)
To: peter.maydell, qemu-devel
Cc: alistair23, Bin Meng, Alistair Francis, Philippe Mathieu-Daudé
From: Bin Meng <bin.meng@windriver.com>
When cadence_gem model was created for Xilinx boards, the PHY address
was hard-coded to 23 in the GEM model. Now that we have introduced a
property we can use that to tell GEM model what our PHY address is.
Change all boards' GEM 'phy-addr' property value to 23, and set the
PHY address default value to 0 in the GEM model.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-13-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/arm/xilinx_zynq.c | 1 +
hw/arm/xlnx-versal.c | 1 +
hw/arm/xlnx-zynqmp.c | 2 ++
hw/net/cadence_gem.c | 6 +++---
4 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
index 969ef0727c..9ffcc5606f 100644
--- a/hw/arm/xilinx_zynq.c
+++ b/hw/arm/xilinx_zynq.c
@@ -119,6 +119,7 @@ static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq)
qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
qdev_set_nic_properties(dev, nd);
}
+ object_property_set_int(OBJECT(dev), "phy-addr", 23, &error_abort);
s = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, base);
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index e3aa4bd1e5..12ba6c4eba 100644
--- a/hw/arm/xlnx-versal.c
+++ b/hw/arm/xlnx-versal.c
@@ -165,6 +165,7 @@ static void versal_create_gems(Versal *s, qemu_irq *pic)
qemu_check_nic_model(nd, "cadence_gem");
qdev_set_nic_properties(dev, nd);
}
+ object_property_set_int(OBJECT(dev), "phy-addr", 23, &error_abort);
object_property_set_int(OBJECT(dev), "num-priority-queues", 2,
&error_abort);
object_property_set_link(OBJECT(dev), "dma", OBJECT(&s->mr_ps),
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index c435b9d52a..7885bb1774 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -460,6 +460,8 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
}
object_property_set_int(OBJECT(&s->gem[i]), "revision", GEM_REVISION,
&error_abort);
+ object_property_set_int(OBJECT(&s->gem[i]), "phy-addr", 23,
+ &error_abort);
object_property_set_int(OBJECT(&s->gem[i]), "num-priority-queues", 2,
&error_abort);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem[i]), errp)) {
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index d80096bbe8..7a534691f1 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -250,7 +250,7 @@
#define GEM_PHYMNTNC_REG_SHIFT 18
/* Marvell PHY definitions */
-#define BOARD_PHY_ADDRESS 23 /* PHY address we will emulate a device at */
+#define BOARD_PHY_ADDRESS 0 /* PHY address we will emulate a device at */
#define PHY_REG_CONTROL 0
#define PHY_REG_STATUS 1
@@ -1446,7 +1446,7 @@ static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size)
uint32_t phy_addr, reg_num;
phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
- if (phy_addr == s->phy_addr || phy_addr == 0) {
+ if (phy_addr == s->phy_addr) {
reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
retval &= 0xFFFF0000;
retval |= gem_phy_read(s, reg_num);
@@ -1569,7 +1569,7 @@ static void gem_write(void *opaque, hwaddr offset, uint64_t val,
uint32_t phy_addr, reg_num;
phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
- if (phy_addr == s->phy_addr || phy_addr == 0) {
+ if (phy_addr == s->phy_addr) {
reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
gem_phy_write(s, reg_num, val);
}
--
2.28.0
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PULL 15/30] hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs
2020-09-10 18:09 [PULL 00/30] riscv-to-apply queue Alistair Francis
` (13 preceding siblings ...)
2020-09-10 18:09 ` [PULL 14/30] hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23 Alistair Francis
@ 2020-09-10 18:09 ` Alistair Francis
2020-09-10 18:09 ` [PULL 16/30] hw/riscv: microchip_pfsoc: Hook GPIO controllers Alistair Francis
` (15 subsequent siblings)
30 siblings, 0 replies; 34+ messages in thread
From: Alistair Francis @ 2020-09-10 18:09 UTC (permalink / raw)
To: peter.maydell, qemu-devel
Cc: alistair23, Bin Meng, Alistair Francis, Philippe Mathieu-Daudé
From: Bin Meng <bin.meng@windriver.com>
Microchip PolarFire SoC integrates 2 Candence GEMs to provide
IEEE 802.3 standard-compliant 10/100/1000 Mbps ethernet interface.
On the Icicle Kit board, GEM0 connects to a PHY at address 8 while
GEM1 connects to a PHY at address 9.
The 2nd stage bootloader (U-Boot) is using GEM1 by default, so we
must specify 2 '-nic' options from the command line in order to get
a working ethernet.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <1598924352-89526-14-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/microchip_pfsoc.h | 7 ++++++
hw/riscv/microchip_pfsoc.c | 39 ++++++++++++++++++++++++++++++
2 files changed, 46 insertions(+)
diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
index 63e786052a..6d20853039 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -24,6 +24,7 @@
#include "hw/char/mchp_pfsoc_mmuart.h"
#include "hw/dma/sifive_pdma.h"
+#include "hw/net/cadence_gem.h"
#include "hw/sd/cadence_sdhci.h"
typedef struct MicrochipPFSoCState {
@@ -42,6 +43,8 @@ typedef struct MicrochipPFSoCState {
MchpPfSoCMMUartState *serial3;
MchpPfSoCMMUartState *serial4;
SiFivePDMAState dma;
+ CadenceGEMState gem0;
+ CadenceGEMState gem1;
CadenceSDHCIState sdhci;
} MicrochipPFSoCState;
@@ -84,6 +87,8 @@ enum {
MICROCHIP_PFSOC_MMUART2,
MICROCHIP_PFSOC_MMUART3,
MICROCHIP_PFSOC_MMUART4,
+ MICROCHIP_PFSOC_GEM0,
+ MICROCHIP_PFSOC_GEM1,
MICROCHIP_PFSOC_ENVM_CFG,
MICROCHIP_PFSOC_ENVM_DATA,
MICROCHIP_PFSOC_IOSCB_CFG,
@@ -99,6 +104,8 @@ enum {
MICROCHIP_PFSOC_DMA_IRQ5 = 10,
MICROCHIP_PFSOC_DMA_IRQ6 = 11,
MICROCHIP_PFSOC_DMA_IRQ7 = 12,
+ MICROCHIP_PFSOC_GEM0_IRQ = 64,
+ MICROCHIP_PFSOC_GEM1_IRQ = 70,
MICROCHIP_PFSOC_EMMC_SD_IRQ = 88,
MICROCHIP_PFSOC_MMUART0_IRQ = 90,
MICROCHIP_PFSOC_MMUART1_IRQ = 91,
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index d8ec973958..7f25609182 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -14,6 +14,7 @@
* 3) MMUARTs (Multi-Mode UART)
* 4) Cadence eMMC/SDHC controller and an SD card connected to it
* 5) SiFive Platform DMA (Direct Memory Access Controller)
+ * 6) GEM (Gigabit Ethernet MAC Controller)
*
* This board currently generates devicetree dynamically that indicates at least
* two harts and up to five harts.
@@ -59,6 +60,9 @@
#define BIOS_FILENAME "hss.bin"
#define RESET_VECTOR 0x20220000
+/* GEM version */
+#define GEM_REVISION 0x0107010c
+
static const struct MemmapEntry {
hwaddr base;
hwaddr size;
@@ -83,6 +87,8 @@ static const struct MemmapEntry {
[MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 },
[MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 },
[MICROCHIP_PFSOC_MMUART4] = { 0x20106000, 0x1000 },
+ [MICROCHIP_PFSOC_GEM0] = { 0x20110000, 0x2000 },
+ [MICROCHIP_PFSOC_GEM1] = { 0x20112000, 0x2000 },
[MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 },
[MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 },
[MICROCHIP_PFSOC_IOSCB_CFG] = { 0x37080000, 0x1000 },
@@ -119,6 +125,9 @@ static void microchip_pfsoc_soc_instance_init(Object *obj)
object_initialize_child(obj, "dma-controller", &s->dma,
TYPE_SIFIVE_PDMA);
+ object_initialize_child(obj, "gem0", &s->gem0, TYPE_CADENCE_GEM);
+ object_initialize_child(obj, "gem1", &s->gem1, TYPE_CADENCE_GEM);
+
object_initialize_child(obj, "sd-controller", &s->sdhci,
TYPE_CADENCE_SDHCI);
}
@@ -134,6 +143,7 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
MemoryRegion *envm_data = g_new(MemoryRegion, 1);
char *plic_hart_config;
size_t plic_hart_config_len;
+ NICInfo *nd;
int i;
sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort);
@@ -272,6 +282,35 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART4_IRQ),
serial_hd(4));
+ /* GEMs */
+
+ nd = &nd_table[0];
+ if (nd->used) {
+ qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
+ qdev_set_nic_properties(DEVICE(&s->gem0), nd);
+ }
+ nd = &nd_table[1];
+ if (nd->used) {
+ qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
+ qdev_set_nic_properties(DEVICE(&s->gem1), nd);
+ }
+
+ object_property_set_int(OBJECT(&s->gem0), "revision", GEM_REVISION, errp);
+ object_property_set_int(OBJECT(&s->gem0), "phy-addr", 8, errp);
+ sysbus_realize(SYS_BUS_DEVICE(&s->gem0), errp);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem0), 0,
+ memmap[MICROCHIP_PFSOC_GEM0].base);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem0), 0,
+ qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM0_IRQ));
+
+ object_property_set_int(OBJECT(&s->gem1), "revision", GEM_REVISION, errp);
+ object_property_set_int(OBJECT(&s->gem1), "phy-addr", 9, errp);
+ sysbus_realize(SYS_BUS_DEVICE(&s->gem1), errp);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem1), 0,
+ memmap[MICROCHIP_PFSOC_GEM1].base);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem1), 0,
+ qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM1_IRQ));
+
/* eNVM */
memory_region_init_rom(envm_data, OBJECT(dev), "microchip.pfsoc.envm.data",
memmap[MICROCHIP_PFSOC_ENVM_DATA].size,
--
2.28.0
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PULL 16/30] hw/riscv: microchip_pfsoc: Hook GPIO controllers
2020-09-10 18:09 [PULL 00/30] riscv-to-apply queue Alistair Francis
` (14 preceding siblings ...)
2020-09-10 18:09 ` [PULL 15/30] hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs Alistair Francis
@ 2020-09-10 18:09 ` Alistair Francis
2020-09-10 18:09 ` [PULL 17/30] hw/riscv: clint: Avoid using hard-coded timebase frequency Alistair Francis
` (14 subsequent siblings)
30 siblings, 0 replies; 34+ messages in thread
From: Alistair Francis @ 2020-09-10 18:09 UTC (permalink / raw)
To: peter.maydell, qemu-devel
Cc: alistair23, Bin Meng, Alistair Francis, Philippe Mathieu-Daudé
From: Bin Meng <bin.meng@windriver.com>
Microchip PolarFire SoC integrates 3 GPIOs controllers. It seems
enough to create unimplemented devices to cover their register
spaces at this point.
With this commit, QEMU can boot to U-Boot (2nd stage bootloader)
all the way to the Linux shell login prompt, with a modified HSS
(1st stage bootloader).
For detailed instructions on how to create images for the Icicle
Kit board, please check QEMU RISC-V WiKi page at:
https://wiki.qemu.org/Documentation/Platforms/RISCV
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <1598924352-89526-15-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/microchip_pfsoc.h | 3 +++
hw/riscv/microchip_pfsoc.c | 14 ++++++++++++++
2 files changed, 17 insertions(+)
diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
index 6d20853039..8bfc7e1a85 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -89,6 +89,9 @@ enum {
MICROCHIP_PFSOC_MMUART4,
MICROCHIP_PFSOC_GEM0,
MICROCHIP_PFSOC_GEM1,
+ MICROCHIP_PFSOC_GPIO0,
+ MICROCHIP_PFSOC_GPIO1,
+ MICROCHIP_PFSOC_GPIO2,
MICROCHIP_PFSOC_ENVM_CFG,
MICROCHIP_PFSOC_ENVM_DATA,
MICROCHIP_PFSOC_IOSCB_CFG,
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index 7f25609182..11ebdd1aa8 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -89,6 +89,9 @@ static const struct MemmapEntry {
[MICROCHIP_PFSOC_MMUART4] = { 0x20106000, 0x1000 },
[MICROCHIP_PFSOC_GEM0] = { 0x20110000, 0x2000 },
[MICROCHIP_PFSOC_GEM1] = { 0x20112000, 0x2000 },
+ [MICROCHIP_PFSOC_GPIO0] = { 0x20120000, 0x1000 },
+ [MICROCHIP_PFSOC_GPIO1] = { 0x20121000, 0x1000 },
+ [MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 },
[MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 },
[MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 },
[MICROCHIP_PFSOC_IOSCB_CFG] = { 0x37080000, 0x1000 },
@@ -311,6 +314,17 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem1), 0,
qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM1_IRQ));
+ /* GPIOs */
+ create_unimplemented_device("microchip.pfsoc.gpio0",
+ memmap[MICROCHIP_PFSOC_GPIO0].base,
+ memmap[MICROCHIP_PFSOC_GPIO0].size);
+ create_unimplemented_device("microchip.pfsoc.gpio1",
+ memmap[MICROCHIP_PFSOC_GPIO1].base,
+ memmap[MICROCHIP_PFSOC_GPIO1].size);
+ create_unimplemented_device("microchip.pfsoc.gpio2",
+ memmap[MICROCHIP_PFSOC_GPIO2].base,
+ memmap[MICROCHIP_PFSOC_GPIO2].size);
+
/* eNVM */
memory_region_init_rom(envm_data, OBJECT(dev), "microchip.pfsoc.envm.data",
memmap[MICROCHIP_PFSOC_ENVM_DATA].size,
--
2.28.0
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PULL 17/30] hw/riscv: clint: Avoid using hard-coded timebase frequency
2020-09-10 18:09 [PULL 00/30] riscv-to-apply queue Alistair Francis
` (15 preceding siblings ...)
2020-09-10 18:09 ` [PULL 16/30] hw/riscv: microchip_pfsoc: Hook GPIO controllers Alistair Francis
@ 2020-09-10 18:09 ` Alistair Francis
2020-09-10 18:09 ` [PULL 18/30] hw/riscv: sifive_u: Connect a DMA controller Alistair Francis
` (13 subsequent siblings)
30 siblings, 0 replies; 34+ messages in thread
From: Alistair Francis @ 2020-09-10 18:09 UTC (permalink / raw)
To: peter.maydell, qemu-devel; +Cc: alistair23, Bin Meng, Alistair Francis
From: Bin Meng <bin.meng@windriver.com>
At present the CLINT timestamp is using a hard-coded timebase
frequency value SIFIVE_CLINT_TIMEBASE_FREQ. This might not be
true for all boards.
Add a new 'timebase-freq' property to the CLINT device, and
update various functions to accept this as a parameter.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-16-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/sifive_clint.h | 4 +++-
target/riscv/cpu.h | 6 ++++--
hw/riscv/microchip_pfsoc.c | 6 +++++-
hw/riscv/sifive_clint.c | 26 +++++++++++++++-----------
hw/riscv/sifive_e.c | 3 ++-
hw/riscv/sifive_u.c | 3 ++-
hw/riscv/spike.c | 3 ++-
hw/riscv/virt.c | 3 ++-
target/riscv/cpu_helper.c | 4 +++-
target/riscv/csr.c | 4 ++--
10 files changed, 40 insertions(+), 22 deletions(-)
diff --git a/include/hw/riscv/sifive_clint.h b/include/hw/riscv/sifive_clint.h
index 9f5fb3d31d..a30be0f3d6 100644
--- a/include/hw/riscv/sifive_clint.h
+++ b/include/hw/riscv/sifive_clint.h
@@ -39,11 +39,13 @@ typedef struct SiFiveCLINTState {
uint32_t timecmp_base;
uint32_t time_base;
uint32_t aperture_size;
+ uint32_t timebase_freq;
} SiFiveCLINTState;
DeviceState *sifive_clint_create(hwaddr addr, hwaddr size,
uint32_t hartid_base, uint32_t num_harts, uint32_t sip_base,
- uint32_t timecmp_base, uint32_t time_base, bool provide_rdtime);
+ uint32_t timecmp_base, uint32_t time_base, uint32_t timebase_freq,
+ bool provide_rdtime);
enum {
SIFIVE_SIP_BASE = 0x0,
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 0d1728a8cd..65daa73675 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -219,7 +219,8 @@ struct CPURISCVState {
pmp_table_t pmp_state;
/* machine specific rdtime callback */
- uint64_t (*rdtime_fn)(void);
+ uint64_t (*rdtime_fn)(uint32_t);
+ uint32_t rdtime_fn_arg;
/* True if in debugger mode. */
bool debugger;
@@ -350,7 +351,8 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);
int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts);
uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
#define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
-void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void));
+void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t),
+ uint32_t arg);
#endif
void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index 11ebdd1aa8..da6bd295ce 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -60,6 +60,9 @@
#define BIOS_FILENAME "hss.bin"
#define RESET_VECTOR 0x20220000
+/* CLINT timebase frequency */
+#define CLINT_TIMEBASE_FREQ 1000000
+
/* GEM version */
#define GEM_REVISION 0x0107010c
@@ -187,7 +190,8 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
/* CLINT */
sifive_clint_create(memmap[MICROCHIP_PFSOC_CLINT].base,
memmap[MICROCHIP_PFSOC_CLINT].size, 0, ms->smp.cpus,
- SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
+ SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
+ CLINT_TIMEBASE_FREQ, false);
/* L2 cache controller */
create_unimplemented_device("microchip.pfsoc.l2cc",
diff --git a/hw/riscv/sifive_clint.c b/hw/riscv/sifive_clint.c
index 15e13d5f7a..fa1ddf2ccd 100644
--- a/hw/riscv/sifive_clint.c
+++ b/hw/riscv/sifive_clint.c
@@ -29,22 +29,23 @@
#include "hw/riscv/sifive_clint.h"
#include "qemu/timer.h"
-static uint64_t cpu_riscv_read_rtc(void)
+static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq)
{
return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
- SIFIVE_CLINT_TIMEBASE_FREQ, NANOSECONDS_PER_SECOND);
+ timebase_freq, NANOSECONDS_PER_SECOND);
}
/*
* Called when timecmp is written to update the QEMU timer or immediately
* trigger timer interrupt if mtimecmp <= current timer value.
*/
-static void sifive_clint_write_timecmp(RISCVCPU *cpu, uint64_t value)
+static void sifive_clint_write_timecmp(RISCVCPU *cpu, uint64_t value,
+ uint32_t timebase_freq)
{
uint64_t next;
uint64_t diff;
- uint64_t rtc_r = cpu_riscv_read_rtc();
+ uint64_t rtc_r = cpu_riscv_read_rtc(timebase_freq);
cpu->env.timecmp = value;
if (cpu->env.timecmp <= rtc_r) {
@@ -59,7 +60,7 @@ static void sifive_clint_write_timecmp(RISCVCPU *cpu, uint64_t value)
diff = cpu->env.timecmp - rtc_r;
/* back to ns (note args switched in muldiv64) */
next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
- muldiv64(diff, NANOSECONDS_PER_SECOND, SIFIVE_CLINT_TIMEBASE_FREQ);
+ muldiv64(diff, NANOSECONDS_PER_SECOND, timebase_freq);
timer_mod(cpu->env.timer, next);
}
@@ -112,10 +113,10 @@ static uint64_t sifive_clint_read(void *opaque, hwaddr addr, unsigned size)
}
} else if (addr == clint->time_base) {
/* time_lo */
- return cpu_riscv_read_rtc() & 0xFFFFFFFF;
+ return cpu_riscv_read_rtc(clint->timebase_freq) & 0xFFFFFFFF;
} else if (addr == clint->time_base + 4) {
/* time_hi */
- return (cpu_riscv_read_rtc() >> 32) & 0xFFFFFFFF;
+ return (cpu_riscv_read_rtc(clint->timebase_freq) >> 32) & 0xFFFFFFFF;
}
error_report("clint: invalid read: %08x", (uint32_t)addr);
@@ -153,13 +154,13 @@ static void sifive_clint_write(void *opaque, hwaddr addr, uint64_t value,
/* timecmp_lo */
uint64_t timecmp_hi = env->timecmp >> 32;
sifive_clint_write_timecmp(RISCV_CPU(cpu),
- timecmp_hi << 32 | (value & 0xFFFFFFFF));
+ timecmp_hi << 32 | (value & 0xFFFFFFFF), clint->timebase_freq);
return;
} else if ((addr & 0x7) == 4) {
/* timecmp_hi */
uint64_t timecmp_lo = env->timecmp;
sifive_clint_write_timecmp(RISCV_CPU(cpu),
- value << 32 | (timecmp_lo & 0xFFFFFFFF));
+ value << 32 | (timecmp_lo & 0xFFFFFFFF), clint->timebase_freq);
} else {
error_report("clint: invalid timecmp write: %08x", (uint32_t)addr);
}
@@ -194,6 +195,7 @@ static Property sifive_clint_properties[] = {
DEFINE_PROP_UINT32("timecmp-base", SiFiveCLINTState, timecmp_base, 0),
DEFINE_PROP_UINT32("time-base", SiFiveCLINTState, time_base, 0),
DEFINE_PROP_UINT32("aperture-size", SiFiveCLINTState, aperture_size, 0),
+ DEFINE_PROP_UINT32("timebase-freq", SiFiveCLINTState, timebase_freq, 0),
DEFINE_PROP_END_OF_LIST(),
};
@@ -232,7 +234,8 @@ type_init(sifive_clint_register_types)
*/
DeviceState *sifive_clint_create(hwaddr addr, hwaddr size,
uint32_t hartid_base, uint32_t num_harts, uint32_t sip_base,
- uint32_t timecmp_base, uint32_t time_base, bool provide_rdtime)
+ uint32_t timecmp_base, uint32_t time_base, uint32_t timebase_freq,
+ bool provide_rdtime)
{
int i;
for (i = 0; i < num_harts; i++) {
@@ -242,7 +245,7 @@ DeviceState *sifive_clint_create(hwaddr addr, hwaddr size,
continue;
}
if (provide_rdtime) {
- riscv_cpu_set_rdtime_fn(env, cpu_riscv_read_rtc);
+ riscv_cpu_set_rdtime_fn(env, cpu_riscv_read_rtc, timebase_freq);
}
env->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
&sifive_clint_timer_cb, cpu);
@@ -256,6 +259,7 @@ DeviceState *sifive_clint_create(hwaddr addr, hwaddr size,
qdev_prop_set_uint32(dev, "timecmp-base", timecmp_base);
qdev_prop_set_uint32(dev, "time-base", time_base);
qdev_prop_set_uint32(dev, "aperture-size", size);
+ qdev_prop_set_uint32(dev, "timebase-freq", timebase_freq);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
return dev;
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index cd7560d8ec..36ccfb2071 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -213,7 +213,8 @@ static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
memmap[SIFIVE_E_PLIC].size);
sifive_clint_create(memmap[SIFIVE_E_CLINT].base,
memmap[SIFIVE_E_CLINT].size, 0, ms->smp.cpus,
- SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
+ SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
+ SIFIVE_CLINT_TIMEBASE_FREQ, false);
create_unimplemented_device("riscv.sifive.e.aon",
memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size);
sifive_e_prci_create(memmap[SIFIVE_E_PRCI].base);
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 404d5e6918..2bc3992989 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -706,7 +706,8 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ));
sifive_clint_create(memmap[SIFIVE_U_CLINT].base,
memmap[SIFIVE_U_CLINT].size, 0, ms->smp.cpus,
- SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
+ SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
+ SIFIVE_CLINT_TIMEBASE_FREQ, false);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) {
return;
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 56f5fe73c7..b54a396107 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -242,7 +242,8 @@ static void spike_board_init(MachineState *machine)
sifive_clint_create(
memmap[SPIKE_CLINT].base + i * memmap[SPIKE_CLINT].size,
memmap[SPIKE_CLINT].size, base_hartid, hart_count,
- SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
+ SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
+ SIFIVE_CLINT_TIMEBASE_FREQ, false);
}
/* register system main memory (actual RAM) */
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 6fca513ec9..c67a910e48 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -541,7 +541,8 @@ static void virt_machine_init(MachineState *machine)
sifive_clint_create(
memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size,
memmap[VIRT_CLINT].size, base_hartid, hart_count,
- SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, true);
+ SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
+ SIFIVE_CLINT_TIMEBASE_FREQ, true);
/* Per-socket PLIC hart topology configuration string */
plic_hart_config_len =
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 005880627e..f4c4111536 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -276,9 +276,11 @@ uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
return old;
}
-void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void))
+void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t),
+ uint32_t arg)
{
env->rdtime_fn = fn;
+ env->rdtime_fn_arg = arg;
}
void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 200001de74..26ae347b4a 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -351,7 +351,7 @@ static int read_time(CPURISCVState *env, int csrno, target_ulong *val)
return -RISCV_EXCP_ILLEGAL_INST;
}
- *val = env->rdtime_fn() + delta;
+ *val = env->rdtime_fn(env->rdtime_fn_arg) + delta;
return 0;
}
@@ -364,7 +364,7 @@ static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val)
return -RISCV_EXCP_ILLEGAL_INST;
}
- *val = (env->rdtime_fn() + delta) >> 32;
+ *val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32;
return 0;
}
#endif
--
2.28.0
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PULL 18/30] hw/riscv: sifive_u: Connect a DMA controller
2020-09-10 18:09 [PULL 00/30] riscv-to-apply queue Alistair Francis
` (16 preceding siblings ...)
2020-09-10 18:09 ` [PULL 17/30] hw/riscv: clint: Avoid using hard-coded timebase frequency Alistair Francis
@ 2020-09-10 18:09 ` Alistair Francis
2020-09-10 18:09 ` [PULL 19/30] hw/riscv: Move sifive_e_prci model to hw/misc Alistair Francis
` (12 subsequent siblings)
30 siblings, 0 replies; 34+ messages in thread
From: Alistair Francis @ 2020-09-10 18:09 UTC (permalink / raw)
To: peter.maydell, qemu-devel; +Cc: alistair23, Bin Meng, Alistair Francis
From: Bin Meng <bin.meng@windriver.com>
SiFive FU540 SoC integrates a platform DMA controller with 4 DMA
channels. This connects the exsiting SiFive PDMA model to the SoC,
and adds its device tree data as well.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-17-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/sifive_u.h | 11 +++++++++++
hw/riscv/sifive_u.c | 30 ++++++++++++++++++++++++++++++
hw/riscv/Kconfig | 1 +
3 files changed, 42 insertions(+)
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index d3c0c00d10..793000a2ed 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -19,6 +19,7 @@
#ifndef HW_SIFIVE_U_H
#define HW_SIFIVE_U_H
+#include "hw/dma/sifive_pdma.h"
#include "hw/net/cadence_gem.h"
#include "hw/riscv/riscv_hart.h"
#include "hw/riscv/sifive_cpu.h"
@@ -43,6 +44,7 @@ typedef struct SiFiveUSoCState {
SiFiveUPRCIState prci;
SIFIVEGPIOState gpio;
SiFiveUOTPState otp;
+ SiFivePDMAState dma;
CadenceGEMState gem;
uint32_t serial;
@@ -72,6 +74,7 @@ enum {
SIFIVE_U_MROM,
SIFIVE_U_CLINT,
SIFIVE_U_L2CC,
+ SIFIVE_U_PDMA,
SIFIVE_U_L2LIM,
SIFIVE_U_PLIC,
SIFIVE_U_PRCI,
@@ -108,6 +111,14 @@ enum {
SIFIVE_U_GPIO_IRQ13 = 20,
SIFIVE_U_GPIO_IRQ14 = 21,
SIFIVE_U_GPIO_IRQ15 = 22,
+ SIFIVE_U_PDMA_IRQ0 = 23,
+ SIFIVE_U_PDMA_IRQ1 = 24,
+ SIFIVE_U_PDMA_IRQ2 = 25,
+ SIFIVE_U_PDMA_IRQ3 = 26,
+ SIFIVE_U_PDMA_IRQ4 = 27,
+ SIFIVE_U_PDMA_IRQ5 = 28,
+ SIFIVE_U_PDMA_IRQ6 = 29,
+ SIFIVE_U_PDMA_IRQ7 = 30,
SIFIVE_U_GEM_IRQ = 0x35
};
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 2bc3992989..79975372ef 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -14,6 +14,7 @@
* 4) GPIO (General Purpose Input/Output Controller)
* 5) OTP (One-Time Programmable) memory with stored serial number
* 6) GEM (Gigabit Ethernet Controller) and management block
+ * 7) DMA (Direct Memory Access Controller)
*
* This board currently generates devicetree dynamically that indicates at least
* two harts and up to five harts.
@@ -73,6 +74,7 @@ static const struct MemmapEntry {
[SIFIVE_U_MROM] = { 0x1000, 0xf000 },
[SIFIVE_U_CLINT] = { 0x2000000, 0x10000 },
[SIFIVE_U_L2CC] = { 0x2010000, 0x1000 },
+ [SIFIVE_U_PDMA] = { 0x3000000, 0x100000 },
[SIFIVE_U_L2LIM] = { 0x8000000, 0x2000000 },
[SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 },
[SIFIVE_U_PRCI] = { 0x10000000, 0x1000 },
@@ -303,6 +305,22 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
qemu_fdt_setprop_string(fdt, nodename, "compatible", "gpio-restart");
g_free(nodename);
+ nodename = g_strdup_printf("/soc/dma@%lx",
+ (long)memmap[SIFIVE_U_PDMA].base);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_cell(fdt, nodename, "#dma-cells", 1);
+ qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
+ SIFIVE_U_PDMA_IRQ0, SIFIVE_U_PDMA_IRQ1, SIFIVE_U_PDMA_IRQ2,
+ SIFIVE_U_PDMA_IRQ3, SIFIVE_U_PDMA_IRQ4, SIFIVE_U_PDMA_IRQ5,
+ SIFIVE_U_PDMA_IRQ6, SIFIVE_U_PDMA_IRQ7);
+ qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
+ qemu_fdt_setprop_cells(fdt, nodename, "reg",
+ 0x0, memmap[SIFIVE_U_PDMA].base,
+ 0x0, memmap[SIFIVE_U_PDMA].size);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible",
+ "sifive,fu540-c000-pdma");
+ g_free(nodename);
+
nodename = g_strdup_printf("/soc/cache-controller@%lx",
(long)memmap[SIFIVE_U_L2CC].base);
qemu_fdt_add_subnode(fdt, nodename);
@@ -627,6 +645,7 @@ static void sifive_u_soc_instance_init(Object *obj)
object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP);
object_initialize_child(obj, "gem", &s->gem, TYPE_CADENCE_GEM);
object_initialize_child(obj, "gpio", &s->gpio, TYPE_SIFIVE_GPIO);
+ object_initialize_child(obj, "pdma", &s->dma, TYPE_SIFIVE_PDMA);
}
static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
@@ -730,6 +749,17 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
SIFIVE_U_GPIO_IRQ0 + i));
}
+ /* PDMA */
+ sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, memmap[SIFIVE_U_PDMA].base);
+
+ /* Connect PDMA interrupts to the PLIC */
+ for (i = 0; i < SIFIVE_PDMA_IRQS; i++) {
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i,
+ qdev_get_gpio_in(DEVICE(s->plic),
+ SIFIVE_U_PDMA_IRQ0 + i));
+ }
+
qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->otp), errp)) {
return;
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index 9032cb0cbd..e53ab1efa5 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -22,6 +22,7 @@ config SIFIVE_U
select CADENCE
select HART
select SIFIVE
+ select SIFIVE_PDMA
select UNIMP
config SPIKE
--
2.28.0
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PULL 19/30] hw/riscv: Move sifive_e_prci model to hw/misc
2020-09-10 18:09 [PULL 00/30] riscv-to-apply queue Alistair Francis
` (17 preceding siblings ...)
2020-09-10 18:09 ` [PULL 18/30] hw/riscv: sifive_u: Connect a DMA controller Alistair Francis
@ 2020-09-10 18:09 ` Alistair Francis
2020-09-10 18:09 ` [PULL 20/30] hw/riscv: Move sifive_u_prci " Alistair Francis
` (11 subsequent siblings)
30 siblings, 0 replies; 34+ messages in thread
From: Alistair Francis @ 2020-09-10 18:09 UTC (permalink / raw)
To: peter.maydell, qemu-devel; +Cc: alistair23, Bin Meng, Alistair Francis
From: Bin Meng <bin.meng@windriver.com>
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_e_prci model to hw/misc directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-2-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/{riscv => misc}/sifive_e_prci.h | 0
hw/{riscv => misc}/sifive_e_prci.c | 2 +-
hw/riscv/sifive_e.c | 2 +-
hw/misc/Kconfig | 3 +++
hw/misc/meson.build | 3 +++
hw/riscv/Kconfig | 1 +
hw/riscv/meson.build | 1 -
7 files changed, 9 insertions(+), 3 deletions(-)
rename include/hw/{riscv => misc}/sifive_e_prci.h (100%)
rename hw/{riscv => misc}/sifive_e_prci.c (99%)
diff --git a/include/hw/riscv/sifive_e_prci.h b/include/hw/misc/sifive_e_prci.h
similarity index 100%
rename from include/hw/riscv/sifive_e_prci.h
rename to include/hw/misc/sifive_e_prci.h
diff --git a/hw/riscv/sifive_e_prci.c b/hw/misc/sifive_e_prci.c
similarity index 99%
rename from hw/riscv/sifive_e_prci.c
rename to hw/misc/sifive_e_prci.c
index 17dfa74715..8ec4ee4b41 100644
--- a/hw/riscv/sifive_e_prci.c
+++ b/hw/misc/sifive_e_prci.c
@@ -24,7 +24,7 @@
#include "qemu/log.h"
#include "qemu/module.h"
#include "hw/hw.h"
-#include "hw/riscv/sifive_e_prci.h"
+#include "hw/misc/sifive_e_prci.h"
static uint64_t sifive_e_prci_read(void *opaque, hwaddr addr, unsigned int size)
{
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 36ccfb2071..7f43ed953a 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -43,8 +43,8 @@
#include "hw/riscv/sifive_clint.h"
#include "hw/riscv/sifive_uart.h"
#include "hw/riscv/sifive_e.h"
-#include "hw/riscv/sifive_e_prci.h"
#include "hw/riscv/boot.h"
+#include "hw/misc/sifive_e_prci.h"
#include "chardev/char.h"
#include "sysemu/arch_init.h"
#include "sysemu/sysemu.h"
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
index 92c397ca07..507398635b 100644
--- a/hw/misc/Kconfig
+++ b/hw/misc/Kconfig
@@ -134,4 +134,7 @@ config MAC_VIA
config AVR_POWER
bool
+config SIFIVE_E_PRCI
+ bool
+
source macio/Kconfig
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index e1576b81cf..b6b2e5797f 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -21,6 +21,9 @@ softmmu_ss.add(when: 'CONFIG_ARM11SCU', if_true: files('arm11scu.c'))
# Mac devices
softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
+# RISC-V devices
+softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))
+
# PKUnity SoC devices
softmmu_ss.add(when: 'CONFIG_PUV3', if_true: files('puv3_pm.c'))
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index e53ab1efa5..5855e99aaa 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -15,6 +15,7 @@ config SIFIVE_E
bool
select HART
select SIFIVE
+ select SIFIVE_E_PRCI
select UNIMP
config SIFIVE_U
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index c29a48c3f1..003994d1ea 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -10,7 +10,6 @@ riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
-riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e_prci.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_otp.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_prci.c'))
--
2.28.0
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PULL 20/30] hw/riscv: Move sifive_u_prci model to hw/misc
2020-09-10 18:09 [PULL 00/30] riscv-to-apply queue Alistair Francis
` (18 preceding siblings ...)
2020-09-10 18:09 ` [PULL 19/30] hw/riscv: Move sifive_e_prci model to hw/misc Alistair Francis
@ 2020-09-10 18:09 ` Alistair Francis
2020-09-10 18:09 ` [PULL 21/30] hw/riscv: Move sifive_u_otp " Alistair Francis
` (10 subsequent siblings)
30 siblings, 0 replies; 34+ messages in thread
From: Alistair Francis @ 2020-09-10 18:09 UTC (permalink / raw)
To: peter.maydell, qemu-devel; +Cc: alistair23, Bin Meng, Alistair Francis
From: Bin Meng <bin.meng@windriver.com>
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_u_prci model to hw/misc directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-3-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/{riscv => misc}/sifive_u_prci.h | 0
include/hw/riscv/sifive_u.h | 2 +-
hw/{riscv => misc}/sifive_u_prci.c | 2 +-
hw/misc/Kconfig | 3 +++
hw/misc/meson.build | 1 +
hw/riscv/Kconfig | 1 +
hw/riscv/meson.build | 1 -
7 files changed, 7 insertions(+), 3 deletions(-)
rename include/hw/{riscv => misc}/sifive_u_prci.h (100%)
rename hw/{riscv => misc}/sifive_u_prci.c (99%)
diff --git a/include/hw/riscv/sifive_u_prci.h b/include/hw/misc/sifive_u_prci.h
similarity index 100%
rename from include/hw/riscv/sifive_u_prci.h
rename to include/hw/misc/sifive_u_prci.h
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index 793000a2ed..cbeb2286d7 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -24,8 +24,8 @@
#include "hw/riscv/riscv_hart.h"
#include "hw/riscv/sifive_cpu.h"
#include "hw/riscv/sifive_gpio.h"
-#include "hw/riscv/sifive_u_prci.h"
#include "hw/riscv/sifive_u_otp.h"
+#include "hw/misc/sifive_u_prci.h"
#define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"
#define RISCV_U_SOC(obj) \
diff --git a/hw/riscv/sifive_u_prci.c b/hw/misc/sifive_u_prci.c
similarity index 99%
rename from hw/riscv/sifive_u_prci.c
rename to hw/misc/sifive_u_prci.c
index 4fa590c064..5d9d446ee8 100644
--- a/hw/riscv/sifive_u_prci.c
+++ b/hw/misc/sifive_u_prci.c
@@ -22,7 +22,7 @@
#include "hw/sysbus.h"
#include "qemu/log.h"
#include "qemu/module.h"
-#include "hw/riscv/sifive_u_prci.h"
+#include "hw/misc/sifive_u_prci.h"
static uint64_t sifive_u_prci_read(void *opaque, hwaddr addr, unsigned int size)
{
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
index 507398635b..65f3fdd9e0 100644
--- a/hw/misc/Kconfig
+++ b/hw/misc/Kconfig
@@ -137,4 +137,7 @@ config AVR_POWER
config SIFIVE_E_PRCI
bool
+config SIFIVE_U_PRCI
+ bool
+
source macio/Kconfig
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index b6b2e5797f..9e9550e30d 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -23,6 +23,7 @@ softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
# RISC-V devices
softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))
+softmmu_ss.add(when: 'CONFIG_SIFIVE_U_PRCI', if_true: files('sifive_u_prci.c'))
# PKUnity SoC devices
softmmu_ss.add(when: 'CONFIG_PUV3', if_true: files('puv3_pm.c'))
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index 5855e99aaa..109364b814 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -24,6 +24,7 @@ config SIFIVE_U
select HART
select SIFIVE
select SIFIVE_PDMA
+ select SIFIVE_U_PRCI
select UNIMP
config SPIKE
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index 003994d1ea..3462cb5a28 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -12,7 +12,6 @@ riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_otp.c'))
-riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_prci.c'))
riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('riscv_htif.c'))
riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
--
2.28.0
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PULL 21/30] hw/riscv: Move sifive_u_otp model to hw/misc
2020-09-10 18:09 [PULL 00/30] riscv-to-apply queue Alistair Francis
` (19 preceding siblings ...)
2020-09-10 18:09 ` [PULL 20/30] hw/riscv: Move sifive_u_prci " Alistair Francis
@ 2020-09-10 18:09 ` Alistair Francis
2020-09-10 18:09 ` [PULL 22/30] hw/riscv: Move sifive_gpio model to hw/gpio Alistair Francis
` (9 subsequent siblings)
30 siblings, 0 replies; 34+ messages in thread
From: Alistair Francis @ 2020-09-10 18:09 UTC (permalink / raw)
To: peter.maydell, qemu-devel; +Cc: alistair23, Bin Meng, Alistair Francis
From: Bin Meng <bin.meng@windriver.com>
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_u_otp model to hw/misc directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-4-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/{riscv => misc}/sifive_u_otp.h | 0
include/hw/riscv/sifive_u.h | 2 +-
hw/{riscv => misc}/sifive_u_otp.c | 2 +-
hw/misc/Kconfig | 3 +++
hw/misc/meson.build | 1 +
hw/riscv/Kconfig | 1 +
hw/riscv/meson.build | 1 -
7 files changed, 7 insertions(+), 3 deletions(-)
rename include/hw/{riscv => misc}/sifive_u_otp.h (100%)
rename hw/{riscv => misc}/sifive_u_otp.c (99%)
diff --git a/include/hw/riscv/sifive_u_otp.h b/include/hw/misc/sifive_u_otp.h
similarity index 100%
rename from include/hw/riscv/sifive_u_otp.h
rename to include/hw/misc/sifive_u_otp.h
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index cbeb2286d7..936a3bd0b1 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -24,7 +24,7 @@
#include "hw/riscv/riscv_hart.h"
#include "hw/riscv/sifive_cpu.h"
#include "hw/riscv/sifive_gpio.h"
-#include "hw/riscv/sifive_u_otp.h"
+#include "hw/misc/sifive_u_otp.h"
#include "hw/misc/sifive_u_prci.h"
#define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"
diff --git a/hw/riscv/sifive_u_otp.c b/hw/misc/sifive_u_otp.c
similarity index 99%
rename from hw/riscv/sifive_u_otp.c
rename to hw/misc/sifive_u_otp.c
index f6ecbaa2ca..c2f3c8e129 100644
--- a/hw/riscv/sifive_u_otp.c
+++ b/hw/misc/sifive_u_otp.c
@@ -23,7 +23,7 @@
#include "hw/sysbus.h"
#include "qemu/log.h"
#include "qemu/module.h"
-#include "hw/riscv/sifive_u_otp.h"
+#include "hw/misc/sifive_u_otp.h"
static uint64_t sifive_u_otp_read(void *opaque, hwaddr addr, unsigned int size)
{
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
index 65f3fdd9e0..fa3d0f4723 100644
--- a/hw/misc/Kconfig
+++ b/hw/misc/Kconfig
@@ -137,6 +137,9 @@ config AVR_POWER
config SIFIVE_E_PRCI
bool
+config SIFIVE_U_OTP
+ bool
+
config SIFIVE_U_PRCI
bool
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index 9e9550e30d..018a88c670 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -23,6 +23,7 @@ softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
# RISC-V devices
softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))
+softmmu_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c'))
softmmu_ss.add(when: 'CONFIG_SIFIVE_U_PRCI', if_true: files('sifive_u_prci.c'))
# PKUnity SoC devices
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index 109364b814..76eaf77a80 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -24,6 +24,7 @@ config SIFIVE_U
select HART
select SIFIVE
select SIFIVE_PDMA
+ select SIFIVE_U_OTP
select SIFIVE_U_PRCI
select UNIMP
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index 3462cb5a28..74a73b2a44 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -11,7 +11,6 @@ riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
-riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_otp.c'))
riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('riscv_htif.c'))
riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
--
2.28.0
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PULL 22/30] hw/riscv: Move sifive_gpio model to hw/gpio
2020-09-10 18:09 [PULL 00/30] riscv-to-apply queue Alistair Francis
` (20 preceding siblings ...)
2020-09-10 18:09 ` [PULL 21/30] hw/riscv: Move sifive_u_otp " Alistair Francis
@ 2020-09-10 18:09 ` Alistair Francis
2020-09-10 18:09 ` [PULL 23/30] hw/riscv: Move sifive_clint model to hw/intc Alistair Francis
` (8 subsequent siblings)
30 siblings, 0 replies; 34+ messages in thread
From: Alistair Francis @ 2020-09-10 18:09 UTC (permalink / raw)
To: peter.maydell, qemu-devel; +Cc: alistair23, Bin Meng, Alistair Francis
From: Bin Meng <bin.meng@windriver.com>
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_gpio model to hw/gpio directory.
Note this also removes the trace-events in the hw/riscv directory,
since gpio is the only supported trace target in that directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-5-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/trace.h | 1 -
include/hw/{riscv => gpio}/sifive_gpio.h | 0
include/hw/riscv/sifive_e.h | 2 +-
include/hw/riscv/sifive_u.h | 2 +-
hw/{riscv => gpio}/sifive_gpio.c | 2 +-
hw/gpio/Kconfig | 3 +++
hw/gpio/meson.build | 1 +
hw/gpio/trace-events | 6 ++++++
hw/riscv/Kconfig | 2 ++
hw/riscv/meson.build | 1 -
hw/riscv/trace-events | 7 -------
meson.build | 1 -
12 files changed, 15 insertions(+), 13 deletions(-)
delete mode 100644 hw/riscv/trace.h
rename include/hw/{riscv => gpio}/sifive_gpio.h (100%)
rename hw/{riscv => gpio}/sifive_gpio.c (99%)
delete mode 100644 hw/riscv/trace-events
diff --git a/hw/riscv/trace.h b/hw/riscv/trace.h
deleted file mode 100644
index 8c0e3ca1f3..0000000000
--- a/hw/riscv/trace.h
+++ /dev/null
@@ -1 +0,0 @@
-#include "trace/trace-hw_riscv.h"
diff --git a/include/hw/riscv/sifive_gpio.h b/include/hw/gpio/sifive_gpio.h
similarity index 100%
rename from include/hw/riscv/sifive_gpio.h
rename to include/hw/gpio/sifive_gpio.h
diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
index 637414130b..b1400843c2 100644
--- a/include/hw/riscv/sifive_e.h
+++ b/include/hw/riscv/sifive_e.h
@@ -21,7 +21,7 @@
#include "hw/riscv/riscv_hart.h"
#include "hw/riscv/sifive_cpu.h"
-#include "hw/riscv/sifive_gpio.h"
+#include "hw/gpio/sifive_gpio.h"
#define TYPE_RISCV_E_SOC "riscv.sifive.e.soc"
#define RISCV_E_SOC(obj) \
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index 936a3bd0b1..fe5c580845 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -23,7 +23,7 @@
#include "hw/net/cadence_gem.h"
#include "hw/riscv/riscv_hart.h"
#include "hw/riscv/sifive_cpu.h"
-#include "hw/riscv/sifive_gpio.h"
+#include "hw/gpio/sifive_gpio.h"
#include "hw/misc/sifive_u_otp.h"
#include "hw/misc/sifive_u_prci.h"
diff --git a/hw/riscv/sifive_gpio.c b/hw/gpio/sifive_gpio.c
similarity index 99%
rename from hw/riscv/sifive_gpio.c
rename to hw/gpio/sifive_gpio.c
index aac6b44cac..78bf29e996 100644
--- a/hw/riscv/sifive_gpio.c
+++ b/hw/gpio/sifive_gpio.c
@@ -15,7 +15,7 @@
#include "qemu/log.h"
#include "hw/irq.h"
#include "hw/qdev-properties.h"
-#include "hw/riscv/sifive_gpio.h"
+#include "hw/gpio/sifive_gpio.h"
#include "migration/vmstate.h"
#include "trace.h"
diff --git a/hw/gpio/Kconfig b/hw/gpio/Kconfig
index 9227cb5598..b6fdaa2586 100644
--- a/hw/gpio/Kconfig
+++ b/hw/gpio/Kconfig
@@ -7,3 +7,6 @@ config PL061
config GPIO_KEY
bool
+
+config SIFIVE_GPIO
+ bool
diff --git a/hw/gpio/meson.build b/hw/gpio/meson.build
index 6bcdfa6b1d..86cae9a0f3 100644
--- a/hw/gpio/meson.build
+++ b/hw/gpio/meson.build
@@ -10,3 +10,4 @@ softmmu_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_gpio.c'))
softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_gpio.c'))
softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_gpio.c'))
softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_gpio.c'))
+softmmu_ss.add(when: 'CONFIG_SIFIVE_GPIO', if_true: files('sifive_gpio.c'))
diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events
index c1271fdfb2..6e3f048745 100644
--- a/hw/gpio/trace-events
+++ b/hw/gpio/trace-events
@@ -5,3 +5,9 @@ nrf51_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PR
nrf51_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64
nrf51_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
nrf51_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
+
+# sifive_gpio.c
+sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64
+sifive_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64
+sifive_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
+sifive_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index 76eaf77a80..5a8335bfec 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -15,6 +15,7 @@ config SIFIVE_E
bool
select HART
select SIFIVE
+ select SIFIVE_GPIO
select SIFIVE_E_PRCI
select UNIMP
@@ -23,6 +24,7 @@ config SIFIVE_U
select CADENCE
select HART
select SIFIVE
+ select SIFIVE_GPIO
select SIFIVE_PDMA
select SIFIVE_U_OTP
select SIFIVE_U_PRCI
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index 74a73b2a44..90003793d4 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -5,7 +5,6 @@ riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_clint.c'))
-riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_gpio.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
diff --git a/hw/riscv/trace-events b/hw/riscv/trace-events
deleted file mode 100644
index 6d59233e23..0000000000
--- a/hw/riscv/trace-events
+++ /dev/null
@@ -1,7 +0,0 @@
-# See docs/devel/tracing.txt for syntax documentation.
-
-# hw/gpio/sifive_gpio.c
-sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64
-sifive_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64
-sifive_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
-sifive_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
diff --git a/meson.build b/meson.build
index 5421eca66a..bc869c676a 100644
--- a/meson.build
+++ b/meson.build
@@ -773,7 +773,6 @@ if have_system
'hw/watchdog',
'hw/xen',
'hw/gpio',
- 'hw/riscv',
'migration',
'net',
'ui',
--
2.28.0
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PULL 23/30] hw/riscv: Move sifive_clint model to hw/intc
2020-09-10 18:09 [PULL 00/30] riscv-to-apply queue Alistair Francis
` (21 preceding siblings ...)
2020-09-10 18:09 ` [PULL 22/30] hw/riscv: Move sifive_gpio model to hw/gpio Alistair Francis
@ 2020-09-10 18:09 ` Alistair Francis
2020-09-10 18:09 ` [PULL 24/30] hw/riscv: Move sifive_plic " Alistair Francis
` (7 subsequent siblings)
30 siblings, 0 replies; 34+ messages in thread
From: Alistair Francis @ 2020-09-10 18:09 UTC (permalink / raw)
To: peter.maydell, qemu-devel; +Cc: alistair23, Bin Meng, Alistair Francis
From: Bin Meng <bin.meng@windriver.com>
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_clint model to hw/intc directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-6-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/{riscv => intc}/sifive_clint.h | 0
hw/{riscv => intc}/sifive_clint.c | 2 +-
hw/riscv/microchip_pfsoc.c | 2 +-
hw/riscv/sifive_e.c | 2 +-
hw/riscv/sifive_u.c | 2 +-
hw/riscv/spike.c | 2 +-
hw/riscv/virt.c | 2 +-
hw/intc/Kconfig | 3 +++
hw/intc/meson.build | 1 +
hw/riscv/Kconfig | 5 +++++
hw/riscv/meson.build | 1 -
11 files changed, 15 insertions(+), 7 deletions(-)
rename include/hw/{riscv => intc}/sifive_clint.h (100%)
rename hw/{riscv => intc}/sifive_clint.c (99%)
diff --git a/include/hw/riscv/sifive_clint.h b/include/hw/intc/sifive_clint.h
similarity index 100%
rename from include/hw/riscv/sifive_clint.h
rename to include/hw/intc/sifive_clint.h
diff --git a/hw/riscv/sifive_clint.c b/hw/intc/sifive_clint.c
similarity index 99%
rename from hw/riscv/sifive_clint.c
rename to hw/intc/sifive_clint.c
index fa1ddf2ccd..0f41e5ea1c 100644
--- a/hw/riscv/sifive_clint.c
+++ b/hw/intc/sifive_clint.c
@@ -26,7 +26,7 @@
#include "hw/sysbus.h"
#include "target/riscv/cpu.h"
#include "hw/qdev-properties.h"
-#include "hw/riscv/sifive_clint.h"
+#include "hw/intc/sifive_clint.h"
#include "qemu/timer.h"
static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq)
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index da6bd295ce..131eea1ef3 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -48,9 +48,9 @@
#include "hw/misc/unimp.h"
#include "hw/riscv/boot.h"
#include "hw/riscv/riscv_hart.h"
-#include "hw/riscv/sifive_clint.h"
#include "hw/riscv/sifive_plic.h"
#include "hw/riscv/microchip_pfsoc.h"
+#include "hw/intc/sifive_clint.h"
#include "sysemu/sysemu.h"
/*
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 7f43ed953a..3bdb16e697 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -40,10 +40,10 @@
#include "target/riscv/cpu.h"
#include "hw/riscv/riscv_hart.h"
#include "hw/riscv/sifive_plic.h"
-#include "hw/riscv/sifive_clint.h"
#include "hw/riscv/sifive_uart.h"
#include "hw/riscv/sifive_e.h"
#include "hw/riscv/boot.h"
+#include "hw/intc/sifive_clint.h"
#include "hw/misc/sifive_e_prci.h"
#include "chardev/char.h"
#include "sysemu/arch_init.h"
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 79975372ef..7187d1ad17 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -47,10 +47,10 @@
#include "target/riscv/cpu.h"
#include "hw/riscv/riscv_hart.h"
#include "hw/riscv/sifive_plic.h"
-#include "hw/riscv/sifive_clint.h"
#include "hw/riscv/sifive_uart.h"
#include "hw/riscv/sifive_u.h"
#include "hw/riscv/boot.h"
+#include "hw/intc/sifive_clint.h"
#include "chardev/char.h"
#include "net/eth.h"
#include "sysemu/arch_init.h"
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index b54a396107..59d9d87c56 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -33,10 +33,10 @@
#include "target/riscv/cpu.h"
#include "hw/riscv/riscv_htif.h"
#include "hw/riscv/riscv_hart.h"
-#include "hw/riscv/sifive_clint.h"
#include "hw/riscv/spike.h"
#include "hw/riscv/boot.h"
#include "hw/riscv/numa.h"
+#include "hw/intc/sifive_clint.h"
#include "chardev/char.h"
#include "sysemu/arch_init.h"
#include "sysemu/device_tree.h"
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index c67a910e48..bce2020d02 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -31,11 +31,11 @@
#include "target/riscv/cpu.h"
#include "hw/riscv/riscv_hart.h"
#include "hw/riscv/sifive_plic.h"
-#include "hw/riscv/sifive_clint.h"
#include "hw/riscv/sifive_test.h"
#include "hw/riscv/virt.h"
#include "hw/riscv/boot.h"
#include "hw/riscv/numa.h"
+#include "hw/intc/sifive_clint.h"
#include "chardev/char.h"
#include "sysemu/arch_init.h"
#include "sysemu/device_tree.h"
diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
index 2ae1e89497..f499d0f8df 100644
--- a/hw/intc/Kconfig
+++ b/hw/intc/Kconfig
@@ -67,3 +67,6 @@ config RX_ICU
config LOONGSON_LIOINTC
bool
+
+config SIFIVE_CLINT
+ bool
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
index c16f7f036e..1e20daab77 100644
--- a/hw/intc/meson.build
+++ b/hw/intc/meson.build
@@ -47,6 +47,7 @@ specific_ss.add(when: 'CONFIG_RX_ICU', if_true: files('rx_icu.c'))
specific_ss.add(when: 'CONFIG_S390_FLIC', if_true: files('s390_flic.c'))
specific_ss.add(when: 'CONFIG_S390_FLIC_KVM', if_true: files('s390_flic_kvm.c'))
specific_ss.add(when: 'CONFIG_SH4', if_true: files('sh_intc.c'))
+specific_ss.add(when: 'CONFIG_SIFIVE_CLINT', if_true: files('sifive_clint.c'))
specific_ss.add(when: 'CONFIG_XICS', if_true: files('xics.c'))
specific_ss.add(when: 'CONFIG_XICS_KVM', if_true: files('xics_kvm.c'))
specific_ss.add(when: 'CONFIG_XICS_SPAPR', if_true: files('xics_spapr.c'))
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index 5a8335bfec..f8bb7e7a05 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -15,6 +15,7 @@ config SIFIVE_E
bool
select HART
select SIFIVE
+ select SIFIVE_CLINT
select SIFIVE_GPIO
select SIFIVE_E_PRCI
select UNIMP
@@ -24,6 +25,7 @@ config SIFIVE_U
select CADENCE
select HART
select SIFIVE
+ select SIFIVE_CLINT
select SIFIVE_GPIO
select SIFIVE_PDMA
select SIFIVE_U_OTP
@@ -35,6 +37,7 @@ config SPIKE
select HART
select HTIF
select SIFIVE
+ select SIFIVE_CLINT
config OPENTITAN
bool
@@ -54,11 +57,13 @@ config RISCV_VIRT
select PCI_EXPRESS_GENERIC_BRIDGE
select PFLASH_CFI01
select SIFIVE
+ select SIFIVE_CLINT
config MICROCHIP_PFSOC
bool
select HART
select SIFIVE
+ select SIFIVE_CLINT
select UNIMP
select MCHP_PFSOC_MMUART
select SIFIVE_PDMA
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index 90003793d4..d0b4cafaec 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -4,7 +4,6 @@ riscv_ss.add(files('numa.c'))
riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
-riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_clint.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
--
2.28.0
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PULL 24/30] hw/riscv: Move sifive_plic model to hw/intc
2020-09-10 18:09 [PULL 00/30] riscv-to-apply queue Alistair Francis
` (22 preceding siblings ...)
2020-09-10 18:09 ` [PULL 23/30] hw/riscv: Move sifive_clint model to hw/intc Alistair Francis
@ 2020-09-10 18:09 ` Alistair Francis
2020-09-10 18:09 ` [PULL 25/30] hw/riscv: Move riscv_htif model to hw/char Alistair Francis
` (6 subsequent siblings)
30 siblings, 0 replies; 34+ messages in thread
From: Alistair Francis @ 2020-09-10 18:09 UTC (permalink / raw)
To: peter.maydell, qemu-devel; +Cc: alistair23, Bin Meng, Alistair Francis
From: Bin Meng <bin.meng@windriver.com>
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_plic model to hw/intc directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-7-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
{include/hw/riscv => hw/intc}/sifive_plic.h | 0
hw/{riscv => intc}/sifive_plic.c | 2 +-
hw/riscv/microchip_pfsoc.c | 2 +-
hw/riscv/sifive_e.c | 2 +-
hw/riscv/sifive_u.c | 2 +-
hw/riscv/virt.c | 2 +-
hw/intc/Kconfig | 3 +++
hw/intc/meson.build | 1 +
hw/riscv/Kconfig | 5 +++++
hw/riscv/meson.build | 1 -
10 files changed, 14 insertions(+), 6 deletions(-)
rename {include/hw/riscv => hw/intc}/sifive_plic.h (100%)
rename hw/{riscv => intc}/sifive_plic.c (99%)
diff --git a/include/hw/riscv/sifive_plic.h b/hw/intc/sifive_plic.h
similarity index 100%
rename from include/hw/riscv/sifive_plic.h
rename to hw/intc/sifive_plic.h
diff --git a/hw/riscv/sifive_plic.c b/hw/intc/sifive_plic.c
similarity index 99%
rename from hw/riscv/sifive_plic.c
rename to hw/intc/sifive_plic.c
index 11ef147606..af611f8db8 100644
--- a/hw/riscv/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -27,9 +27,9 @@
#include "hw/pci/msi.h"
#include "hw/boards.h"
#include "hw/qdev-properties.h"
+#include "hw/intc/sifive_plic.h"
#include "target/riscv/cpu.h"
#include "sysemu/sysemu.h"
-#include "hw/riscv/sifive_plic.h"
#define RISCV_DEBUG_PLIC 0
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index 131eea1ef3..4627179cd3 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -48,9 +48,9 @@
#include "hw/misc/unimp.h"
#include "hw/riscv/boot.h"
#include "hw/riscv/riscv_hart.h"
-#include "hw/riscv/sifive_plic.h"
#include "hw/riscv/microchip_pfsoc.h"
#include "hw/intc/sifive_clint.h"
+#include "hw/intc/sifive_plic.h"
#include "sysemu/sysemu.h"
/*
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 3bdb16e697..0ddcf1508d 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -39,11 +39,11 @@
#include "hw/misc/unimp.h"
#include "target/riscv/cpu.h"
#include "hw/riscv/riscv_hart.h"
-#include "hw/riscv/sifive_plic.h"
#include "hw/riscv/sifive_uart.h"
#include "hw/riscv/sifive_e.h"
#include "hw/riscv/boot.h"
#include "hw/intc/sifive_clint.h"
+#include "hw/intc/sifive_plic.h"
#include "hw/misc/sifive_e_prci.h"
#include "chardev/char.h"
#include "sysemu/arch_init.h"
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 7187d1ad17..faca2e829e 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -46,11 +46,11 @@
#include "hw/misc/unimp.h"
#include "target/riscv/cpu.h"
#include "hw/riscv/riscv_hart.h"
-#include "hw/riscv/sifive_plic.h"
#include "hw/riscv/sifive_uart.h"
#include "hw/riscv/sifive_u.h"
#include "hw/riscv/boot.h"
#include "hw/intc/sifive_clint.h"
+#include "hw/intc/sifive_plic.h"
#include "chardev/char.h"
#include "net/eth.h"
#include "sysemu/arch_init.h"
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index bce2020d02..0caab8e050 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -30,12 +30,12 @@
#include "hw/char/serial.h"
#include "target/riscv/cpu.h"
#include "hw/riscv/riscv_hart.h"
-#include "hw/riscv/sifive_plic.h"
#include "hw/riscv/sifive_test.h"
#include "hw/riscv/virt.h"
#include "hw/riscv/boot.h"
#include "hw/riscv/numa.h"
#include "hw/intc/sifive_clint.h"
+#include "hw/intc/sifive_plic.h"
#include "chardev/char.h"
#include "sysemu/arch_init.h"
#include "sysemu/device_tree.h"
diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
index f499d0f8df..d07954086a 100644
--- a/hw/intc/Kconfig
+++ b/hw/intc/Kconfig
@@ -70,3 +70,6 @@ config LOONGSON_LIOINTC
config SIFIVE_CLINT
bool
+
+config SIFIVE_PLIC
+ bool
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
index 1e20daab77..3f82cc230a 100644
--- a/hw/intc/meson.build
+++ b/hw/intc/meson.build
@@ -48,6 +48,7 @@ specific_ss.add(when: 'CONFIG_S390_FLIC', if_true: files('s390_flic.c'))
specific_ss.add(when: 'CONFIG_S390_FLIC_KVM', if_true: files('s390_flic_kvm.c'))
specific_ss.add(when: 'CONFIG_SH4', if_true: files('sh_intc.c'))
specific_ss.add(when: 'CONFIG_SIFIVE_CLINT', if_true: files('sifive_clint.c'))
+specific_ss.add(when: 'CONFIG_SIFIVE_PLIC', if_true: files('sifive_plic.c'))
specific_ss.add(when: 'CONFIG_XICS', if_true: files('xics.c'))
specific_ss.add(when: 'CONFIG_XICS_KVM', if_true: files('xics_kvm.c'))
specific_ss.add(when: 'CONFIG_XICS_SPAPR', if_true: files('xics_spapr.c'))
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index f8bb7e7a05..23b7027e11 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -17,6 +17,7 @@ config SIFIVE_E
select SIFIVE
select SIFIVE_CLINT
select SIFIVE_GPIO
+ select SIFIVE_PLIC
select SIFIVE_E_PRCI
select UNIMP
@@ -28,6 +29,7 @@ config SIFIVE_U
select SIFIVE_CLINT
select SIFIVE_GPIO
select SIFIVE_PDMA
+ select SIFIVE_PLIC
select SIFIVE_U_OTP
select SIFIVE_U_PRCI
select UNIMP
@@ -38,6 +40,7 @@ config SPIKE
select HTIF
select SIFIVE
select SIFIVE_CLINT
+ select SIFIVE_PLIC
config OPENTITAN
bool
@@ -58,6 +61,7 @@ config RISCV_VIRT
select PFLASH_CFI01
select SIFIVE
select SIFIVE_CLINT
+ select SIFIVE_PLIC
config MICROCHIP_PFSOC
bool
@@ -67,4 +71,5 @@ config MICROCHIP_PFSOC
select UNIMP
select MCHP_PFSOC_MMUART
select SIFIVE_PDMA
+ select SIFIVE_PLIC
select CADENCE_SDHCI
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index d0b4cafaec..df3f89d062 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -4,7 +4,6 @@ riscv_ss.add(files('numa.c'))
riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
-riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
--
2.28.0
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PULL 25/30] hw/riscv: Move riscv_htif model to hw/char
2020-09-10 18:09 [PULL 00/30] riscv-to-apply queue Alistair Francis
` (23 preceding siblings ...)
2020-09-10 18:09 ` [PULL 24/30] hw/riscv: Move sifive_plic " Alistair Francis
@ 2020-09-10 18:09 ` Alistair Francis
2020-09-10 18:09 ` [PULL 26/30] hw/riscv: Move sifive_uart " Alistair Francis
` (5 subsequent siblings)
30 siblings, 0 replies; 34+ messages in thread
From: Alistair Francis @ 2020-09-10 18:09 UTC (permalink / raw)
To: peter.maydell, qemu-devel; +Cc: alistair23, Bin Meng, Alistair Francis
From: Bin Meng <bin.meng@windriver.com>
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move riscv_htif model to hw/char directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-8-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/{riscv => char}/riscv_htif.h | 0
hw/{riscv => char}/riscv_htif.c | 2 +-
hw/riscv/spike.c | 2 +-
hw/char/Kconfig | 3 +++
hw/char/meson.build | 1 +
hw/riscv/Kconfig | 3 ---
hw/riscv/meson.build | 1 -
7 files changed, 6 insertions(+), 6 deletions(-)
rename include/hw/{riscv => char}/riscv_htif.h (100%)
rename hw/{riscv => char}/riscv_htif.c (99%)
diff --git a/include/hw/riscv/riscv_htif.h b/include/hw/char/riscv_htif.h
similarity index 100%
rename from include/hw/riscv/riscv_htif.h
rename to include/hw/char/riscv_htif.h
diff --git a/hw/riscv/riscv_htif.c b/hw/char/riscv_htif.c
similarity index 99%
rename from hw/riscv/riscv_htif.c
rename to hw/char/riscv_htif.c
index ca87a5cf9f..ba1af1cfc4 100644
--- a/hw/riscv/riscv_htif.c
+++ b/hw/char/riscv_htif.c
@@ -24,10 +24,10 @@
#include "qapi/error.h"
#include "qemu/log.h"
#include "hw/sysbus.h"
+#include "hw/char/riscv_htif.h"
#include "hw/char/serial.h"
#include "chardev/char.h"
#include "chardev/char-fe.h"
-#include "hw/riscv/riscv_htif.h"
#include "qemu/timer.h"
#include "qemu/error-report.h"
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 59d9d87c56..3fd152a035 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -31,11 +31,11 @@
#include "hw/loader.h"
#include "hw/sysbus.h"
#include "target/riscv/cpu.h"
-#include "hw/riscv/riscv_htif.h"
#include "hw/riscv/riscv_hart.h"
#include "hw/riscv/spike.h"
#include "hw/riscv/boot.h"
#include "hw/riscv/numa.h"
+#include "hw/char/riscv_htif.h"
#include "hw/intc/sifive_clint.h"
#include "chardev/char.h"
#include "sysemu/arch_init.h"
diff --git a/hw/char/Kconfig b/hw/char/Kconfig
index 1d645554c7..91da92f617 100644
--- a/hw/char/Kconfig
+++ b/hw/char/Kconfig
@@ -1,6 +1,9 @@
config ESCC
bool
+config HTIF
+ bool
+
config PARALLEL
bool
default y
diff --git a/hw/char/meson.build b/hw/char/meson.build
index ae27932d00..3db623eeec 100644
--- a/hw/char/meson.build
+++ b/hw/char/meson.build
@@ -34,6 +34,7 @@ softmmu_ss.add(when: 'CONFIG_SH4', if_true: files('sh_serial.c'))
softmmu_ss.add(when: 'CONFIG_STM32F2XX_USART', if_true: files('stm32f2xx_usart.c'))
softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_MMUART', if_true: files('mchp_pfsoc_mmuart.c'))
+specific_ss.add(when: 'CONFIG_HTIF', if_true: files('riscv_htif.c'))
specific_ss.add(when: 'CONFIG_TERMINAL3270', if_true: files('terminal3270.c'))
specific_ss.add(when: 'CONFIG_VIRTIO', if_true: files('virtio-serial-bus.c'))
specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_vty.c'))
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index 23b7027e11..a0e256c344 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -1,6 +1,3 @@
-config HTIF
- bool
-
config HART
bool
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index df3f89d062..90df67acc7 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -8,7 +8,6 @@ riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
-riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('riscv_htif.c'))
riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
--
2.28.0
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PULL 26/30] hw/riscv: Move sifive_uart model to hw/char
2020-09-10 18:09 [PULL 00/30] riscv-to-apply queue Alistair Francis
` (24 preceding siblings ...)
2020-09-10 18:09 ` [PULL 25/30] hw/riscv: Move riscv_htif model to hw/char Alistair Francis
@ 2020-09-10 18:09 ` Alistair Francis
2020-09-10 18:09 ` [PULL 27/30] hw/riscv: Move sifive_test model to hw/misc Alistair Francis
` (4 subsequent siblings)
30 siblings, 0 replies; 34+ messages in thread
From: Alistair Francis @ 2020-09-10 18:09 UTC (permalink / raw)
To: peter.maydell, qemu-devel; +Cc: alistair23, Bin Meng, Alistair Francis
From: Bin Meng <bin.meng@windriver.com>
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_uart model to hw/char directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-9-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/{riscv => char}/sifive_uart.h | 0
hw/{riscv => char}/sifive_uart.c | 2 +-
hw/riscv/sifive_e.c | 2 +-
hw/riscv/sifive_u.c | 2 +-
hw/char/Kconfig | 3 +++
hw/char/meson.build | 1 +
hw/riscv/Kconfig | 2 ++
hw/riscv/meson.build | 1 -
8 files changed, 9 insertions(+), 4 deletions(-)
rename include/hw/{riscv => char}/sifive_uart.h (100%)
rename hw/{riscv => char}/sifive_uart.c (99%)
diff --git a/include/hw/riscv/sifive_uart.h b/include/hw/char/sifive_uart.h
similarity index 100%
rename from include/hw/riscv/sifive_uart.h
rename to include/hw/char/sifive_uart.h
diff --git a/hw/riscv/sifive_uart.c b/hw/char/sifive_uart.c
similarity index 99%
rename from hw/riscv/sifive_uart.c
rename to hw/char/sifive_uart.c
index 9350482662..3a00ba7f00 100644
--- a/hw/riscv/sifive_uart.c
+++ b/hw/char/sifive_uart.c
@@ -24,7 +24,7 @@
#include "chardev/char-fe.h"
#include "hw/hw.h"
#include "hw/irq.h"
-#include "hw/riscv/sifive_uart.h"
+#include "hw/char/sifive_uart.h"
/*
* Not yet implemented:
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 0ddcf1508d..40bbf530d4 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -39,9 +39,9 @@
#include "hw/misc/unimp.h"
#include "target/riscv/cpu.h"
#include "hw/riscv/riscv_hart.h"
-#include "hw/riscv/sifive_uart.h"
#include "hw/riscv/sifive_e.h"
#include "hw/riscv/boot.h"
+#include "hw/char/sifive_uart.h"
#include "hw/intc/sifive_clint.h"
#include "hw/intc/sifive_plic.h"
#include "hw/misc/sifive_e_prci.h"
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index faca2e829e..4f12a93188 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -46,9 +46,9 @@
#include "hw/misc/unimp.h"
#include "target/riscv/cpu.h"
#include "hw/riscv/riscv_hart.h"
-#include "hw/riscv/sifive_uart.h"
#include "hw/riscv/sifive_u.h"
#include "hw/riscv/boot.h"
+#include "hw/char/sifive_uart.h"
#include "hw/intc/sifive_clint.h"
#include "hw/intc/sifive_plic.h"
#include "chardev/char.h"
diff --git a/hw/char/Kconfig b/hw/char/Kconfig
index 91da92f617..939bc44758 100644
--- a/hw/char/Kconfig
+++ b/hw/char/Kconfig
@@ -58,3 +58,6 @@ config AVR_USART
config MCHP_PFSOC_MMUART
bool
+
+config SIFIVE_UART
+ bool
diff --git a/hw/char/meson.build b/hw/char/meson.build
index 3db623eeec..196ac91fa2 100644
--- a/hw/char/meson.build
+++ b/hw/char/meson.build
@@ -30,6 +30,7 @@ softmmu_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210_uart.c'))
softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_uart.c'))
softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_aux.c'))
softmmu_ss.add(when: 'CONFIG_RENESAS_SCI', if_true: files('renesas_sci.c'))
+softmmu_ss.add(when: 'CONFIG_SIFIVE_UART', if_true: files('sifive_uart.c'))
softmmu_ss.add(when: 'CONFIG_SH4', if_true: files('sh_serial.c'))
softmmu_ss.add(when: 'CONFIG_STM32F2XX_USART', if_true: files('stm32f2xx_usart.c'))
softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_MMUART', if_true: files('mchp_pfsoc_mmuart.c'))
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index a0e256c344..a0461578a6 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -15,6 +15,7 @@ config SIFIVE_E
select SIFIVE_CLINT
select SIFIVE_GPIO
select SIFIVE_PLIC
+ select SIFIVE_UART
select SIFIVE_E_PRCI
select UNIMP
@@ -27,6 +28,7 @@ config SIFIVE_U
select SIFIVE_GPIO
select SIFIVE_PDMA
select SIFIVE_PLIC
+ select SIFIVE_UART
select SIFIVE_U_OTP
select SIFIVE_U_PRCI
select UNIMP
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index 90df67acc7..967572d4f6 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -5,7 +5,6 @@ riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
-riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
--
2.28.0
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PULL 27/30] hw/riscv: Move sifive_test model to hw/misc
2020-09-10 18:09 [PULL 00/30] riscv-to-apply queue Alistair Francis
` (25 preceding siblings ...)
2020-09-10 18:09 ` [PULL 26/30] hw/riscv: Move sifive_uart " Alistair Francis
@ 2020-09-10 18:09 ` Alistair Francis
2020-09-10 18:09 ` [PULL 28/30] hw/riscv: Always build riscv_hart.c Alistair Francis
` (3 subsequent siblings)
30 siblings, 0 replies; 34+ messages in thread
From: Alistair Francis @ 2020-09-10 18:09 UTC (permalink / raw)
To: peter.maydell, qemu-devel; +Cc: alistair23, Bin Meng, Alistair Francis
From: Bin Meng <bin.meng@windriver.com>
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_test model to hw/misc directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-10-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/{riscv => misc}/sifive_test.h | 0
hw/{riscv => misc}/sifive_test.c | 2 +-
hw/riscv/virt.c | 2 +-
hw/misc/Kconfig | 3 +++
hw/misc/meson.build | 1 +
hw/riscv/Kconfig | 1 +
hw/riscv/meson.build | 1 -
7 files changed, 7 insertions(+), 3 deletions(-)
rename include/hw/{riscv => misc}/sifive_test.h (100%)
rename hw/{riscv => misc}/sifive_test.c (98%)
diff --git a/include/hw/riscv/sifive_test.h b/include/hw/misc/sifive_test.h
similarity index 100%
rename from include/hw/riscv/sifive_test.h
rename to include/hw/misc/sifive_test.h
diff --git a/hw/riscv/sifive_test.c b/hw/misc/sifive_test.c
similarity index 98%
rename from hw/riscv/sifive_test.c
rename to hw/misc/sifive_test.c
index 8c70dd69df..2deb2072cc 100644
--- a/hw/riscv/sifive_test.c
+++ b/hw/misc/sifive_test.c
@@ -25,7 +25,7 @@
#include "qemu/module.h"
#include "sysemu/runstate.h"
#include "hw/hw.h"
-#include "hw/riscv/sifive_test.h"
+#include "hw/misc/sifive_test.h"
static uint64_t sifive_test_read(void *opaque, hwaddr addr, unsigned int size)
{
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 0caab8e050..41bd2f38ba 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -30,12 +30,12 @@
#include "hw/char/serial.h"
#include "target/riscv/cpu.h"
#include "hw/riscv/riscv_hart.h"
-#include "hw/riscv/sifive_test.h"
#include "hw/riscv/virt.h"
#include "hw/riscv/boot.h"
#include "hw/riscv/numa.h"
#include "hw/intc/sifive_clint.h"
#include "hw/intc/sifive_plic.h"
+#include "hw/misc/sifive_test.h"
#include "chardev/char.h"
#include "sysemu/arch_init.h"
#include "sysemu/device_tree.h"
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
index fa3d0f4723..3185456110 100644
--- a/hw/misc/Kconfig
+++ b/hw/misc/Kconfig
@@ -134,6 +134,9 @@ config MAC_VIA
config AVR_POWER
bool
+config SIFIVE_TEST
+ bool
+
config SIFIVE_E_PRCI
bool
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index 018a88c670..bd24132757 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -22,6 +22,7 @@ softmmu_ss.add(when: 'CONFIG_ARM11SCU', if_true: files('arm11scu.c'))
softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
# RISC-V devices
+softmmu_ss.add(when: 'CONFIG_SIFIVE_TEST', if_true: files('sifive_test.c'))
softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))
softmmu_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c'))
softmmu_ss.add(when: 'CONFIG_SIFIVE_U_PRCI', if_true: files('sifive_u_prci.c'))
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index a0461578a6..8e0710001b 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -61,6 +61,7 @@ config RISCV_VIRT
select SIFIVE
select SIFIVE_CLINT
select SIFIVE_PLIC
+ select SIFIVE_TEST
config MICROCHIP_PFSOC
bool
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index 967572d4f6..f762623288 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -4,7 +4,6 @@ riscv_ss.add(files('numa.c'))
riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
-riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
--
2.28.0
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PULL 28/30] hw/riscv: Always build riscv_hart.c
2020-09-10 18:09 [PULL 00/30] riscv-to-apply queue Alistair Francis
` (26 preceding siblings ...)
2020-09-10 18:09 ` [PULL 27/30] hw/riscv: Move sifive_test model to hw/misc Alistair Francis
@ 2020-09-10 18:09 ` Alistair Francis
2020-09-10 18:09 ` [PULL 29/30] hw/riscv: Drop CONFIG_SIFIVE Alistair Francis
` (2 subsequent siblings)
30 siblings, 0 replies; 34+ messages in thread
From: Alistair Francis @ 2020-09-10 18:09 UTC (permalink / raw)
To: peter.maydell, qemu-devel; +Cc: alistair23, Bin Meng, Alistair Francis
From: Bin Meng <bin.meng@windriver.com>
Every RISC-V machine needs riscv_hart hence there is no need to
have a dedicated Kconfig option for it. Drop the Kconfig option
and always build riscv_hart.c.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-11-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/Kconfig | 9 ---------
hw/riscv/meson.build | 2 +-
2 files changed, 1 insertion(+), 10 deletions(-)
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index 8e0710001b..7d017bc7c3 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -1,6 +1,3 @@
-config HART
- bool
-
config IBEX
bool
@@ -10,7 +7,6 @@ config SIFIVE
config SIFIVE_E
bool
- select HART
select SIFIVE
select SIFIVE_CLINT
select SIFIVE_GPIO
@@ -22,7 +18,6 @@ config SIFIVE_E
config SIFIVE_U
bool
select CADENCE
- select HART
select SIFIVE
select SIFIVE_CLINT
select SIFIVE_GPIO
@@ -35,7 +30,6 @@ config SIFIVE_U
config SPIKE
bool
- select HART
select HTIF
select SIFIVE
select SIFIVE_CLINT
@@ -44,7 +38,6 @@ config SPIKE
config OPENTITAN
bool
select IBEX
- select HART
select UNIMP
config RISCV_VIRT
@@ -52,7 +45,6 @@ config RISCV_VIRT
imply PCI_DEVICES
imply TEST_DEVICES
select PCI
- select HART
select SERIAL
select GOLDFISH_RTC
select VIRTIO_MMIO
@@ -65,7 +57,6 @@ config RISCV_VIRT
config MICROCHIP_PFSOC
bool
- select HART
select SIFIVE
select SIFIVE_CLINT
select UNIMP
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index f762623288..275c0f7eb7 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -1,7 +1,7 @@
riscv_ss = ss.source_set()
riscv_ss.add(files('boot.c'), fdt)
riscv_ss.add(files('numa.c'))
-riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
+riscv_ss.add(files('riscv_hart.c'))
riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
--
2.28.0
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PULL 29/30] hw/riscv: Drop CONFIG_SIFIVE
2020-09-10 18:09 [PULL 00/30] riscv-to-apply queue Alistair Francis
` (27 preceding siblings ...)
2020-09-10 18:09 ` [PULL 28/30] hw/riscv: Always build riscv_hart.c Alistair Francis
@ 2020-09-10 18:09 ` Alistair Francis
2020-09-10 18:09 ` [PULL 30/30] hw/riscv: Sort the Kconfig options in alphabetical order Alistair Francis
2020-09-13 21:30 ` [PULL 00/30] riscv-to-apply queue Peter Maydell
30 siblings, 0 replies; 34+ messages in thread
From: Alistair Francis @ 2020-09-10 18:09 UTC (permalink / raw)
To: peter.maydell, qemu-devel; +Cc: alistair23, Bin Meng, Alistair Francis
From: Bin Meng <bin.meng@windriver.com>
The name SIFIVE is too vague to convey the required component of
MSI_NONBROKEN. Let's drop the option, and select MSI_NONBROKEN in
each machine instead.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-12-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/Kconfig | 14 +++++---------
1 file changed, 5 insertions(+), 9 deletions(-)
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index 7d017bc7c3..e152fdc7d9 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -1,13 +1,9 @@
config IBEX
bool
-config SIFIVE
- bool
- select MSI_NONBROKEN
-
config SIFIVE_E
bool
- select SIFIVE
+ select MSI_NONBROKEN
select SIFIVE_CLINT
select SIFIVE_GPIO
select SIFIVE_PLIC
@@ -18,7 +14,7 @@ config SIFIVE_E
config SIFIVE_U
bool
select CADENCE
- select SIFIVE
+ select MSI_NONBROKEN
select SIFIVE_CLINT
select SIFIVE_GPIO
select SIFIVE_PDMA
@@ -31,7 +27,7 @@ config SIFIVE_U
config SPIKE
bool
select HTIF
- select SIFIVE
+ select MSI_NONBROKEN
select SIFIVE_CLINT
select SIFIVE_PLIC
@@ -44,20 +40,20 @@ config RISCV_VIRT
bool
imply PCI_DEVICES
imply TEST_DEVICES
+ select MSI_NONBROKEN
select PCI
select SERIAL
select GOLDFISH_RTC
select VIRTIO_MMIO
select PCI_EXPRESS_GENERIC_BRIDGE
select PFLASH_CFI01
- select SIFIVE
select SIFIVE_CLINT
select SIFIVE_PLIC
select SIFIVE_TEST
config MICROCHIP_PFSOC
bool
- select SIFIVE
+ select MSI_NONBROKEN
select SIFIVE_CLINT
select UNIMP
select MCHP_PFSOC_MMUART
--
2.28.0
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PULL 30/30] hw/riscv: Sort the Kconfig options in alphabetical order
2020-09-10 18:09 [PULL 00/30] riscv-to-apply queue Alistair Francis
` (28 preceding siblings ...)
2020-09-10 18:09 ` [PULL 29/30] hw/riscv: Drop CONFIG_SIFIVE Alistair Francis
@ 2020-09-10 18:09 ` Alistair Francis
2020-09-13 21:30 ` [PULL 00/30] riscv-to-apply queue Peter Maydell
30 siblings, 0 replies; 34+ messages in thread
From: Alistair Francis @ 2020-09-10 18:09 UTC (permalink / raw)
To: peter.maydell, qemu-devel; +Cc: alistair23, Bin Meng, Alistair Francis
From: Bin Meng <bin.meng@windriver.com>
At present the Kconfig file is in disorder. Let's sort the options.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-13-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/Kconfig | 58 ++++++++++++++++++++++++------------------------
1 file changed, 29 insertions(+), 29 deletions(-)
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index e152fdc7d9..2df978fe8d 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -1,36 +1,16 @@
config IBEX
bool
-config SIFIVE_E
- bool
- select MSI_NONBROKEN
- select SIFIVE_CLINT
- select SIFIVE_GPIO
- select SIFIVE_PLIC
- select SIFIVE_UART
- select SIFIVE_E_PRCI
- select UNIMP
-
-config SIFIVE_U
+config MICROCHIP_PFSOC
bool
- select CADENCE
+ select CADENCE_SDHCI
+ select MCHP_PFSOC_MMUART
select MSI_NONBROKEN
select SIFIVE_CLINT
- select SIFIVE_GPIO
select SIFIVE_PDMA
select SIFIVE_PLIC
- select SIFIVE_UART
- select SIFIVE_U_OTP
- select SIFIVE_U_PRCI
select UNIMP
-config SPIKE
- bool
- select HTIF
- select MSI_NONBROKEN
- select SIFIVE_CLINT
- select SIFIVE_PLIC
-
config OPENTITAN
bool
select IBEX
@@ -40,23 +20,43 @@ config RISCV_VIRT
bool
imply PCI_DEVICES
imply TEST_DEVICES
+ select GOLDFISH_RTC
select MSI_NONBROKEN
select PCI
- select SERIAL
- select GOLDFISH_RTC
- select VIRTIO_MMIO
select PCI_EXPRESS_GENERIC_BRIDGE
select PFLASH_CFI01
+ select SERIAL
select SIFIVE_CLINT
select SIFIVE_PLIC
select SIFIVE_TEST
+ select VIRTIO_MMIO
-config MICROCHIP_PFSOC
+config SIFIVE_E
bool
select MSI_NONBROKEN
select SIFIVE_CLINT
+ select SIFIVE_GPIO
+ select SIFIVE_PLIC
+ select SIFIVE_UART
+ select SIFIVE_E_PRCI
select UNIMP
- select MCHP_PFSOC_MMUART
+
+config SIFIVE_U
+ bool
+ select CADENCE
+ select MSI_NONBROKEN
+ select SIFIVE_CLINT
+ select SIFIVE_GPIO
select SIFIVE_PDMA
select SIFIVE_PLIC
- select CADENCE_SDHCI
+ select SIFIVE_UART
+ select SIFIVE_U_OTP
+ select SIFIVE_U_PRCI
+ select UNIMP
+
+config SPIKE
+ bool
+ select HTIF
+ select MSI_NONBROKEN
+ select SIFIVE_CLINT
+ select SIFIVE_PLIC
--
2.28.0
^ permalink raw reply related [flat|nested] 34+ messages in thread* Re: [PULL 00/30] riscv-to-apply queue
2020-09-10 18:09 [PULL 00/30] riscv-to-apply queue Alistair Francis
` (29 preceding siblings ...)
2020-09-10 18:09 ` [PULL 30/30] hw/riscv: Sort the Kconfig options in alphabetical order Alistair Francis
@ 2020-09-13 21:30 ` Peter Maydell
30 siblings, 0 replies; 34+ messages in thread
From: Peter Maydell @ 2020-09-13 21:30 UTC (permalink / raw)
To: Alistair Francis; +Cc: Alistair Francis, QEMU Developers
On Thu, 10 Sep 2020 at 19:20, Alistair Francis <alistair.francis@wdc.com> wrote:
>
> The following changes since commit 9435a8b3dd35f1f926f1b9127e8a906217a5518a:
>
> Merge remote-tracking branch 'remotes/kraxel/tags/sirius/ipxe-20200908-pull-request' into staging (2020-09-08 21:21:13 +0100)
>
> are available in the Git repository at:
>
> git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200910
>
> for you to fetch changes up to 7595a65818ea9b49c36650a8c217a1ef9bd6e62a:
>
> hw/riscv: Sort the Kconfig options in alphabetical order (2020-09-09 15:54:19 -0700)
>
> ----------------------------------------------------------------
> This PR includes multiple fixes and features for RISC-V:
> - Fixes a bug in printing trap causes
> - Allows 16-bit writes to the SiFive test device. This fixes the
> failure to reboot the RISC-V virt machine
> - Support for the Microchip PolarFire SoC and Icicle Kit
> - A reafactor of RISC-V code out of hw/riscv
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/5.2
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 34+ messages in thread